View UM10562_4638660.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

UM10562 lpc408x/407x user manual rev. 1 ? 13 september 2012 user manual document information info content keywords lpc4088fbd208, lpc4088fet208, lpc4088fet180, lpc4088fbd144, lpc4078fbd208, lpc4078fet208, lpc4078fbd144, lpc4078fbd80, lpc4076fet180, lpc4074fbd144, lpc4074fbd80, arm, arm cortex-m4 , 32-bit, usb, ethernet, lcd, can, i 2 c, i 2 s, flash, eeprom, microcontroller abstract lpc408x/407x user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 2 of 942 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors UM10562 lpc408x/407x user manual revision history rev date description 1 20120913 inital lpc408x/407x user manual version.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 3 of 942 1.1 introduction the lpc408x/407x is an arm cortex-m4 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. the cortex-m4 processor is a high-performance 32-bit processor with a 3-stage pipeline harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peri pherals. the cortex-m4 uses the thumb? instruction set, providing high code densit y and reduced program memory requirements. the cortex-m4 cpu also includes an internal prefetch unit that supports speculative branches. the lpc408x/407x adds a specializ ed flash memory accelerator to give optimal performance when executing code from flash. the lpc408x/407x is targeted to operate at up to a 120 mhz cpu frequency under worst case commercial conditions. the peripheral complement of the lpc408x/407x includes up to 512 kb of flash memory, up to 96 kb of data memory, 4,032 bytes of eeprom memory, an external memory controller for sdram and static memory access, an lcd panel controller, an ethernet mac, a high speed spi flash memory interface (spifi), a general purpose dma controller, a usb device/host/otg interf ace, 5 uarts, 3 ssp controllers, 3 i 2 c interfaces, an i 2 s serial audio interface, a 2-channel can interface, an sd card interface, an 8 channel 12-bit adc, a 10-bit dac, analog comparators, a motor control pwm, a quadrature encoder interface, 4 general purpose timers, a 6-output general purpose pwm, an ultra-low power rtc with separate battery supply and event monitor/recorder, a windowed watchdog timer, a crc calculation engine, up to 165 general purpose i/o pins, and more. UM10562 chapter 1: introductory information rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 4 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.2 features refer to section 1.4 for details of features for specific part numbers. ? functional replacement for lpc23xx and 24xx family devices. ? arm cortex-m4 processor, running at freque ncies of up to 120 mhz. the cortex-m4 executes the thumb?-2 instruction set for optimal performance and code size, including hardware division, single cycle multiply, and bit-field manipulation. a memory protection unit (mpu) sup porting eight regions is included. ? cortex-m4 built-in nested vector ed interrupt controller (nvic). ? cortex-m4 floating point unit (fpu), supporting single-precision floating-point computation functionality in compliance with the ansi/ieee stan dard 754-200 8. the fpu provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. it also performs a variet y of conversions between fixed-point, floating-point, and integer data formats. the fpu is not available on lpc4074 devices. ? up to 512 kb on-chip flash program memory with in-system programming (isp) and in-application programming (iap) capabilitie s. the combination of an enhanced flash memory accelerator and location of the flash memory on the cpu local code/data bus provides high code performance from flash. ? up to 96 kb on-chip sram includes: ? up to 64 kb of main sram on the cpu code/data bus for high-performance cpu access. ? up to two 16 kb sram blocks with separa te access paths for higher throughput. these sram blocks may be used for ethe rnet, usb, lcd, and dma memory, as well as for general purpose instruction and data storage. ? up to 4,032 bytes of on-chip eeprom. ? external memory controller provides suppor t for asynchronous st atic memory devices such as ram, rom and flash up to 64 mb, as well as dynamic memories such as single data rate sdram. ? eight channel general purpose dma controller (gpdma) on the ahb multilayer matrix that can be used with the ssp, i 2 s, uart, sd/mmc, crc engine, analog-to-digital and digital-to-analog conv erter peripherals, timer match signals, gpio, and for memory-to-memory transfers. ? multilayer ahb matrix interconnect prov ides a separate bus for each ahb master. ahb masters include the cpu, general purp ose dma controller, ethernet mac, lcd controller, and the usb interface. this inte rconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time. ? split apb bus allows for higher throughput with fewer stalls between the cpu and dma. a single level of write buffering allows the cpu to continue without waiting for completion of apb writes if the apb was not already busy. ? lcd controller, supporting both super-twisted nematic (stn) and thin-film transistor (tft) displays. the lcd controller is not available on lpc407x devices. ? dedicated dma controller. ? selectable display resolution (up to 1024 768 pixels).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 5 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? supports up to 24-bit true-color mode. ? serial interfaces: ? ethernet mac with mii/rmii interface and dedicated dma controller. ? usb 2.0 full-speed controller that can be configured for either device, host, or otg operation with an on-chip phy for dev ice and host functions and a dedicated dma controller. usb host and otg are not available on lpc4074 devices. ? five uarts with fractional baud rate generation, internal fifos, irda, dma support, and rs-485/eia-485 support on most lpc408x/407x devices. uart1 also has a full set of modem handshaking signals. uart4 includes a synchronous mode and a smart card mode supporting iso 7816-3. uart4 is not available on lpc4074 devices. ? three ssp controllers with fifo and mu lti-protocol capa bilities. the ssp interfaces can be used with the gpdma controller. ? three enhanced i 2 c-bus interfaces, one with an open-drain output supporting the full i 2 c specification and fast mode plus with data rates of 1mbit/s, two with standard port pins. enhancements include multiple address recognition and monitor mode. ? two-channel can controller. ? i 2 s (inter-ic sound) interface for digital audio input or output, with fractional rate control. the i 2 s interface can be used with the gpdma. the i 2 s interface supports 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. ? spifi (spi flash interface). this interfac e uses an spi bus superset with 4 data lines to access off-chip quad spi flash memory at a much higher rate than is possible using standard spi or ssp interfaces. the spif i function allows memory mapping the contents of the off-chip spi flash memory such that it can be executed as if it were on-chip code memo ry. supports spi memories with 1 or 4 data lines. ? other peripherals: ? sd card interface that also supports mmc cards. the sd card interface is not available on lpc4074 devices. ? general purpose i/o (gpio) pins with configurable pull-up/down resistors, open drain mode, and repeater mode. all gpios are located on an ahb bus for fast access, and support cortex-m4 bit-banding. gpios can be accessed by the general purpose dma controller. any pin of ports 0 and 2 can be used to generate an interrupt. there are 165 gpios on 208-pin packages, 141 gpios on 180-pin packages, and 109 gpios on 144-pin packages. ? 12-bit analog-to-digital co nverter (adc) with input multiplexing among eight pins, conversion rates up to 400 khz, and multip le result registers. the 12-bit adc can be used with the gpdma controller. ? 10-bit digital-to-analog converter (dac) with dedicated conversion timer and dma support. ? dual analog comparator with multiple selectable input s, selectable internal reference voltages, and versatile interr upt generation. the comparators are not available on lpc4074 devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 6 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. each timer block has an external count input. specific timer events can be selected to generate dma requests. ? one motor control pwm with support for thre e-phase motor control. ? quadrature encoder interface that can monitor one external quadrature encoder. the qei is not available on lpc4074 devices. ? two standard pwm/timer blocks wit h external count input option. ? real-time clock (rtc) with a separate po wer domain. the rtc is clocked by a dedicated rtc oscillator. the rtc block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off. battery power can be supplied from a standard 3 v lithium button cell. the rtc will continue working when the battery voltage drops to as low as 2.1 v. an rtc interrupt can wake up the cpu from any reduced power mode. ? event monitor/recorder that can capture the rtc value when an event occurs on any of 3 inputs. the event identification and the time it occurred are stored in registers. the event monitor/recorder is in the rtc power domain, and can therefore operate as long as there is rtc power. ? windowed watchdog timer (wwdt). windowed operation, dedicated internal oscillator, watchdog warning in terrupt, and safety features. ? crc engine block can calculate a crc on supplied data using 1 of 3 standard polynomials. the crc engine can be used in conjunction with the dma controller to generate a crc witho ut cpu involvement in the data transfer. ? cortex-m4 system tick timer, including an external clock input option. ? standard jtag test/debug interface as well as serial wire debug and serial wire trace port options. ? emulation trace module supports real-time trace. ? single 3.3 v power supply (2.4 v to 3.6 v). temperature range of -40 c to 85 c. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? power savings for operation at or below 100 mhz by reducing on-chip regulator output. ? four external interrupt inputs configurable as edge/level sensitive. all pins on port0 and port2 can be used as edge sensitive interrupt sources. ? non-maskable inte rrupt (nmi) input. ? clock output function th at can reflect the main oscillator clock, irc clock, rtc clock, cpu clock, usb clock, spifi clock, or the watchdog timer clock. ? the wakeup interrupt controlle r (wic) allows the cpu to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes. ? processor wake-up from power-down mode via any interrupt able to operate during power-down mode (includes external interrupts, rtc interrupt, usb activity, ethernet wake-up interrupt, can bus activity , port0/2 pin interrupt, and nmi). ? brownout detect with separate threshold for interrupt and forced reset. ? on-chip power-on reset (por). ? on-chip crystal oscillator with an op erating range of 1 mhz to 25 mhz.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 7 of 942 nxp semiconductors UM10562 chapter 1: introductory information ? 12 mhz internal rc oscillator (irc) trimmed to 1% accuracy that can optionally be used as a system clock. ? an on-chip pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the main oscillator or the internal rc oscillator. ? a second, dedicated pll may be used for the usb and/or spifi interfaces in order to allow added flexibility for the main pll settings. ? versatile pin function selection feature a llows many possibilities for using on-chip peripheral functions. ? boundary scan for simplified board testing. ? unique device serial number for identification purposes. ? available as 208-pin lqfp, 208-pin tfbga, 180-pin tfbga, 144-pin lqfp, 80-pin lqfp packages. 1.3 applications ? communications ? point-of-sale terminals, web servers, multi-protocol bridges ? industrial/medical ? automation controllers, application control, robotic controls, hvac, plc, inverters, circuit breakers, medical scanning, security monitoring, motor drive, video intercom ? consumer/appliance ? audio, mp3 decoders, alarm systems, displays, printers, scanners, small appliances, fitness equipment ? automotive ? aftermarket, car alarms , gps/fleet monitor
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 8 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.4 ordering information 1.4.1 part options summary [1] all types include spifi, event recorder , 2 can channels, 3 ssp interfaces, 3 i 2 c interfaces, i2s, dac, and an 8-channel 12-bit adc. [2] 96kb = 64kb main + 32kb peripheral sram; 80kb = 64kb main + 16kb peripheral sram; 40kb = 32kb main + 8kb peripheral sram. [3] devices that include ethernet in packages with 180 pins and greater support both mii and rmii. smaller packages support only rmii. [4] maximum data bus width for each package, smaller widths may al so be used. on 180-pin packages, the external bus is limited t o 16 bits. on 144-pin packages, the external bus is limited to 8 bits. 80-pin devic es do not support an external bus. table 1. ordering information type number package name description version lpc4088 lpc4088fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 lpc4088fet208 tfbga208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 0.7 mm sot950-1 lpc4088fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4088fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4078 lpc4078fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm sot459-1 lpc4078fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4078fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4078fbd80 lqfp80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm sot315-1 lpc4076 lpc4076fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls; body 12 12 0.8 mm sot570-2 lpc4074 lpc4074fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm sot486-1 lpc4074fbd80 lqfp80 plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm sot315-1 table 2. ordering options for lpc408x/407x parts type number [1] flash kb sram kb [2] eeprom bytes fpu ether- net [3] usb ext. bus [4] lcd uart qei sd comp- arators pack- age(s) lpc4088 512 96 4,032 y y h/o/d 32-bit/ 16-bit/ 8-bit y5yyy208, 180, 144 lpc4078 512 96 4,032 y y h/o/d 32-bit/ 16-bit/ 8-bit/ none n5yyy 208, 180, 144, 80 lpc4076 256 80 4,032 y y h/o/d 16-bit n 5 y y y 180 lpc4074 128 40 2,048 n n d none n 4 n n n 144, 80
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 9 of 942 nxp semiconductors UM10562 chapter 1: introductory information 5. simplified block diagram fig 1. lpc408x/407x simplified block diagram arm cortex-m4 with fpu jtag interface test/debug interface general purpose dma controller system bus d-code bus i-code bus clock generation, power control, and other system functions sram up to 96 kb boot rom 8 kb flash up to 512 kb rst xtalin xtalout clocks and controls flash accelerator ethernet 10/100 mac usb otg/ host/ device lcd panel interface ethernet phy interface usb bus or tranceiver lcd panel crc engine general purpose i/o ports eeprom up to 4 kb 120229 multilayer ahb matrix static / dynamic memory controller ethernet registers usb registers lcd registers 26-bit addr 32-bit data apb slave group 0 capture/match timer 0 & 1 watchdog osc illator windowed watchdog ssp1 uarts 0 & 1 can 1 & 2 12-bit adc pin connect block gpio interrupt control i 2 c 0 & 1 pwm0 & 1 apb slave group 1 note: - orange shaded peripheral blocks support general purpose dma. - yellow shaded peripheral blocks include a dedicated dma controller . uarts 2, 3, & 4 ssp0 & 2 system control dac external interrupts motor control pwm i 2 s i 2 c 2 sd card interface capture/match timer 2 & 3 quadrature encoder i/f rtc power domain 32 khz oscillator backup registers (20 bytes) ultra-low power regulator vbat alarm real time clock event inputs event monitor/ recorder spi flash interface analog comparators
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 10 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.6 architectural overview the arm cortex-m4 includes three ahb-lite buses, one system bus and the i-code and d-code buses which are faster and are used similarly to tightly coupled memory interfaces: one bus dedicated for instructio n fetch (i-code) and one bus for data access (d-code). the use of two core buses allows for simultaneous operations if concurrent operations target different devices. the lpc408x/407x uses a multi-layer ahb ma trix to connect the cortex-m4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals on different slaves ports of the matrix to be accessed simultaneously by different bus masters. details of the multilayer matrix connections are shown in figure 2 . apb peripherals are connected to the cpu via two apb buses using separate slave ports from the multilayer ahb matrix. this allows for better perfor mance by reducing collisions between the cpu and the dma controller. the apb bus bridge s are configured to buffer writes so that the cpu or dma controller can write to apb devices without always waiting for apb write completion. 1.7 arm cortex-m4 processor the arm cortex-m4 is a general purpose 32-bit microprocessor, which offers high performance and very low power consumpt ion. the cortex-m4 offers a thumb-2 instruction set, low in terrupt latency, interruptible/cont inuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller, and multiple core buses capable of simultaneous accesses. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. information about cortex-m4 config uration options can be found in section 40.1 . 1.8 on-chip flash memory system the lpc408x/407x contains up to 512 kb of on-chip flash memory. a flash memory accelerator maximizes performance for cpu accesses. this memory may be used for both code and data storage. programming of the flash memory may be accomplished in several ways. it may be pr ogrammed in system via the serial port. the application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field fi rmware upgrades, etc. 1.9 on-chip static ram the lpc408x/407x contains up to 96 kb of on-chip static ram memory. up to 64 kb of sram, accessible by the cpu and the general purpose dma controller, is on a higher-speed bus. up to 32 kb sram is provided in up to two additional 16 kb sram blocks for use primarily for peripheral da ta. when both srams are present, they are situated on separate slave ports on the ahb multilayer matrix.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 11 of 942 nxp semiconductors UM10562 chapter 1: introductory information this architecture allows the possibility for cpu and dma accesses to be separated in such a way that there are few or no delays for the bus masters. it also allows separation of data for different peripherals functions, in order to improve system performance. for example, lcd dma can be occurring in one sram while ethernet dma is occurring in another, all while the cpu is using the main sram for data and/or instruction access. 1.10 on-chip eeprom the lpc408x/407x contains up to 4,03 2 bytes of on-chip eeprom memory. the eeprom is accessible only by the cpu.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 12 of 942 nxp semiconductors UM10562 chapter 1: introductory information 1.11 detailed block diagram fig 2. lpc408x/407x block diagram, cpu and buses multilayer ahb matrix arm cortex-m4 with fpu ahb to apb bridge ahb to apb bridge jtag interface periph. sram up to 16 kb test/debug interface general purpose dma controller system bus d-code bus i-code bus clock generation, power control, and other system functions main sram up to 64 kb boot rom 8 kb flash up to 512 kb rst xtalin xtalout apb slave group 1 note: - orange shaded peripheral blocks support general purpose dma. - yellow shaded peripheral blocks include a dedicated dma controller. apb slave group 0 voltage regulator clocks and controls internal power vdd clk out capture/match timer 0 & 1 flash accelerator driver rom 16 kb ethernet 10/100 mac usb otg/ host/dev lcd panel interface static / dynamic memory controller d[31:0] a[25:0] control periph. sram up to 16 kb ethernet phy interface usb bus or tranceiver lcd panel watchdog osc illator windowed watchdog ethernet registers gpdma registers crc engine usb registers lcd registers hs gpio mem ctl registers ssp1 uarts 0 & 1 can 1 & 2 12-bit adc pin connect block gpio interrupt control i 2 c 0 & 1 pwm0 & 1 uarts 2, 3, & 4 ssp0 & 2 system control dac external interrupts motor control pwm i 2 s i 2 c 2 sd card interface capture/match timer 2 & 3 quadrature encoder i/f eeprom up to 4 kb 120621 rtc power domain 32 khz oscillator backup registers (20 bytes) ultra-low power regulator vbat alarm real time clock event inputs event monitor/ recorder spi flash interface
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 13 of 942 2.1 memory map and peripheral addressing the arm cortex-m4 processor has a single 4 gb address space. the following table shows how this space is used on the lpc408x/407x. [1] can be up to 256 mb, upper address 0x8fff ffff, if the address shift mode is enabled. see scs register bit 0 ( section 3.3.7.1 ). [2] can be up to 128 mb, upper address 0x97ff ffff, if t he address shift mode is enabled. see scs register bit 0 ( section 3.3.7.1 ). UM10562 chapter 2: lpc408x/407x memory map rev. 1 ? 13 september 2012 user manual table 3. memory usage and details address range general use address range details and description 0x0000 0000 to 0x1fff ffff on-chip non-volatile memory 0x0000 0000 - 0x0007 ffff for devices with 512 kb of flash memory. 0x0000 0000 - 0x0003 ffff for devices with 256 kb of flash memory. 0x0000 0000 - 0x0001 ffff for devices with 128 kb of flash memory. on-chip sram 0x1000 0000 - 0x1000 ffff for devices with 64 kb of main sram. 0x1000 0000 - 0x1000 7fff for devices with 32 kb of main sram. boot rom 0x1fff 0000 - 0x1fff 7fff 8 kb boot rom with flash services. driver rom 0x1fff 8000 - 0x1fff 1fff 16 kb driver rom 0x2000 0000 to 0x3fff ffff on-chip sram (typically used for peripheral data) 0x2000 0000 - 0x2000 1fff peripheral sram - bank 0 (first 8 kb) 0x2000 2000 - 0x2000 3fff peripheral sram - bank 0 (second 8 kb) 0x2000 4000 - 0x2000 7fff peripheral sram - bank 1 (16 kb) ahb peripherals 0x2008 0000 - 0x200b ffff see section 2.3.1 for details spifi buffer space 0x2800 0000 - 0x28ff ffff spifi memory mapped access space 0x4000 0000 to 0x7fff ffff apb peripherals 0x4000 0000 - 0x4007 ffff apb0 peripherals, up to 32 peripheral blocks of 16 kb each. 0x4008 0000 - 0x400f ffff apb1 peripherals, up to 32 peripheral blocks of 16 kb each. 0x8000 0000 to 0xdfff ffff off-chip memory via the external memory controller four static memory chip selects: 0x8000 0000 - 0x83ff ffff static memory chip select 0 (up to 64 mb) [1] 0x9000 0000 - 0x93ff ffff static memory chip select 1 (up to 64 mb) [2] 0x9800 0000 - 0x9bff ffff static memory chip select 2 (up to 64 mb) 0x9c00 0000 - 0x9fff ffff static memory chip select 3 (up to 64 mb) four dynamic memory chip selects: 0xa000 0000 - 0xafff ffff dynamic memory chip select 0 (up to 256mb) 0xb000 0000 - 0xbfff ffff dynamic memory chip select 1 (up to 256mb) 0xc000 0000 - 0xcfff ffff dynamic memory chip select 2 (up to 256mb) 0xd000 0000 - 0xdfff ffff dynamic memory chip select 3 (up to 256mb) 0xe000 0000 to 0xe00f ffff cortex-m4 private peripheral bus 0xe000 0000 - 0xe00f ffff cortex-m4 related functions, includes the nvic and system tick timer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 14 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.2 memory maps the lpc408x/407x incorporates several distinct memory regions, shown in the following figures. figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping, which is described later in this section. figure 3 and ta b l e 5 show different views of the peripheral address space. the ahb peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. the apb peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. each peripheral of either type is allocated 16 kilobytes of space. this allows simplifying the address decoding for each peripheral.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 15 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map fig 3. system memory map 31-24 23 22-19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x4008 0000 0x4006 0000 0x4005 c000 0x4004 c000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 c000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 c000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 c000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 c000 0x4000 8000 0x4000 4000 0x4000 0000 reserved i2c1 reserved can 2 can 1 can common can af registers can af ram adc ssp1 pin connect gpio interrupts rtc comparators i2c0 pwm1 pwm0 uart1 uart0 timer1 timer0 watchdog timer apb0 peripherals 7 6 5 4 3 2 1 0 0x200a 0000 0x2009 c000 0x2009 8000 0x2009 4000 0x2009 0000 0x2008 c000 0x2008 8000 0x2008 4000 0x2008 0000 emc registers gpio spifi registers crc engine usb lcd controller ethernet gp dma ctlr ahb peripherals i-code and d-code memory space 31 30-17 16 15 14 13-12 11 10 9 8 7 6 5 4 3 2 1-0 0x4010 0000 0x400f c000 0x400c 4000 0x400c 0000 0x400b c000 0x400b 8000 0x400b 0000 0x400a c000 0x400a 8000 0x400a 4000 0x400a 0000 0x4009 c000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 c000 0x4008 8000 0x4008 0000 system control reserved sd card qei motor ctl pwm reserved ssp2 i2s uart4 i2c2 uart3 uart2 timer3 timer2 dac ssp0 reserved apb1 peripherals 0.5 gb 1 gb 2 gb 4 gb active interrupt vectors 0x0400 0x0000 reserved private peripheral bus external memory (4 dynamic chip selects) apb peripheral group 1 apb peripheral group 0 reserved reserved reserved reserved reserved reserved reserved reserved ahb peripherals boot rom and driver rom external memory (4 static chip selects) apb peripheral bit-band addressing spifi memory mapped space peripheral sram 1 peripheral sram 0 64 kb main sram 512 kb flash memory memory space 0xffff ffff 0xe010 0000 0xe004 0000 0xe000 0000 0xa000 0000 0x8000 0000 0x4400 0000 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2900 0000 0x2800 0000 0x200c 0000 0x2000 4000 0x2000 0000 0x1fff 0000 0x1001 0000 0x1000 0000 0x0008 0000 0x0000 0000 0x2400 0000 0x2200 0000 0x2008 0000 peripheral sram bit-band addressing 120420
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 16 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.3 on-chip peripherals all peripheral register addresses are word aligned (to 32-bit boundaries) regardless of their size. this eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit) accesses to occur at smaller boundaries. an implication of this is that word and half-word registers must be accessed all at once. for example, it is not possible to read or write the upper byte of a word register separately. 2.3.1 ahb peripherals the following table shows the addresses of periph eral functions that reside directly on the ahb bus matrix. complete register descripti ons may be found in the relevant chapters. 2.3.2 apb peripheral addresses the following table shows the address maps of the 2 apb buses. apb peripherals do not use all of the 16 kb space allocated to them. typically each device?s registers are "aliased" or repeated at multiple locations within each 16 kb range. table 4. ahb peripherals and base addresses ahb peripheral address range peripheral name 0 0x2008 0000 to 0x2008 3fff general purpose dma controller 1 0x2008 4000 to 0x2008 7fff ethernet mac 2 0x2008 8000 to 0x2008 bfff lcd controller 3 0x2008 c000 to 0x2008 ffff usb interface 4 0x2009 0000 to 0x2009 3fff crc engine 5 0x2009 4000 to 0x2009 7fff spifi 6 0x2009 8000 to 0x2009 bfff gpio 7 0x2009 c000 to 0x2009 ffff external memory controller 8 to 15 0x200a 0000 to 0x200b ffff reserved table 5. apb0 peripherals and base addresses apb0 peripheral base address peripheral name 0 0x4000 0000 watchdog timer 1 0x4000 4000 timer 0 2 0x4000 8000 timer 1 3 0x4000 c000 uart0 4 0x4001 0000 uart1 5 0x4001 4000 pwm0 6 0x4001 8000 pwm1 7 0x4001 c000 i 2 c0 8 0x4002 0000 comparators 9 0x4002 4000 rtc and event monitor/recorder 10 0x4002 8000 gpio interrupts 11 0x4002 c000 pin connect block 12 0x4003 0000 ssp1 13 0x4003 4000 adc
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 17 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.4 memory re-mapping the cortex-m4 incorporates a me chanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register contained in the cortex-m4. refer to the nvic description in section 5.4 and to the arm cortex-m4 user guide referr ed to in section 40.1 . boot rom re-mapping following a hardware reset, the boot rom is temporarily mapp ed to address 0. this is normally transparent to the user. however, if execution is halted immediately after reset by a debugger, it should correct the mapping for the user. see section 39.8 . 14 0x4003 8000 can acceptance filter ram 15 0x4003 c000 can acceptance filter registers 16 0x4004 0000 can common registers 17 0x4004 4000 can controller 1 18 0x4004 8000 can controller 2 19 to 22 0x4004 c000 to 0x4005 8000 reserved 23 0x4005 c000 i 2 c1 24 to 31 0x4006 0000 to 0x4007 c000 reserved table 6. apb1 peripherals and base addresses apb1 peripheral base address peripheral name 0 to 1 0x4008 0000 to 0x4008 4000 reserved 2 0x4008 8000 ssp0 3 0x4008 c000 dac 4 0x4009 0000 timer 2 5 0x4009 4000 timer 3 6 0x4009 8000 uart2 7 0x4009 c000 uart3 8 0x400a 0000 i 2 c2 9 0x400a 4000 uart4 10 0x400a 8000 i 2 s 11 0x400a c000 ssp2 12 to 13 0x400b 0000 to 0x400b 4000 reserved 14 0x400b 8000 motor control pwm 15 0x400b c000 quadrature encoder interface 16 0x400c 0000 sd card interface 17 to 30 0x400d 0000 to 0x400f 8000 reserved 31 0x400f c000 system control table 5. apb0 peripherals and base addresses apb0 peripheral base address peripheral name
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 18 of 942 nxp semiconductors UM10562 chapter 2: lpc408x/407x memory map 2.5 ahb arbitration the multilayer ahb matrix arbitrates between several masters, only if they attempt to access the same matrix slave port at the sa me time. by default, the cortex-m4 d-code bus has the highest priority, followed by the i-code bus. all other masters share a lower priority. the default priority can be altered by the user if care is taken. this may be particularly useful if the lcd interface is used and it has difficulty getting sufficient data. 2.5.1 matrix arbitration register the matrix arbitration regist er provides the ability to c hange the default ahb matrix arbitration priorities. the values used for the various priorities are 3 = highest, 0 = lowest. an example of a way to give priority to the lcd dma is to use the value 0x0000 0c09. the gives the lcd highest priority, d-code second priority, i-code third priority, and all others lowest priority. where in the memory space code and various types of data are located can be managed to help minimize the need for arbitration and possible starvation of any of the bus masters, as well as a need for changing the default priorities. for instance, lcd refresh from off-chip memory connected to the emc, while also executing off-chip code via the emc can cause a great deal of arbitration. table 7. matrix arbitration register (ma trix_arb - 0x400f c188) bit description bit symbol description reset value 1:0 pri_icode i-code bus priority. should be lower than pri_dcode for proper operation. 0x1 3:2 pri_dcode d-code bus priority. 0x3 5:4 pri_sys system bus priority. 0 7:6 pri_gpdma general purpose dma controller priority. 0 9:8 pri_eth ethernet dma priority. 0 11:10 pri_lcd lcd dma priority. 0 13:12 pri_usb usb dma priority. 0 15:14 - reserved. read value is undefined, only zero should be written. na 16 rom_lat rom latency select. should always be 0. 0 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 19 of 942 3.1 introduction the system control block includes several sy stem features and control registers for a number of functions that are not related to specific peripheral devices. these include: ? chip reset (see section 3.4 ) ? peripheral reset control (see section 3.5 ) ? brown-out detection (see section 3.6 ) ? external interrupt inputs (see section 3.7 ) each type of function has its own registers if any are required and unneeded bits are defined as reserved in orde r to allow future expansion. 3.1.1 summary of clocking and power control functions this section describes the generation of th e various clocks needed for device operation, and options of clock source selection, as we ll as power control and wake-up from reduced power modes. functions described in the following subsections include: ? oscillators (see section 3.8 ) ? plls (see section 3.10 ) ? clock selection and dividers (see section 3.11 ) ? power control (see section 3.12 ) ? wake-up timer (see section 3.13 ) ? external clock output (see section 3.14 ) UM10562 chapter 3: lpc408x/407x system and clock control rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 20 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.2 pin description ta b l e 8 shows pins that are associated with system control block functions. fig 4. clock generation cclk pclk divide select pclksel[4:0] pclk usb_clk spifi_clk pll1 settings pll1con, pll1cfg alt_pll_clk pll0 settings pll0con, pll0cfg sysclk pll_clk system clock select clksrcsel[0] 1 0 irc_clk osc_clk cpu divide select cclksel[4:0] usb divide select usbclksel[4:0] spifi divide select spificlksel[4:0] emc_clk emc divide select emcclksel[0] 01 10 00 usb clock select usbclksel[9:8] sysclk pll_clk alt_pll_clk cpu clock divider peripheral clock divider emc clock divider usb clock divider spifi clock divider pll1 (alt pll) pll0 (main pll) cpu clock select cclksel[8] sysclk pll_clk 1 0 01 10 00 spifi clock select spificlksel[9:8) sysclk pll_clk alt_pll_clk 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 21 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 8. pin summary pin name pin direction pin description eint0 input external inte rrupt input 0 - an active low/high level or falling/rising edge general purpose interrupt input. this pin may be used to wake up the processor from sleep, deep-sleep, or power-down modes. eint1 input external inte rrupt input 1 - see the eint0 description above. eint2 input external inte rrupt input 2 - see the eint0 description above. eint3 input external inte rrupt input 3 - see the eint0 description above. reset input external reset input - a low on this pin resets the chip, causing i/o ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 22 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3 register description all registers, regardless of si ze, are on word address boundaries. details of the registers appear in the description of each function. table 9. register overview: system control (base address 0x400f c000) name access address offset description reset value refer- ence pll registers 3.3.1 pllcon0:1 r/w 0x080; 0xa0 pll0 and pll1 control registers 0 3.3.1.1 pllcfg0:1 r/w 0x084; 0xa4 pll0 and pll1 configuration registers 0 3.3.1.2 pllstat0:1 ro 0x088; 0xa8 pll0 and pll1 status registers 0 3.3.1.3 pllfeed0:1 wo 0x08c; 0xac pll0 and pll1 feed registers na 3.3.1.5 power control 3.3.2 pcon r/w 0x0c0 power control register 0 3.3.2.1 pconp r/w 0x0c4 power control for peripherals 0x0408 829e 3.3.2.2 pconp1 r/w 0x0c8 power control for peripherals 1 0x8 3.3.2.2 pboost r/w 0x1b0 power boost register 0x3 3.3.2.3 clock selection and divider registers 3.3.3 emcclksel r/w 0x100 external memory controller clock selection register 0 3.3.3.1 cclksel r/w 0x104 cpu clock selection register 1 3.3.3.2 usbclksel r/w 0x108 usb clock selection register 0 3.3.3.3 clksrcsel r/w 0x10c clock so urce select register 0 3.3.3.4 pclksel r/w 0x1a8 peripheral clock selection register 0x10 3.3.3.5 spificlksel r/w 0x1b4 spifi cl ock selection register 0 3.3.3.6 external interrupts 3.3.4 extint r/w 0x140 external interrupt flag register 0 3.3.4.1 extmode r/w 0x148 external interrupt mode register 0 3.3.4.2 extpolar r/w 0x14c external interrupt polarity register 0 3.3.4.3 device and peripheral reset 3.3.5 rsid r/w 0x180 reset source identification register see ta b l e 2 8 3.3.5.1 rstcon0 r/w 0x1cc individual peripheral reset control bits 0 3.3.5.2 rstcon1 r/w 0x1d0 individual peripheral reset control bits 0 3.3.5.3 emc delay control and calibration 3.3.6 emcdlyctl r/w 0x1dc values for the 4 programmable delays associated with sdram operation. 0x210 3.3.6.1 emccal r/w 0x1e0 controls the calibration counter for programmable delays and returns the result value. 0x1f00 3.3.6.2 miscellaneous system control registers 3.3.7 scs r/w 0x1a0 system control and status 0 3.3.7.1 lcd_cfg r/w 0x1b8 lcd clock configuration register 0 3.3.7.2 cansleepclr r/w 0x110 allows clearing the current can channel sleep state as well as reading back that state. 0 3.3.7.3 canwakeflags r/w 0x114 indicates the wake-up state of the can channels. 0 3.3.7.4
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 23 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control usbintst r/w 0x1c0 usb interrupt status 0x8000 0000 3.3.7.5 dmacreqsel r/w 0x1c4 selects between alternative requests on dma channels 0 through 7 and 10 through 15. 0 3.3.7.6 clkoutcfg r/w 0x1c8 clock output configuration register 0 3.3.7.7 table 9. register overview: system control (base address 0x400f c000) name access address offset description reset value refer- ence
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 24 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.1 pll registers 3.3.1.1 pll control registers the pllcon registers contains the bits that enable and connect each pll. enabling a pll allows it to attempt to lock to the curr ent settings of the multiplier and divider values. changes to a pllcon register do not take ef fect until a correct pll feed sequence has been given for that pll (see section 3.3.1.5 and section 3.3.1.2 ). each pll must be set up, enabled, and lock established before it may be used as a clock source. the hardware does not insure that the pll is locked before it is selected nor does it automatically disconnect the pll if lock is lost during operation. 3.3.1.2 pll configuration registers the pllcfg register contains the pll multiplier and divider values. changes to the pllcfg register do not take effect until a correct pll feed sequence has been given (see section 3.3.1.5 ). calculations for the pll frequency, and multiplier and divider values are found in section 3.10.5 . table 10. pll control registers (pllcon[0:1] - ad dresses 0x400f c080 (pllcon0) and 0x400f c0a0 (pllcon1)) bit description bit symbol description reset value 0 plle pll enable. when one, and after a valid pll feed, this bit will activate the related pll and allow it to lock to the requested frequency. see pllstat register, table 12 . 0 31:1 - reserved. read value is undefined, only zero should be written. na table 11. pll configuration registers (pllcfg[0 :1] - addresses 0x400f c084 (pllcfg0) and 0x400f c0a4 (pllcfg1)) bit description bit symbol description reset value 4:0 msel pll multiplier value. supplies the value "m" in the pll frequency calculations. the value stored here is the m value minus 1. note: for details on selecting the right value for msel see section 3.10.4 . 0 6:5 psel pll divider value. supplies the value "p" in the pll frequency calculations. this value is encoded as follows: 00 (0x0) = divide by 1 01 (0x1) = divide by 2 10 (0x2) = divide by 4 11 (0x3) = divide by 8 note: for details on selecting th e right value for psel see section 3.10.4 . 0 31:7 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 25 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.1.3 pll status registers the read-only pllstat register provides the actual pll parameters that are in effect at the time it is read, as well as the pll status. pllstat may disagree with values found in pllcon and pllcfg because changes to those registers do not take effect until a proper pll feed has occurred (see section 3.3.1.5 ? pll feed registers ? ). 3.3.1.4 pll interrupts: plock0 and plock1 the plock bit in the pllstat regist er reflects the lock status of the related pll1. when the pll is first enabled, or when its parameters are changed, the pll requires some time to establish lock under the new conditions. the related plock bit can be monitored to determine when the pll may be connected for use. each plock bit is connected to the interrupt cont roller. this allows for software to turn on the pll and continue with other functions wi thout having to wait for the pll to achieve lock. when the interrupt occurs, the pll ma y be selected as a clock source, and the interrupt disabled. plock0 and plock1 appear as exception numbers 32 and 48 respectively in ta b l e 5 0 . note that each plock bit remains asserted whenever the related pll is locked, so if th e interrupt is used, the interrupt service routine must disable the interrupt prior to exiting. 3.3.1.5 pll feed registers a correct feed sequence must be written to the related pllfeed register in order for changes to the related pllcon and pllcfg registers to take effect. the feed sequence is: 1. write the value 0xaa to pllfeed. 2. write the value 0x55 to pllfeed. the two writes must be in the correct seq uence, and there must be no other register access in the same address space (0x400f c000 to 0x400f ffff) between them. because of this, it may be necessary to disable interrupts for the duration of the pll feed operation, if there is a poss ibility that an interrupt service routine coul d write to another table 12. pll status registers (pllstat[0:1] - addresses 0x400f c088 (pllstat0) and 0x400f c0a8 (pllstat1)) bit description bit symbol description reset value 4:0 msel read-back for the pll multiplier value. this is the value currently used by the related pll. 0 6:5 psel read-back for the pll divider value. this is the va lue currently used by the related pll. 0 7 - reserved. the value read from a reserved bit is not defined. na 8 plle_stat read-back for the pll enable bit. when one, the related pll is currently activated. when zero, the related pll is turned off. this bit is automatically cleared when power-down mode is activated. 0 9 - reserved. the value read from a reserved bit is not defined. na 10 plock reflects the pll lock status. when zero, the related pll is not locked. when one, the related pll is locked onto the requested frequency. 0 31:11 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 26 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control register in that space. if eith er of the feed values is incorrect, or one of the previously mentioned conditions is not me t, any changes to the pllcon or pllcfg register will not become effective. table 13. pll feed registers (pllfeed[0:1] - addresses 0x400f c08c (pllfeed0) and 0x400f c0ac (pllfeed1)) bit description bit symbol description reset value 7:0 pllfeed the pll feed sequence must be written to this register in order for the related pll?s configuration and control register changes to take effect. 0x00 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 27 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.2 power control 3.3.2.1 power mode control register controls for some reduced power modes and other power related controls are contained in the pcon register, as described in ta b l e 1 4 . [1] only one of these flags will be valid at a specific time. [2] hardware reset value only for a power-up of core power or by a brownout detect event. [3] hardware reset value only for a power-up event on vbat. table 14. power mode control register (pcon - address 0x400f c0c0) bit description bit symbol description reset value 0 pm0 power mode control bit 0. this bit controls entry to the power-down mode. see section 3.3.2.1.1 below for details. 0 1 pm1 power mode control bit 1. this bit controls entry to the deep power-down mode. see section 3.3.2.1.1 below for details. 0 2 bodrpm brown-out reduced power mode. when bodrpm is 1, the brown-out detect circuitry will be turned off when chip power-down mode or deep sleep mode is entered, resulting in a further reduction in power usage. however, the possibility of using brown-out detect as a wake-up source from the reduced power mode will be lost. when 0, the brown-out detect function remains active during power-down and deep sleep modes. see the system control block chapter for details of brown-out detection. 0 3 bogd brown-out global disable. when bogd is 1, the brown-out detect circuitry is fully disabled at all times, and does not consume power. when 0, the brown-out detect circuitry is enabled. see the system control block chapter for details of brown-out detection. note: the brown-out reset disable (bord, in this register) and the brown-out interrupt (see section 5.1 ) must be disabled when software changes the value of this bit. 0 4 bord brown-out reset disable. when bord is 1, the bod will not reset the device when the v dd(reg)(3v3) voltage dips goes below the bod reset trip level. the brown-out interrupt is not affected. when bord is 0, the bod reset is enabled. see the section 3.6 for details of brown-out detection. 0 7:3 - reserved. read value is undefined, only zero should be written. na 8 smflag sleep mode entry flag. set when the sleep mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 9 dsflag deep sleep entry flag. set when the deep sl eep mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 10 pdflag power-down entry flag. set when the power-down mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [2] 11 dpdflag deep power-down entry flag. set when the deep power-down mode is successfully entered. cleared by software writing a one to this bit. 0 [1] [3] 31:12 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 28 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.2.1.1 encoding of reduced power modes the pm1and pm0 bits in pcon allow entering reduced power modes as needed. the encoding of these bits allows backward comp atibility with devices th at previously only supported sleep and power-down modes. ta b l e 1 5 below shows the encoding for the three reduced power modes. 3.3.2.2 power control for peripherals registers the pconp registers allow turning off select ed peripheral functions for the purpose of saving power. this is accomplished by gating off the clock source to the specified peripheral blocks. a few peripheral functions cannot be turned off (i.e. the watchdog timer and the system control block). some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. these peripherals may contain a separate disable control that turns off additional circuitry to reduce power. when this is the case, the peripheral should be disabled internally first, then turned off using pconp, in order to get the greatest power savings. information on peripheral specific power saving features may be found in the chapter describing that peripheral. each bit in pconp controls one peripheral as shown in table 16 . if a peripheral control bit is 1, that peripheral is enabled. if a peripheral control bit is 0, that peripheral?s clock is disabled (gated off) to conserve power. for example if bit 19 is 1, the i 2 c1 interface is enabled. if bit 19 is 0, the i 2 c1 interface is disabled. important: valid data reads from a peripheral register and valid data writes to a peripheral register are possible only if that peripheral is enabled in the pconp register! table 15. encoding of reduced power modes pm1, pm0 description 00 execution of wfi or wfe enters either sleep or deep sleep mode as defined by the sleepdeep bit in the cortex-m4 system control register. 01 execution of wfi or wfe enters powe r-down mode if the sleepdeep bit in the cortex-m4 system control register is 1. 10 reserved, this setting should not be used. 11 execution of wfi or wfe enters deep power-down mode if the sleepdeep bit in the cortex-m4 system control register is 1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 29 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 16. power control for peripherals register (pconp - address 0x400f c0c4) bit description bit symbol description reset value 0 pclcd lcd controller power/clock control bit. 0 1 pctim0 timer/counter 0 power/clock control bit. 1 2 pctim1 timer/counter 1 power/clock control bit. 1 3 pcuart0 uart0 power/clock control bit. 1 4 pcuart1 uart1 power/clock control bit. 1 5 pcpwm0 pwm0 power/clock control bit. 0 6 pcpwm1 pwm1 power/clock control bit. 0 7pci2c0i 2 c0 interface power/clock control bit. 1 8 pcuart4 uart4 power/clock control bit. 0 9 pcrtc rtc and event monitor/recorder power/clock control bit. 1 10 pcssp1 ssp 1 interface power/clock control bit. 0 11 pcemc external memory controller power/clock control bit. 0 12 pcadc a/d converter (adc) power/clock control bit. note: clear the pdn bit in the ad0cr before clearing this bit, and set this bit before attempting to set pdn. 0 13 pccan1 can controller 1 power/clock control bit. 0 14 pccan2 can controller 2 power/clock control bit. 0 15 pcgpio power/clock control bit for iocon, gpio, and gpio interrupts. 1 16 pcspifi spi flash interface power/clock control bit. 0 17 pcmcpwm motor control pwm power/clock control bit. 0 18 pcqei quadrature encoder interface power/clock control bit. 0 19 pci2c1 i 2 c1 interface power/clock control bit. 1 20 pcssp2 ssp2 interface power/clock control bit. 0 21 pcssp0 ssp0 interface power/clock control bit. 0 22 pctim2 timer 2 power/clock control bit. 0 23 pctim3 timer 3 power/clock control bit. 0 24 pcuart2 uart 2 power/clock control bit. 0 25 pcuart3 uart 3 power/clock control bit. 0 26 pci2c2 i 2 c interface 2 power/clock control bit. 1 27 pci2s i 2 s interface power/clock control bit. 0 28 pcsdc sd card interface power/clock control bit. 0 29 pcgpdma gpdma function power/clock control bit. 0 30 pcenet ethernet block power/clock control bit. 0 31 pcusb usb interface power/clock control bit. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 30 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control note that the dac peripheral does not have a control bit in pconp. to enable the dac, its output must be selected to appear on the related pin, p0[26], by configuring the relevant iocon register. see section 7.4.1 . 3.3.2.3 power boost control register the power boost control register allows choosing between high-speed operation above 100 mhz, or power savings wh en operation is at 100 mhz or lower, by controlling the output of the main on-chip regulator. the boost feature is turned on when user code is first executed following reset. it ca n then be turned off by user code if th e cpu clock rate will always be at or below 100 mhz, thus savi ng power that is only needed for operation above 100 mhz. details are show in table 18 . table 17. power control for peripherals register (pconp1 - address 0x400f c0c8) bit description bit symbol description reset value 2:0 - reserved. read value is undefined, only zero should be written. na 3 pccmp comparator power/clock control bit. 1 31:4 - reserved. read value is undefined, only zero should be written. na table 18. power boost control register (pboost - address 0x400f c1b0) bit description bit symbol description reset value 1:0 boost boost control bits. 00 : boost is off, operation must be below 100 mhz. 11 : boost is on, operation up to 120 mhz is supported. other values are not allowed. 0x3 31:2 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 31 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3 clock selection a nd divider registers 3.3.3.1 emc clock selection register the emcclksel register controls division of the clock before it is used by the emc. the emc uses the same base clock as the cp u and the apb peripherals. the emc clock can be the same as the cpu clock, or half that. this is intended to be used primarily when the cpu is running faster than the external bus can support. 3.3.3.2 cpu clock selection register the cclksel register controls selection of the clock used as the main pll input, and also controls the division of the pll0 output before it is used by the cpu. when pll0 is bypassed, the division may be by 1. when pll0 is running, the output must be divided in order to bring the cpu clock frequency (cclk) within operating limits. a 5-bit divider allows a range of options, including slowing cpu operation to a low rate for temporary power savings without turning off pll0. note that the cpu clock rate should not be set lower than the peripheral clock rate. the two clock sources that may be chosen to drive pll0 and ultimately the cpu and on-chip peripheral devices ar e the main oscillator and the inter nal rc oscillator. the clock source selection for pll0 can only be changed safely when pll0 is not being used. for a detailed description of how to cha nge the clock source in a system using pll0 see section 3.10.7 ? pll configuration examples ? . note the following restrictions rega rding the choice of clock sources: ? the irc oscillator should not be used (via pll0 ) as the clock s ource for the usb subsystem. ? the irc oscillator should not be used (via pll0 ) as the clock s ource for the can controllers if the can baud rate is higher than 100 kbit/s. table 19. emc clock selection register (emcclksel - address 0x400f c100) bit description bit symbol value description reset value 0 emcdiv selects the emc clock rate relative to the cpu clock. 0 0 the emc uses the same clock as the cpu. 1 the emc uses a clock at half the rate of the cpu. 31:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 32 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3.3 usb clock selection register the usbclksel register controls selection of the clock used for the usb subsystem, and also controls the division of the that clock before it is used by the usb. the output of the selected pll must be divided in order to bring the usb clock frequency to 48 mhz with a 50% duty cycle. a divider allows obtaining the correct usb clock from any even multiple of 48 mhz (i.e. any multiple of 96 mhz) within the pll operating range. remark: a clock derived from the internal rc osc illator should not be used to clock the usb subsystem. table 20. cpu clock selection register (cclksel - address 0x400f c104) bit description bit symbol value description reset value 4:0 cclkdiv selects the divide value for creating the cpu clock (cclk) from the selected clock source. 0 = the divider is turned off., no clock will be provided to the cpu. this setting should typically not be used, the cpu w ill be halted and a reset will be required to restore operation. 1 = the input clock is divided by 1 to produce the cpu clock. 2 = the input clock is divided by 2 to produce the cpu clock. 3 = the input clock is divided by 3 to produce the cpu clock. ... 31 = the input clock is divided by 31 to produce the cpu clock. 0x01 7:5 - reserved. read value is undefined, only zero should be written. na 8 cclksel selects the input clock for the cpu clock divider. 0 0 sysclk is used as the input to the cpu clock divider. 1 the output of the main pll is used as the input to the cpu clock divider. 31:9 - reserved. read value is undefined, only zero should be written. na table 21. usb clock selection register (usb clksel - address 0x400f c108) bit description bit symbol value description reset value 4:0 usbdiv selects the divide value for creating the usb clock from the selected pll output. only the values shown below can produce even number multiples of 48 mhz from the pll. warning: improper setting of this value will result in incorrect operation of the usb interface. only the main oscillator in conjunction with either pll0 or pll1 can provide a clock that meets usb accuracy and jitter specifications. other values cannot produce the 48 mhz clock required for usb operation. 0 0x0 the divider is turned off, no clock will be provided to the usb subsystem. 0x1 the selected output is divided by 1. the pll output must be 48 mhz. 0x2 the selected output is divided by 2. the pll output must be 96 mhz. 0x3 the selected output is divided by 3. the pll output must be 144 mhz. 7:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 33 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.3.4 clock source selection register the clksrcsel register controls selecti on of the clock used for sysclk and pll0. 3.3.3.5 peripheral clock selection register the pclksel register contro ls the base clock used fo r all apb peripherals. a clock divider allows a range of frequencies to be used. note that the peripheral clock rate should not be set higher than the cpu clock rate. 3.3.3.6 spifi clock selection register the spificlksel register controls selection of the clock used for the spifi, and also controls the division of that clock before it is used by the spifi. if a pll is used as the spifi clock source, its output must be divided in order to bring the frequency down to one that will work with the spifi. a 5-bit divide r allows a range of fr equencies to be used. 9:8 usbsel selects the input clock for the usb clock divider. 0 0x0 sysclk is used as the input to the u sb clock divider. when this clock is selected, the usb can be accessed by software but cannot perform usb functions. 0x1 the output of the main pll is used as the input to the usb clock divider. 0x2 the output of the alt pll is used as the input to the usb clock divider. 0x3 reserved, this setting should not be used. 31:10 - reserved. read value is undefined, only zero should be written. na table 21. usb clock selection register (usb clksel - address 0x400f c108) bit description bit symbol value description reset value table 22. clock source selection register (clksrcsel - address 0x400f c10c) bit description bit symbol value description reset value 0 clksrc selects the clock source for sysclk and pll0 as follows: 0 0 selects the internal rc oscillator as the sysclk and pll0 clock source (default). 1 selects the main oscillator as the sysclk and pll0 clock source. 31:1 - reserved. read value is undefined, only zero should be written. na table 23. peripheral clock selection register (pclksel - address 0x400f c1a8) bit description bit symbol description reset value 4:0 pclkdiv selects the divide value for the clock used for all apb peripherals. 0 = the divider is turned off., no clo ck will be provided to apb peripherals. 1 = the input clock is divided by 1 to produce the apb peripheral clock. 2 = the input clock is divided by 2 to produce the apb peripheral clock. 3 = the input clock is divided by 3 to produce the apb peripheral clock. 4 = the input clock is divided by 4 to produce the apb peripheral clock. other values = not supported. 0x04 31:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 34 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 24. spifi clock selection register (spi ficlksel - address 0x400f c1b4) bit description bit symbol value description reset value 4:0 spifidiv selects the divide value for creating the spifi clock from the selected clock source. 0 = the divider is turned off., no clock will be provided to the spifi. 1 = the input clock is divided by 1 to produce the spifi clock. 2 = the input clock is divided by 2 to produce the spifi clock. 3 = the input clock is divided by 3 to produce the spifi clock. ... 31 = the input clock is divided by 31 to produce the spifi clock. 0 7:5 - reserved. read value is undefined, only zero should be written. na 9:8 spifisel selects the input clock for the usb clock divider. 0 0x0 sysclk is used as the input to the spifi clock divider. 0x1 the output of the main pll is used as the input to the spifi clock divider. 0x2 the output of the alt pll is used as the input to the spifi clock divider. 0x3 reserved, this setting should not be used. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 35 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.4 external interrupts 3.3.4.1 external interrupt flag register when a pin is selected for its external interrupt function, the level or edge on that pin (selected by its bits in the extpolar and extmode registers) will set its interrupt flag in this register. this asserts the corresponding in terrupt r equest to the nvic, which will cause an interrupt if interrupts from the pin are enabled. writing ones to bits eint0 through eint3 in extint register clears the corresponding bits. in level-sensitive mode the interrupt is cleared only when the pin is in its inactive state. once a bit from eint0 to eint3 is set and an appropriate code starts to execute (handling wake-up and/or external interrupt), this bit in extint register must be cleared. otherwise event that was just triggered by activity on the eint pin will not be recognized in future. important: whenever a change of external interrupt operating mode (i.e. active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in the extint register must be cleared! for details see section 3.3.4.2 ? external interrupt mode register ? and section 3.3.4.3 ? external interrupt polarity register ? . for example, if a system wakes up from powe r-down using low level on external interrupt 0 pin, its post wake-up code must reset eint0 bit in order to allow future entry into the power-down mode. if eint0 bit is left set to 1, any subsequent attempt to invoke power-down mode will fail. the same g oes for external interrupt handling. more details on powe r-down mode will be discussed in the following chapters. table 25. external interrupt flag register (extint - address 0x400f c140) bit description bit symbol description reset value 0 eint0 in level-sensitive mode, this bit is set if the eint0 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint0 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 1 eint1 in level-sensitive mode, this bit is set if the eint1 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint1 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 36 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control [1] example: e.g. if the eintx is selected to be low level sensitive and low level is present on corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 3.3.4.2 external interrupt mode register the bits in this register select whether each ei nt pin is level- or edge-sensitive. only pins that are selected for the eint function (see section 7.3 ) and enabled in the appropriate nvic register) can cause interrupts from the ex ternal interrupt function (though of course pins selected for other functions may cause interrupts from those functions). note: software should only change a bit in this register when its interrupt is disabled in the nvic (state readable in the isern/icern registers), and should write the corresponding 1 to extint before enabling (initializing) or re-enabling the interrupt. an extraneous interrupt could be set by changing the mode and not having the extint cleared. 2 eint2 in level-sensitive mode, this bit is set if the eint2 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint2 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 3 eint3 in level-sensitive mode, this bit is set if the eint3 function is selected for its pin, and the pin is in its active state. in edge-sensitive mode, this bit is set if the eint3 function is selected for its pin, and the selected edge occurs on the pin. this bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state. [1] 0 31:4 - reserved. read value is undefined, only zero should be written. na table 25. external interrupt flag register (extint - address 0x400f c140) bit description bit symbol description reset value table 26. external interrupt mode register (extmode - address 0x400f c148) bit description bit symbol value description reset value 0 extmode0 level or edge sensitivity select for eint0. 0 0 level sensitive. 1 edge sensitive. 1 extmode1 level or edge sensitivity select for eint1. 0 0 level sensitive. 1 edge sensitive. 2 extmode2 level or edge sensitivity select for eint2. 0 0 level sensitive. 1 edge sensitive. 3 extmode3 level or edge sensitivity select for eint3. 0 0 level sensitive. 1 edge sensitive. 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 37 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.4.3 external interrupt polarity register in level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. in edge-s ensitive mode, they select whether the pin is rising- or falling-edge sensitive. only pins that are selected for the eint function only pins that are selected for the eint function (see section 7.3 ) and enabled in the appropriate nvic register) can cause interrupts from the extern al interrupt function (t hough of course pins selected for other functions may caus e interrupts from those functions). note: software should only change a bit in this register when its interrupt is disabled in the nvic (state readable in the isern/icern registers), and should write the corresponding 1 to extint before enabling (initializing) or re-enabling the interrupt. an extraneous interrupt could be set by changing the polarity and not having the extint cleared. table 27. external interrupt polarity register (extpolar - address 0x400f c14c) bit description bit symbol value description reset value 0 extpolar0 external interru pt polarity for eint0 . 0 0 low-active or falling-edge sensitive (depending on extmode0). 1 high-active or rising-edge sensitive (depending on extmode0). 1 extpolar1 external interru pt polarity for eint1 . 0 0 low-active or falling-edge sensitive (depending on extmode1). 1 high-active or rising-edge sensitive (depending on extmode1). 2 extpolar2 external interru pt polarity for eint2 . 0 0 low-active or falling-edge sensitive (depending on extmode2). 1 high-active or rising-edge sensitive (depending on extmode2). 3 extpolar3 external interru pt polarity for eint3 . 0 0 low-active or falling-edge sensitive (depending on extmode3). 1 high-active or rising-edge sensitive (depending on extmode3). 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 38 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5 device and peripheral reset 3.3.5.1 reset source identification register this register contains one bit for each source of reset. writing a 1 to any of these bits clears the corresponding read-side bit to 0. the interactions among the four sources are described below. table 28. reset source identification regist er (rsid - address 0x400f c180) bit description bit symbol description reset value 0 por assertion of the por signal sets this bit, and clears all of the other bits in this register. but if another reset signal (e.g., external reset) remains asserted after the por signal is negated, then its bit is set. this bit is not affected by any of the other sources of reset. see description 1 extr assertion of the external reset signal sets this bit. this bit is cleared only by software or por. see description 2 wdtr this bit is set when the watchdog timer times out and the wdtreset bit in the watchdog mode register is 1. this bit is cleared only by software or por. see description 3 bodr this bit is set when the v dd(reg)(3v3) voltage reaches a level below the bod reset trip level (typically 1.85 v under nominal room temperature conditions). if the v dd(reg)(3v3) voltage dips from the normal operating range to below the bod reset trip level and recovers, the bodr bit will be set to 1. if the v dd(reg)(3v3) voltage dips from the normal operating range to below the bod reset trip level and continues to decline to the level at which por is asserted (nominally 1 v), the bodr bit is cleared. if the v dd(reg)(3v3) voltage rises continuously from below 1 v to a level above the bod reset trip level, the bodr will be set to 1. this bit is cleared only by software or por. note: only in the case where a reset occurs and the por = 0, the bodr bit indicates if the v dd(reg)(3v3) voltage was below the bod reset trip level or not. see description 4 sysreset this bit is set if the processor has been reset due to a system reset request. setting the sysresetreq bit in the cortex-m4 aircr register causes a chip reset. this bit is cleared only by software or por. see description 5 lockup this bit is set if the processor has been reset due to a lockup of the cpu (see cortex-m4 documentation for details). the lockup state causes a chip reset. this bit is cleared only by software or por. see description 31:6 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 39 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5.2 reset control register 0 many peripherals may be given a hardware reset using the rstcon0 register. some additional peripherals may be reset using the rstcon1 register following. table 29. reset control register 0 (rstco n0 - address 0x400f c1cc) bit description bit symbol description reset value 0 rstlcd lcd controller reset control bit. 0 1 rsttim0 timer/counter 0 reset control bit. 0 2 rsttim1 timer/counter 1 reset control bit. 0 3 rstuart0 uart0 reset control bit. 0 4 rstuart1 uart1 reset control bit. 0 5 rstpwm0 pwm0 reset control bit. 0 6 rstpwm1 pwm1 reset control bit. 0 7rsti2c0 the i 2 c0 interface reset control bit. 0 8 rstuart4 uart4 reset control bit. 0 9 rstrtc rtc and event monitor/recorder reset control bit. rtc reset is limited, see table 626 ? register overview: real-time clock (base address 0x4002 4000) ? for details. 0 10 rstssp1 the ssp 1 interface reset control bit. 0 11 rstemc external memory cont roller reset control bit. 0 12 rstadc a/d converter (adc) reset control bit. 0 13 rstcan1 can controller 1 reset control bit. note: the can acceptance filter may be reset by a separate bit in the rstcon1 register. 0 14 rstcan2 can controller 2 reset control bit. note: the can acceptance filter may be reset by a separate bit in the rstcon1 register. 0 15 rstgpio reset control bit for gpio, and gpio interrupts. note: iocon may be reset by a separate bit in the rstcon1 register. 0 16 rstspifi spi flash interface reset control bit. 0 17 rstmcpwm motor control pwm reset control bit. 0 18 rstqei quadrature encoder interface reset control bit. 0 19 rsti2c1 the i 2 c1 interface reset control bit. 0 20 rstssp2 the ssp2 interface reset control bit. 0 21 rstssp0 the ssp0 interface reset control bit. 0 22 rsttim2 timer 2 reset control bit. 0 23 rsttim3 timer 3 reset control bit. 0 24 rstuart2 uart 2 reset control bit. 0 25 rstuart3 uart 3 reset control bit. 0 26 rsti2c2 i 2 c interface 2 reset control bit. 0 27 rsti2s i 2 s interface reset control bit. 0 28 rstsdc sd card interface reset control bit. 0 29 rstgpdma gpdma function reset control bit. 0 30 rstenet ethernet block reset control bit. 0 31 rstusb usb interface reset control bit. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 40 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.5.3 reset control register 1 some additional peripherals may be given a hardware reset using the rstcon1 register, as shown in ta b l e 3 0 below. table 30. reset control register 1 (rstco n1 - address 0x400f c1d0) bit description bit symbol description reset value 0 rstiocon reset control bit for the iocon registers. 0 1 rstdac d/a converter (dac) reset control bit. 0 2 rstcanacc can acceptance filter reset control bit. 0 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 41 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.6 emc delay control and calibration 3.3.6.1 emc delay control register the emcdlyctl register controls on-chip programmable delays that can b used to fine tune timing to external sdram memories. dela ys can be configured in increments of approximately 250 picoseconds up to a maximum of roughly 7.75 ns. see section 9.5.6 for an overview of the programmable delays. figure 5 shows the detailed connections of the programmable delays. ta b l e 3 1 shows the bit assignments in emcdlyctl. fig 5. emc programmable delays 100811 0 1 0 1 0 1 0 1 programmable delay block emcdelayctl[4:0] emc_clk emcclkdelay 0.25 ns 0.5 ns 2 ns 1 ns programmable delay block clkout[0] or clkout[1] fbclkin emcdelayctl[12:8] programmable delay block clkout[0] emc_clkout[0] emcdelayctl[20:16] programmable delay block clkout[1] emc_clkout[1] emcdelayctl[28:24] 0 1 4 ns table 31. delay control register (emcdlyctl - 0x400f c1dc) bit description bit symbol description reset value 4:0 cmddly programmable delay value for emc outputs in command delayed mode. see section 9.13.6 . the delay amount is roughly (cmddly+1) * 250 picoseconds. this field applies only when the command delayed read strategy is selected in the emcdynamicreadconfig register. in this mode, all control outputs from the emc are delayed, but the output clock is not. delaying the control outputs changes dynamic characteristics defined in the device data sheet. 0x10 7:5 - reserved. read value is undefined, only zero should be written. na 12:8 fbclkdly programmable delay value for the feedback clock that controls input data sampling. see section 9.5.3 . the delay amount is roughly (fbclkdly+1) * 250 picoseconds. 0x02 15:13 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 42 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.6.2 emc calibration register the emccal register allows calibration of the emc programmable delays by providing a real-time representation of the value of those delays. delay settings that are in use in the application can be calibrated to compensate for intrinsic differences between devices, and for changes in ambient conditions. figure 6 below shows the delay calibration circuit. ta b l e 3 2 shows the bit assignments in emccal. 20:16 clkout0dly programmable delay value for the clkout0 output. this would typically be used in clock delayed mode. see section 9.13.6 the delay amount is roughly (clkout0dly+1) * 250 picoseconds. dela ying the clock outp ut changes dynamic characteristics defined in the device data sheet. 0 23:21 - reserved. read value is undefined, only zero should be written. na 28:24 clkout1dly programmable delay value for the clkout1 output. this would typically be used in clock delayed mode. see section 9.13.6 the delay amount is roughly (clkout1dly+1) * 250 picoseconds. 0 31:29 - reserved. read value is undefined, only zero should be written. na table 31. delay control register (emcdlyctl - 0x400f c1dc) bit description bit symbol description reset value fig 6. emc delay calibration 100813 8-bit counter 5-bit counter clear enable ring oscillator emccal register control clear enable overflow irc reference clock (factory calibrated to 12 mhz) 0 78 1314 15 31 16 ~50 mhz (varies with process, voltage, and temperature) calvalue (reserved) start done (reserved) table 32. emc calibration register (emccal - 0x400f c1e0) bit description bit symbol description reset value 7:0 calvalue returns the count of the approximatel y 50 mhz ring oscillator that occur during 32 clocks of the irc oscillator. this represents the co mposite effect of processing variation, internal regulator supply voltage, and ambient temperature. 0 13:8 - reserved. read value is undefined, only zero should be written. na 14 start start control bit for the emc calibration counter. writing a 1 to this bit begins the measurement process. this bit is cleare d automatically when the measurement is complete. 0 15 done measurement completion flag. this bit is set when a calibration measurement is completed. this bit is cleared automatically when the start bit is set. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 43 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control procedure for calibrating programmable delays 1. write 1 to the start bit of the emccal register. 2. wait until the done bit of the same register becomes 1. other operations can be done during this time, the calibration requires 32 clocks of the 12 mhz irc clock, or about 2.7 microseconds. 3. read the calibration value from the bottom 8 bits of the emccal register. a typical value at room temperature is 0x86. 4. adjust one or more programmable delays if needed based on the calibration result. the calibration procedure should typically be repeated periodically, depending on how rapidly ambient conditions may change in the application environment.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 44 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7 miscellaneous system control registers 3.3.7.1 system controls and status register the scs register contains special control and status bits related to various aspects of chip operation. these functi ons are described in ta b l e 3 3 . several of these bits apply to the main oscillator. since chip operation always begins using the internal rc oscillato r, and the main oscillator may not be used at all in some applications, it w ill only be started by software request. this is accomplished by setting the oscen bit in the scs register, as described in table 3-13. t he main oscillator provides a status flag (the oscstat bit in the scs re gister) so that software can determine when the oscillator is running and stable. at that point, software can cont rol switching to the main oscillator as a clock sour ce. prior to starting the main oscillator, a frequenc y range must be selected by configuring th e oscrange bit in the scs register. table 33. system controls and status register (scs - address 0x400f c1a0) bit description bit function value description access reset value 0 emcsc emc shift control. controls how addresses are output on the emc address pins for static memories. also see section 9.9 in the emc chapter. r/w 1 0 static memory addresses are shifted to match the data bus width. for example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the lsb. in this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. this also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift. 1 static memory addresses are always output as byte addresses regardless of the data bus width. for example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. in this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. this mode matches the operation of lpc23xx and lpc24xx devices. 1 emcrd emc reset disable [1] . external memory controller reset disable. also see section 9.8 in the emc chapter. r/w 0 0 both emc resets are asserted when any type of chip reset event occurs. in this mode, all registers and functions of the emc are initialized upon any reset condition. 1 many portions of the emc are only rese t by a power-on or brown-out event, in order to allow the emc to retain its state through a warm reset (external reset or watchdog reset). if the emc is configured correctly, auto-refresh can be maintained through a warm reset. 2 emcbc external memory controller burst control. also see section 9.10 in the emc chapter. r/w 0 0 burst enabled. 1 burst disabled. this mode can be used to prevent multiple sequential accesses to memory mapped i/o devices connected to emc static memory chip selects. these unrequested accesses can cause issues with some i/o devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 45 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control [1] the state of this bit is preserved through a software reset, and only a por or a bod event will reset it to its default valu e. 3.3.7.2 lcd configuration register the lcd_cfg register controls the prescalin g of the clock used for lcd data generation. the contents of the lcd_cfg register are described in ta b l e 3 4 . 3 mcipwral mcipwr active level [1] . selects the active level of the sd card interface signal sd_pwr. r/w 1 0 sd_pwr is active low (inverted output of the sd card interface block). 1 sd_pwr is active high (follows the output of the sd card interface block). 4 oscrs main oscillator range select. r/w 0 0 the frequency range of the main oscillator is 1 mhz to 20 mhz. 1 the frequency range of the main oscillator is 15 mhz to 25 mhz. 5 oscen main oscillator enable. r/w 0 0 the main oscillator is disabled. 1 the main oscillator is enabled, and will start up if the correct external circuitry is connected to the xtal1 and xtal2 pins. 6 oscstat main oscillator status. ro 0 0 the main oscillator is not ready to be used as a clock source. 1 the main oscillator is ready to be used as a clock source. the main oscillator must be enabled via the oscen bit. 31:7 - reserved. read value is undefined, only zero should be written. - na table 33. system controls and status register (scs - address 0x400f c1a0) bit description bit function value description access reset value table 34. lcd configuration register (lcd_cf g, address - 0x400f c1b8) bit description bits symbol description reset value 4:0 clkdiv lcd panel clock prescaler selection. the value in the this register plus 1 is used to divide the selected input clock (see the clksel bit in the lcd_pol register), to produce the panel clock. 0 31:5 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 46 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.3 can sleep clear register this register provides the cu rrent sleep state of the two can channels and provides a means to restore the clocks to that channel following wake-up. refer to section 20.8.2 ? sleep mode ? for more information on the can sleep feature. 3.3.7.4 can wake-up flags register this register provides the wake-up status for the two can channels and allows clearing wake-up events. refer to section 20.8.2 ? sleep mode ? for more information on the can sleep feature. table 35. can sleep clear register (cansl eepclr - address 0x400f c110) bit description bit symbol function reset value 0 - reserved. read value is undefined, only zero should be written. na 1 can1sleep sleep status and control for can channel 1. read: when 1, indicates that can channel 1 is in the sleep mode. write: writing a 1 causes clocks to be restored to can channel 1. 0 2 can2sleep sleep status and control for can channel 2. read: when 1, indicates that can channel 2 is in the sleep mode. write: writing a 1 causes clocks to be restored to can channel 2. 0 31:3 - reserved. read value is undefined, only zero should be written. na table 36. can wake-up flags register (canwakeflags - address 0x400f c114) bit description bit symbol function reset value 0 - reserved. read value is undefined, only zero should be written. na 1 can1wake wake-up status for can channel 1 . read: when 1, indicates that a falling edge has occurred on the receive data line of can channel 1. write: writing a 1 clears this bit. 0 2 can2wake wake-up status for can channel 2 . read: when 1, indicates that a falling edge has occurred on the receive data line of can channel 2. write: writing a 1 clears this bit. 0 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 47 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.5 usb interrupt status register the usb otg controller has seven interrupt lines. only the first three interrupts (usb_int_req_lp, usb_int_req_hp, and usb_int_req_hp) and the usb_need_clk signal are used for the device controller. the interrupt lines are ored together to a single channel of the vectored interrupt controller. th is register allows software to determine their status with a single read operation. table 37. usb interrupt status register - (u sbintst - address 0x400f c1c0) bit description bit symbol description reset value 0 usb_int_req_lp low priority interrupt line status. this bit is read-only. 0 1 usb_int_req_hp high priority interrupt line status. this bit is read-only. 0 2 usb_int_req_dma dma interrupt line status. this bit is read-only. 0 3 usb_host_int usb host interrupt line status. this bit is read-only. 0 4 usb_atx_int external atx interrupt line status. this bit is read-only. 0 5 usb_otg_int otg interrupt line status. this bit is read-only. 0 6 usb_i2c_int i 2 c module interrupt line status. this bit is read-only. 0 7 - reserved. read value is undefined, only zero should be written. na 8 usb_need_clk usb need clock indicator. this bit is read-only. this bit is set to 1 when usb activity or a change of state on the usb data pins is detected, and it indicates that a pll supplied clock of 48 mhz is needed. once usb_need_clk becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the suspend change (sus_ch) interrupt has occurred. a change of this bit from 0 to 1 can wake up the microcontroller if activity on the usb bus is selected to wake up the part from the power-down mode (see section 3.12.8 ? wake-up from reduced power modes ? for details). also see section 3.10.3 ? plls and power-down mode ? and section 3.3.2.2 ? power control for peripherals registers ? for considerations about the pll and invoking the power-down mode. this bit is read-only. 1 30:9 - reserved. read value is undefined, only zero should be written. na 31 en_usb_ints enable all usb interrupts. when this bit is cleared, the nvic does not see the ored output of the usb interrupt lines. 1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 48 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.6 dma request select register dmacreqsel is a read/write register that allows selecting between potential dma requests for dma inputs 0 through 7 and 10 through 15. table 38 shows the bit assignments of the dmacreqsel register. table 38. dma request select register bit description bit name description reset value 0 dmasel00 selects the dma request for gpdma input 0: 0 - (unused) 1 - timer 0 match 0 is selected. 0 1 dmasel01 selects the dma request for gpdma input 1: 0 - sd card interface is selected. 1 - timer 0 match 1 is selected. 0 2 dmasel02 selects the dma request for gpdma input 2: 0 - ssp0 transmit is selected. 1 - timer 1 match 0 is selected. 0 3 dmasel03 selects the dma request for gpdma input 3: 0 - ssp0 receive is selected. 1 - timer 1 match 1 is selected. 0 4 dmasel04 selects the dma request for gpdma input 4: 0 - ssp1 transmit is selected. 1 - timer 2 match 0 is selected. 0 5 dmasel05 selects the dma request for gpdma input 5: 0 - ssp1 receive is selected. 1 - timer 2 match 1 is selected. 0 6 dmasel06 selects the dma request for gpdma input 6: 0 - ssp2 transmit is selected. 1 - i 2 s channel 0 is selected. 0 7 dmasel07 selects the dma request for gpdma input 7: 0 - ssp2 receive is selected. 1 - i 2 s channel 1 is selected. 0 9:8 - reserved. read value is undefined, only zero should be written. - 10 dmasel10 selects the dma request for gpdma input 10: 0 - uart0 transmit is selected. 1 - uart3 transmit is selected. 0 11 dmasel11 selects the dma request for gpdma input 11: 0 - uart0 receive is selected. 1 - uart3 receive is selected. 0 12 dmasel12 selects the dma request for gpdma input 12: 0 - uart1 transmit is selected. 1 - uart4 transmit is selected. 0 13 dmasel13 selects the dma request for gpdma input 13: 0 - uart1 receive is selected. 1 - uart4 receive is selected. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 49 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.3.7.6.1 timer dma requests timer dma requests are generated by the timer when the timer value matches the related match register (see section 24.6.12 ). if the dma controller is configured so that a timer dma request is selected as an input to a dma channel, and the dma channel is enabled, the dma controller will act on that request. 3.3.7.7 clock output configuration register the clkoutcfg register controls the selection of the internal clock that appears on the clkout pin and allows dividing the clock by an integer value up to 16. the divider can be used to produce a system clock that is related to one of the on-chip clocks. for most clock sources, the division may be by 1. when the cpu clock is selected and is higher than approximately 50 mhz, the output must be divi ded in order to bring the frequency within the ability of the pin to switch wi th reasonable logic levels. if a clock is selected that is not running, there will be no signal on clkout. note: the clkout multiplexer is designed to switch cleanly, without glitches, between the possible clock sources. the divider is also designed to allow changing the divide value without glitches. 14 dmasel14 selects the dma request for gpdma input 14: 0 - uart2 transmit is selected. 1 - timer 3 match 0 is selected. 0 15 dmasel15 selects the dma request for gpdma input 15: 0 - uart2 receive is selected. 1 - timer 3 match 1 is selected. 0 31:16 - reserved. read value is undefined, only zero should be written. - table 38. dma request select register bit description ?continued bit name description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 50 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control table 39. clock output configuration register (clkoutcfg - 0x400f c1c8) bit description bit symbol description reset value 3:0 clkoutsel selects the clock source for the clkout function. 0x0 = selects the cpu clock as the clkout source. 0x1 = selects the main oscillator as the clkout source. 0x2 = selects the internal rc oscillator as the clkout source. 0x3 = selects the usb clock as the clkout source. 0x4 = selects the rtc oscillator as the clkout source. 0x5 = selects the spifi clock as the clkout source. 0x6 = selects the watchdog oscillator as the clkout source. other settings are reserved. do not use. 0 7:4 clkoutdiv integer value to divide the output clock by, minus one. 0x0 = clock is divided by 1. 0x1 = clock is divided by 2. 0x2 = clock is divided by 3. ... 0xf = clock is divided by 16. 0 8 clkout_en clkout enable control, allows switching the clkout source without glitches. clear to stop clkout on the next falling edge. set to enable clkout. 0 9 clkout_act clkout activity indication. reads as 1 when clkout is enabled. read as 0 when clkout has been disabled via the clkout_en bit and the clock has completed being stopped. 0 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 51 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.4 chip reset reset has 6 sources: the reset pin, watchdog reset, power on reset (por), brown out detect (bod), sy stem reset, and lockup. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the wake-up timer (see description in section 3.13 ? wake-up timer ? in this chapter), causing reset to remain asserted until the external reset is de-a sserted, the oscillator is running, a fi xed number of clocks have passed, and the flash controller has completed it s initialization. the reset logic is shown in the following block diagram (see figure 7 ). on the assertion of a reset source external to the cpu (por, bod reset, external reset, and watchdog reset), the irc starts up. afte r the irc-start-up time (maximum of 60 ? s on power-up) and after the irc provides a stable clock output, the reset signal is latched and synchronized on the irc clock. then the following two sequences start simultaneously: 1. the 2-bit irc wake-up timer starts counting when the synchronized reset is de-asserted. the boot code in the rom starts when the 2-bit irc wake-up timer times out. the boot code performs the boot tasks an d may jump to the flash. if the flash is not ready to acce ss, the flash accelerato r will insert wait cycles until the flash is ready. 2. the flash wake-up timer (9-bit) starts counting when the synchronized reset is de-asserted. the flash wakeup-timer generates the 100 ? s flash start-up time. once it times out, the flash initialization sequence is started, which takes about 250 cycles. when it?s done, the flas h accelerator will be gran ted access to the flash. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. figure 8 shows an example of the re lationship between the reset , the irc, and the processor status when the device starts up after reset. see section 3.8.2 ? main oscillator ? for start-up of the main oscillato r if selected by the user code. fig 7. reset block diagram 120601 watchdog reset por bod external reset clr q set reset to on-chip circuitry wake-up complete system reset lockup to wake-up logic
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 52 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control fig 8. example of start-up after reset valid threshold processor status v dd(reg)(3v3) irc status reset gnd 60 s 1 s; irc stability count boot time boot code executing user code boot code execution finishes; user code starts irc starts irc stable supply ramp-up time
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 53 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.5 peripheral reset control most peripheral functions can have a hardware reset initiated by software by setting appropriate bits in the rstcon0 and rstc on1 registers. software must clear the rstcon register after this in order to a llow the peripheral to function. a peripheral remains in a hardware reset state as long as the corresponding bit in rstcon = 1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 54 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.6 brown-out detection a brown-out detector (bod) is included that provides 2-stage monitoring of the voltage on the v dd(reg)(3v3) pins. if this voltage falls below the bod interrupt trip level (typically 2.2 v under nominal room temperature conditions), the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading the raw interrupt status register. the second stage of low-voltage detection asserts reset to inactivate the device when the voltage on the v dd(reg)(3v3) pins falls below the bod rese t trip level (typically 1.85 v under nominal room temperature conditions). this reset prevents alteration of the flash as operation of the various elements of th e chip would otherwise become unreliable due to low voltage. the bod circuit maintains this reset down below 1 v, at which point the power-on reset circuitry maintains the overall reset. both the bod reset interrupt level and the bo d reset trip level thresholds include some hysteresis. in normal operatio n, this hysteresis allows the bod reset interrupt level detection to reliably interrupt, or a regularly -executed event loop to sense the condition. but when brown-out detection is enabled to bring the device out of power-down mode (which is itself not a guaranteed operation -- see section 3.3.2.1 ? power mode control register ? ), the supply voltage may recover from a transient before the wake-up timer has completed its delay. in this case, the net result of the transient bod is that the part wakes up and continues operation after the instructions that set power-down mode, without any interrupt occurring and with the bod bit in the rsid being 0. since all other wake-up conditions have latching flags (see section 3.3.4.1 ? external interrup t flag register ? and section 29.6.2 ), a wake-up of this type, without any apparent cause, can be assumed to be a brown-out that was too short to be fully captured.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 55 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.7 external interrupt inputs four external interrupt inputs are included as selectable pin functions. the logic of an individual external interrupt is represented in figure 9 . in addition, extern al interrupts have the ability to wake up the cpu from power-down mode. refer to section 3.12.8 ? wake-up from reduced power modes ? for details. fig 9. external interrupt logic interrupt flag (one bit of extint) write to extinti internal reset einti to wake-up logic einti pin extmodei pclk to interrupt controller extpolari einti interrupt enable pclk 1 glitch filter apb read of extinti q s r q s r q s d 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 56 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.7.1 register description the external interrupt function has four regist ers associated with it. the extint register contains the interrupt flags. the extmode and extpolar registers specify the level and edge sensitivity parameters. [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 40. external interrupt registers name description access reset value [1] address extint the external interrupt flag register contains interrupt flags for eint0, eint1, eint2 and eint3. see table 25 . r/w 0x00 0x400f c140 extmode the external interrupt mode regist er controls whether each pin is edge- or level-sensitive. see ta b l e 2 6 . r/w 0x00 0x400f c148 extpolar the external interrupt polarity register controls which level or edge on each pin will cause an interrupt. see ta b l e 2 7 . r/w 0x00 0x400f c14c
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 57 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.8 oscillators three indepen dent oscillators are included. these are the main oscillator, the internal rc oscillator, and the rtc oscillator. each oscillator can be used for more than one purpose as required in a particular application. this can be seen in figure 4 . following reset, the device will operate from the internal rc oscillato r until switched by software. this allows systems to operate wit hout any external crystal, and allows the boot loader code to operate at a known frequency. 3.8.1 internal rc oscillator the internal rc oscillator (irc) may be us ed as the clock that drives pll0 and subsequently the cpu. the precision of t he irc does not allow for use of the usb interface, which requires a much more precise time base in order to comply with the usb specification (only the main o scillator can meet that specif ication). also, the irc should not be used with the can1/2 block if the can baud rate is higher than 100 kbit/s.the irc frequency is 12 mhz, factory tr immed to within 1% accuracy. upon power-up or any chip rese t, the irc is used as the cl ock source. software may later switch to one of the other available clock sources. 3.8.2 main oscillator the main oscillator can be used as the clock source for the cpu, with or without using pll0. the main oscillato r operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the main pll (pll0). th e oscillator ou tput is called osc_clk. t he clock selected as the pll0 input is pllclkin and the arm processo r clock frequency is referred to as cclk for purposes of rate equations, etc. elsewh ere in this document. the frequencies of pllclkin and cclk are the same value unless the pll0 is active and connected. refer to section 3.10 for details. the on-board oscillator can ope rate in one of two modes: slave mode and oscillation mode. in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf (c c in figure 10 , drawing a), with an amplitude between 200 mvrms and 1000 mvrms. this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtal2 pin in this configuration can be left unconnected. external components and models used in oscillation mode are shown in figure 10 , drawings b and c, and in ta b l e 4 1 and ta b l e 4 2 . since the feedback resistance is integrated on chip, only a crys tal and the capacitances c x1 and c x2 need to be connected externally in case of fund amental mode oscillation (the fundamental frequency is represented by l, c l and r s ). capacitance c p in figure 10 , drawing c, represents the parallel package capacitance and should not be larger than 7 pf. parameters f c , c l , r s and c p are supplied by the crystal manufacturer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 58 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control fig 10. oscillator modes and models: a) slave mode of oper ation, b) oscillation mode of operation, c) external crystal model used for c x1 / x2 evaluation microcontroller microcontroller clock c c c x1 c x2 c l c p l r s < = > a) b) c) xtal xtal1 xtal2 xtal1 xtal2 table 41. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode (oscrange = 0, see table 33 ) fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 1mhz - 5mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 42. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) high fr equency mode (oscrange = 1, see table 33 ) fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , cx2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 59 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.8.2.1 main oscillator startup since chip operation always begins using th e internal rc oscillator, and the main oscillator may not be used at a ll in some applications, it will only be started by software request. this is accomplished by setting the oscen bit in the scs register, as described in ta b l e 3 3 . the main oscillato r provides a status flag (t he oscstat bit in the scs register) so that software can determine when the oscillator is running and stable. at that point, software can cont rol switching to the main oscilla tor as a clock source. prior to starting the main oscillator, a frequency range must be selected by configuring the oscrange bit in the scs register. 3.8.3 rtc oscillator the rtc oscillator provides a 1 hz clock to the rtc and a 32 khz cl ock output that can be output on the clkout pin in order to allow trimming the rtc oscillator without interference from a probe. 3.8.4 watchdog oscillator the watchdog timer has a dedicated oscilla tor that provides a 500 khz clock to the watchdog timer that is always running if the watchdog timer is enabled. the watchdog oscillator clock can be output on the clkout pin in order to allow observe its frequency. in order to allow watchdog timer operation with minimum power consumption, which can be important in reduced power modes, the watchdog oscillator frequ ency is not tightly controlled. the watchdog osc illator frequency will vary over temperat ure and power supply within a particular pa rt, and may vary by processing across different parts. this variation should be taken into account when determining watchdog reload values. within a particular part, temperature and power supply variations can produce up to a 17% frequency variation. frequency variation between devices under the same operating conditions can be up to 30%.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 60 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.9 clock source selection multiplexer two clock sources may be chosen to drive the system clock (sysclk) and pll0. these are the internal rc oscillator and the main oscillator. the clock source selection should only be ch anged safely when pll0 is not connected. for a detailed description of how to change the clock source in a system using pll0 see section 3.10.6 ? pll configuration sequence ? .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 61 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10 pll0 and pll1 (phase locked loops) pll0 (also called the main pll) and pll1 (also called the alt pll) are functionally identical, but have somewhat di fferent input possibilities and output connec tions. these possibilities are shown in figure 4 . the main pll can receive its input from either the irc or the main oscillator, and can potentially be used to pr ovide the clocks to nearly everything on the devi ce. the alt pll receives its input only from the main oscillator and is intended to be used as an alternate source of clocking to the usb and the spifi. this peripheral has timing needs that may not always be filled by the main pll. both plls are disabled and powered off on re set. if the alt pll is left disabled, the usb and spifi clocks can be supplied by pll0 if ev erything is set up to provide 48 mhz to the usb clock and the desired spifi clock through that route. the source for each clock must be selected via the clksel registers (see section 3.11 ), and can be further reduced by clock dividers as needed. pll activation is controlled via the pllcon registers. pll multiplier and divider values are controlled by the pllcfg registers. the pllcfg registers are protected in order to prevent accidental deactivation of plls or accidental alteration pll operating parameters. the protection is accomplished by a feed sequence similar to that of the watchdog timer. details are provided in t he descriptions of the pllfeed registers. pll0 accepts an input clock fre quency from either the irc or the main oscilla tor. if only the main pll is used, then its output frequency must be an integer multiple of all other clocks needed in the system. pl l1 takes its input only from th e main oscillator, requiring an external crystal in the range of 10 to 25 mhz. in each pll, the current controlled oscillator (cco) operates in the range of 156 mhz to 320 mhz, so there are additional dividers to bring the output down to the de sired frequencies. the minimum output divider value is 2, insuring that the output of the plls have a 50% duty cycle. figure 11 shows a block diagram of pll internal connections. if the usb is used, the possibilities for the cp u clock and other clocks will be limited by the requirements that the frequency be precise and very low jitter, and that the pll0 output must be a multiple of 48 mhz. even multiples of 48 mhz that are within the operating range of the pll f cco are 192 and 288 mhz. also, only the main oscillator in conjunction with the pll can meet the precision and jitter specifications for usb. it is due to these limitations that the alt pll is provided. the alt pll accepts an input clock frequency from the main oscillator in the range of 10 mhz to 25 mhz only. when used as the usb clock, the input frequency is multiplied up to a multiple of 48 mhz (192 or 288 mhz as described above). the alt pll can also provide the clock to the spifi through a separate divider, if needed. 3.10.1 pll and startup/b oot code interaction when there is no valid user code (determined by the checksum word) in the user flash or the isp enable pin (p2[10]) is pulled low on startup, the isp mode will be entered and the boot code will setup the main pll with the irc. therefore it ca n not be assumed that the main pll is disabled when the user opens a debug session to debug the application code. the user startup code must follow the st eps described in this chapter to disconnect the main pll.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 62 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.2 pll register description the plls are controlled by the registers shown in ta b l e 4 3 . more detailed descriptions follow. warning: improper setting of pll values may result in incorrect operation of the usb subsystem! [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 43. pll1 registers generic name description access reset value [1] plln register name and address table pllcon pll control register. holding register for updating pll control bits. values written to this register do not take effect until a valid pll feed sequence has taken place. r/w 0 pll0con - 0x400f c080 pll1con - 0x400f c0a0 10 pllcfg pll configuration register. holding register for updating pll configuration values. values written to this register do not take effect until a valid pll feed sequence has taken place. r/w 0 pll0cfg - 0x400f c084 pll1cfg - 0x400f c0a4 11 pllstat pll status register. read-back register for pll control and configuration information. if pllcon or pllcfg have been written to, but a pll feed sequence has not yet occurred, they will not reflect the current pll state. reading this register provides the actual values controlling pll, as well as pll status. ro 0 pll0stat - 0x400f c088 pll1stat - 0x400f c0a8 12 pllfeed pll feed register. this register enables loading of pll control and configuration information from the pllcon and pllcfg registers into the shadow registers that actually affect pll operation. wo na pll0feed - 0x400f c08c pll1feed - 0x400f c0ac 13 fig 11. pll0 and pll1 block diagram 120601 pll output clock divide by 2p phase detector plock pllstat[10] current- controlled oscillator fcco psel pllstat[6:5] pll input clock divide by m msel pllstat[4:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 63 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.3 plls and power-down mode power-down mode automatically turns off and disconnects activated plls, while subsequent wake-up from power-down mode d oes not automatically restore pll settings. this must be done in software. typically, a ro utine to activate a pl l, wait for lock, and then select the pll can be called at the begi nning of any interrupt service routine that might be called due to the wake-up. if activity on the usb data lines is not se lected to wake the microcontroller from power-down mode (see section 3.12.8 for details of wake up from reduced modes), both the main pll (pll0) and the alt pll (pll1) will be automatically be turned off and disconnected when power-down mode is invoked, as described above. however, if the usb activity interrupt is enab led and usb_need_clk = 1 (see ta b l e 2 5 3 for a description of usb_need_clk), it is not possible to go into power-down mode and any attempt to set the pd bit will fail, leaving the plls in the current state.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 64 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.4 pll frequency calculation equations for both the main and alt plls use the following parameters: the pll output frequency (when the pll is active and locked) is given by: pll_out_clk = m ? pll_in_clk - or - pll_out_clk = f cco / (2 ? p) the cco frequency can be computed as: f cco = pll_out_clk ? 2 ? p- or -f cco = pll_in_clk ? m ? 2 ? p the pll inputs and settings must meet the following criteria: ? m is in the range of 1 to 32. ? p is one of 1, 2, 4, 8. ? pll_in_clk is in the ra nge of 10 mhz to 25 mhz. ? f cco is in the range of 156 mhz to 320 mhz. ? pll_out_clk is in the range of 9.75 mhz to 160 mhz. 3.10.5 procedure for determining pll settings in general, pll configuration values may be found as follows: 1. based on the desired pll output freque ncy, choose an oscillator frequency (f osc ). if the usb interface is to be used, an external crystal of either 12 mhz, 16 mhz, or 24 mhz must be provided. 12 mhz is recommen ded for this purpose in order to save power and have more flexibility with pll settings. 2. if the usb interface is used in the system, and if a pll output of 96 mhz or 144 mhz can provide the desired cpu clock frequency, it is probably possible to use only pll0. 3. calculate the value of m to configure the msel1 bits to obtain the desired pll output frequency. m = pll_out_clk / pll_in_clk. the value written to the msel bits in the pllcfg register is m ? 1 (or see ta b l e 4 5 ). this is done for both plls if they are both used. table 44. elements determining pll frequency element description pll_in_clk the frequency of the input to the pll f cco the frequency of the pll cu rrent controlled oscillator pll_out_clk the pll output frequency m pll multiplier value from the msel bits in the pllcfg register p pll divider value from the psel bits in the pllcfg register
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 65 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 4. find a value for p to configure the psel bits, such that f cco is within its defined operating frequency limits of 156 mhz to 320 mhz. f cco is calculated using f cco = pll_out_clk ? 2 ? p. the value written to the psel bits in pllcfg can be found in ta b l e 4 6 . table 45. pll multiplier values value of m msel bits (pllcfg bits [4:0]) msel hex 1 00000 0 2 00001 0x01 3 00010 0x02 4 00011 0x03 5 00100 0x04 6 00101 0x05 7 00110 0x06 8 00111 0x07 9 01000 0x08 10 01001 0x09 11 01010 0x0a 12 01011 0x0b 13 01100 0x0c 14 01101 0x0d 15 01110 0x0e 16 01111 0x0f 17 10000 0x10 18 10001 0x11 19 10010 0x12 20 10011 0x13 21 10100 0x14 22 10101 0x15 23 10110 0x16 24 10111 0x17 25 11000 0x18 26 11001 0x19 27 11010 0x1a 28 11011 0x1b 29 11100 0x1c 30 11101 0x1d 31 11110 0x1e 32 11111 0x1f
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 66 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.6 pll configuration sequence the following discussions refer to plls and pll related registers generically (e.g. pllcfg rather than pll0cfg or pll1cfg). th e instructions have to be adapted to the specific case being addressed in the application. to set up a pll and switch clocks to its output: 1. make sure that the pll output is not already being used. the cclksel, usbclksel, and spificlksel registers must not select the pll being set up (see ? to switch clocks away from a pll output: ? below). clock dividers included in these registers may also be set up at this time if writing to any of the noted registers. 2. if the main pll is being set up, and the main clock source is being changed (irc versus main oscillator), change this firs t by writing the correct value to the clksrcsel register. 3. write pll new setup values to the pllcfg register. write a 1 to the plle bit in the pllcon register. perform a pll feed sequence by writing first the value 0xaa, then the value 0x55 to the pllfeed register. 4. set up the necessary cloc k dividers. these may incl ude the cclksel, pclksel, emcclksel, usbclksel, and th e spificlksel registers. 5. wait for the pll to lock. this may be a ccomplished by polling th e pllstat register and testing for plock = 1, or by using the pll lock interrupt. 6. connect the pll by selecting it output in the appropriate places. this may include the cclksel, usbclksel, and spificlksel registers. to switch clocks away from a pll output: 1. to switch back to the mode of not using a pll, write values to any or all of the cclksel, usbclksel, and spificl ksel registers in order to select a different clock source. 2. the related pll may now be turned off by writing to the pllcon register and performing a pll feed sequence, reconfigured by writing to the pllcfg register, etc. table 46. pll divider values value of p psel bits (pllcfg bits [6:5]) psel hex 10 00 20 10 x 1 41 00 x 2 81 10 x 3
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 67 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.10.7 pll configuration examples the following examples illustrate selectin g pll values based on different system requirements. example 1) . assumptions: ? the system design is planned to use the irc to generate the cpu clock. ? a frequency as close to 80 mhz as po ssible is desired for the cpu clock. of the two plls, only pll0 can supply the cp u clock, so this example is for pll0. the nearest multiple of the 12 mhz irc frequency to 80 mhz is 84 mhz. since pll_out_clk = m ? pll_in_clk, m = pl l_out_clk / pll_in_clk = 84 / 12 = 7. now a value for p must be found that puts f cco within the pll operating range of 156 mhz to 320 mhz. f cco = pll_out_clk ? 2 ? p. start by finding the value of f cco with p = 1, which is 84 mhz ? 2 = 168 mhz. since that is within the pll operating range, no further work is needed. set up the pll for m = 7and p = 1. this requires putting the value 6 (m - 1, or see table 45 ? pll multiplier values ? ) in the msel field of the pll0cfg register. a value of 0 (see table 46 ? pll divider values ? ) is needed in the psel field of pll0cfg. a single write of both values would be pll0cfg = 0x06. see section 3.10.6 for a description of the pll setup sequence. example 2) . assumptions: ? the system design is planned to use a 12 mhz crystal generate both the cpu clock and the usb clock. ? a frequency close to 100 mhz is desired for the cpu clock. of the two plls, only pll0 can supply both the cpu clock and the usb clock, so this example is for pll0. the pll output must be an even integer multiple of 48 mhz for the usb to operate correctly (i.e. a multiple of 96 mhz). two multiples of 96 mhz fit within the pll operating range: 192 mhz (2 ? 96 mhz), and 288 mhz (3 ? 96 mhz). of these, only 192 mhz can produce a cpu clock near 100 mhz (96 mhz). so, a 96 mhz pll output can be used to obtain the 2 needed frequencies. since pll_out_clk = m ? pll_in_clk, m = pll_out_clk / pll_in_clk = 96 / 12 = 8. now a value for p must be found that puts f cco within the pll operating range of 156 mhz to 320 mhz. f cco = pll_out_clk ? 2 ? p. start by finding the value of f cco with p = 1, which is 96 mhz ? 2 = 192 mhz. since that is within the pll operating range, no further work is needed. set up the pll for m = 8 and p = 1. this requires putting the value 7 (m - 1, or see ta b l e 4 5 ) in the msel field of the pll0cfg register. a value of 0 (see table 46 ) is needed in the psel field of pll0cfg. a single write of both values would be pll0cfg = 0x07. see section 3.10.6 for a description of the pll setup sequence. example 3)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 68 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control assumptions: ? the system design will use the usb interface. ? it is desired that the cpu clock remain flexible and able to operate at frequencies unrelated to the usb clock. in order to keep the cpu clo ck separate form the usb clock, the cpu will use pll0. for usb, pll1 may be configured with the same values used in the last example. pll0 can be operated from ei ther the irc or the main oscillator to obtain whatever frequency is needed, and the pll0 setup can be changed without compromising usb operation. 3.11 clock selection and division the output of each pll that is used must be divided down to whatever frequency is needed by each subsystem. there are separa te clocks for the cpu, external memory controller, usb interface, spifi, and peri pherals on the apb buses. separate clock selection multiplexers and cl ock dividers provide flexibilit y in the generation of these clocks. 3.12 power control a variety of power control features are supported: sleep mode, deep sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be controlled as needed by changing clock so urces, re-configuring pll values, and/or altering the cpu clock divider value. this a llows a trade-off of po wer versus processing speed based on application requirements. in addition, peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. a power boost feature a llows operation up to 120 mhz, or power savings when operation is at or below 100 mhz. entry to any reduced power mode begins with the execution of either a wfi (wait for interrupt) or wfe (wait for exception) instruction by th e cpu. the cpu internally supports two reduced power modes: sleep an d deep sleep. these are selected by the sleepdeep bit in the cortex-m4 system co ntrol register. power-down and deep power-down modes are selected by bits in the pcon register. see table 14 . the same register contains flags that indicate whether entry into each reduced power mode actually occurred. a separate power domain is implemented in order to allow turning off power to the bulk of the device while maintaining operation of the real time clock. reduced power modes have some limitation during debug, see section 39.7 for more information. 3.12.1 sleep mode note: sleep mode on these devices corresponds to the idle mode on older lpc2xxx series devices. the name is changed because arm has incorporated portions of reduced power mode control into the cortex-m4.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 69 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control when sleep mode is entered, the clock to the core is stopped, and the smflag bit in pcon is set, see ta b l e 1 4 .resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is su spended until either a reset or an interrupt occurs. peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. the dma controller can continue to work in sleep mode, and has access to the peripheral srams and all peripheral registers. the fl ash memory and the main sram are not available in sleep mode, they are disabled in order to save power. wake-up from sleep mode will occur wh enever any enabled interrupt occurs. 3.12.2 deep sleep mode note: deep sleep mode on these devices corresponds to the sleep mode on older lpc23xx and lpc24xx series devices. the name is changed because arm has incorporated portions of reduced power mode control into the cortex-m4. when the chip enters the deep sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the dsflag bit in pcon is set, see ta b l e 1 4 . the irc remains running for fast startup. the 32 khz rtc oscillator is not stoppe d and rtc interrupts may be used as a wake-up source. the flash is left in the standby mode allowing a quick wake-up. the plls are automatically turned off and the clock selection multiplexers are set to use sysclk (the reset state). the clock divider control registers are automatically reset to zero. the processor state and registers, peripheral registers, and internal sram values are preserved throughout deep sleep mode and the logic levels of chip pins remain static. the deep sleep mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that ar e able to function without clocks. since all dynamic operation of the chip is suspend ed, deep sleep mode reduces chip power consumption to a very low value. on the wake-up of deep sleep mode, if the irc was used before entering deep sleep mode, a 2-bit irc timer starts counting and t he code execution and peripherals activities will resume after the timer expire s (4 cycles). if the main oscillator is used, the 12-bit main oscillator timer starts counting and the code execution will resume when the timer expires (4096 cycles). the user must remember to re-configure any required plls and clock dividers after the wake-up. wake-up from deep sleep mode can be brought about by nmi, external interrupts eint0 through eint3, gpio interrupts, the ether net wake-on-lan interrupt, brownout detect, an rtc alarm interrupt, a usb input pin trans ition (usb activity in terrupt), a can input pin transition, or a watchdog timer timeout, when the related interrupt is enabled. wake-up will occur wh enever any enabled interrupt occurs.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 70 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.12.3 power-down mode power-down mode does everythi ng that deep sleep mode does, but also turns off the flash memory. entry to power-down mode causes the pdflag bit in pcon to be set, see ta b l e 1 4 . this saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. when the chip enters power-do wn mode, the irc, the main oscillator, and all clocks are stopped. the rtc remains running if it has been enabled and rtc interrupts may be used to wake up the cpu. the flash is fo rced into power-down mode. the plls are automatically turned off and the clock select ion multiplexers are se t to use sysclk (the reset state). the clock divider control regist ers are automatically re set to zero. if the watchdog timer is running, it will co ntinue running in power-down mode. upon wake-up from power-down mode, if t he irc was used before entering power-down mode, after irc-start-up time (about 60 ? s), the 2-bit irc timer starts counting and expiring in 4 cycles. code execution can then be resumed immediately following the expiration of the irc timer if the code was running from sram. in the meantime, the flash wake-up timer measures flash start-up time of about 100 ? s. when it times out, access to the flash is enabled. the user must remember to re-configure any required plls and clock dividers after the wake-up. wake-up from power-down mode can be brought about by nmi, external interrupts eint0 through eint3, gpio interrupts, the ether net wake-on-lan interrupt, brownout detect, an rtc alarm interrupt, a usb input pin transi tion (usb activity interrupt), or a can input pin transition, when the related interrupt is enabled. 3.12.4 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the real-time clock, the reset pin, the wic, and the rtc backup registers. entry to deep power-down mode causes the dpdflag bit in pcon to be set, see ta b l e 1 4 . to optimize power conservation, the user ha s the additional option of turning off or retaining power to the 32 khz osc illator. it is also possible to use external circ uitry to turn off power to the on-chip regulator via the v dd(reg)(3v3) pins and/or the i/o power via the v dd(3v3) pins after entering deep power-down mode. power must be restored before device operation can be restarted. wake-up from deep power-do wn mode will occur when an external rese t signal is applied, or the rtc interrupt is enabled and an rtc interrupt is generated. 3.12.5 peripheral power control a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. this is detailed in the description of the pconp register. 3.12.6 power boost a power boost feature allows operation above 100 mhz, to the upper limit for this device of 120 mhz. this boost is on by default when user code begins after a chip reset. power can be saved by turning of th is mode when operat ion will be at 100 mhz or lower. see section 3.3.2.3 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 71 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.12.7 register description the power control function uses registers shown in ta b l e 4 7 . more detailed descriptions follow. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 3.12.8 wake-up from re duced power modes any enabled interrupt can wake up the cpu from sleep mode. certain interrupts can wake up the processor if it is in eith er deep sleep mode or power-down mode. interrupts that can o ccur during deep sleep or power-down mo de will wake up the cpu if the interrupt is en abled. after wake-up, ex ecution will continue to th e appropriate interrupt service routine. these interrupts are nmi, ex ternal interrupts eint 0 through eint3, gpio interrupts, ethernet wake-on- lan interrupt, brownout detect, rtc alarm, can activity interrupt, usb activity interrupt, and watch dog timer timeout. for the wake-up process to take place, the corresponding interrupt must be enabled in the nvic. for pin-related peripheral functions, the related functions must also be mapped to pins. the can activity interrupt is generated by activity on the can bus pins, and the usb activity interrupt is generated by activity on the usb bus pins. these interrupts are only useful to wake up the cpu when it is on deep sleep or power-down mode, when the peripheral functions are powered up, but not ac tive. typically, if these interrupts are used, their flags should be polled just before enabling the interrupt and entering the desired reduced power mode. this can save time and power by avoiding an immediate wake-up. upon wake-up, the interrupt service can turn off the related activity interrupt, do any application specific setup, and exit to await a normal peripheral interrupt. in deep power-down mode, intern al power to most of the device is removed, which limits the possibilities for waking up from this m ode. external reset ca n wake-up the device. also, of the rtc is running and has been set up to cause an interrupt, that event can wake-up the device. 3.12.9 power control usage notes after every reset, the pconp register contains the value that enables selected interfaces and peripherals controlled by the pconp to be enabled. therefore, apart from proper configuring via peripheral dedicated registers, the user?s application might have to access the pconp in order to start using some of the on-board peripherals. table 47. power control registers name description access reset value [1] address table pcon power control register. this register contains control bits that enable some reduced power operating modes. see ta b l e 1 4 . r/w 0 0x400f c0c0 14 pconp power control for peripherals register. this register contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed. see table 16 . r/w 0x0408 829e 0x400f c0c4 16 pboost power boost control register. th is register controls the output of the main on-chip regulator, allowing a choice between high-speed operation above 100 mhz, or power savings when operation is at 100 mhz or lower. r/w 0x3 0x400f c1b0 18
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 72 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control power saving oriented systems should have 1s in the pconp register only in positions that match peripherals that are actually used in the application. all other bits, declared to be "reserved" or dedicated to the peripherals not used in the current application, must be cleared to 0. 3.12.10 power domains two independent power domains are provided that allow the bulk of the device to have power removed while maintaining op eration of the real time clock. the v bat pin supplies power only to the rtc domain. the rtc requires a minimum of power to operate, which can be supplied by an external battery. whenever the device core power is greater than v bat , that power is used to operate the rtc. 3.13 wake-up timer at power-up and when awaken ed from power-down mode, op eration begins by using the 12 mhz irc oscillator as the clo ck source. this allows chip op eration to begin quickly. if the main oscillator or one or both plls are needed by the app lication, software will need to enable these features and wait for them to stabilize before they are used as a clock source. when the main oscillator is init ially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. this is im portant at power-on, all types of reset, and whenever any of the aforemen tioned functions are turned off for any reason. since the oscillator and other functions are turned off during power- down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monitors the crystal oscillator as the means of checki ng whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit powe r-down mode, some time is required for the os cillator to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd(reg)(3v3) ramp (in the case of power on), the type of crystal and its electrical char acteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacito rs), and the char acteristics of the osc illator itself under the existing ambient conditions. once a clock is detected, the wake-up timer counts a fixed number of clocks (4,096), then sets the flag (oscstat bit in the scs r egister) that indicates th at the main oscillator is ready for use. software can then switch to the main oscillator and start any required plls. refer to the main oscillator description in this chapter for details.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 73 of 942 nxp semiconductors UM10562 chapter 3: lpc408x/407x system and clock control 3.14 external clock output pin for system test and developm ent purposes, any one of seve ral internal clocks may be brought out on the clkout function available on the p1[25] or p1[27] pins, as shown in figure 12 . clocks that may be ob served via clkout are the cpu cl ock (cclk), the main oscillator (osc_clk), the internal rc oscillator (irc_osc), the usb cl ock (usb_clk), the rtc clock (rtc_clk), the spifi clock (spifi_clk), and the watchdog oscillator (wdt_clk). fig 12. clkout selection clkoutcfg[3:0] clkout divider clkoutcfg[7:4] clock enable syncronizer clkoutcfg[8] clkout clkoutcfg[9] cclk osc_clk irc_osc usb_clk rtc_clk spifi_clk wdt_clk 000 001 010 011 100 101 110 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 74 of 942 4.1 introduction the flash accelerator block allows maximization of the performance of the cpu when it is running code from flash memory, while also saving power. the flash accelerator also provides speed and power improvements for data accesses to the flash memory. 4.2 flash accelerator blocks the flash accelerator is divided into several functional blocks: ? ahb-lite bus interface, accessible by the i-code and d-code buses of the cpu, as well as by the general purpose dma controller ? an array of eight 128-bit buffers ? flash accelerator control logic, including address compare and flash control ? a flash memory interface figure 13 shows a simplified diagram of the flash accelerator blocks and data paths. in the following descriptions, the term ?fetch? applies to an explicit flash read request from the cpu. ?prefetch? is used to denote a fl ash read of instructions beyond the current processor fetch address. 4.2.1 flash memory bank flash programming operations are not controlle d by the flash accelerator, but are handled as a separate function. a boot rom contains flash programming algorithms that may be called as part of the application program, and a loader that may be run to allow programming of the flash memory. UM10562 chapter 4: lpc408x/407x flash accelerator rev. 1 ? 13 september 2012 user manual fig 13. simplified block diagram of the flash accelerator showing potential bus connections flash accelerator control flash interface ahb-lite bus interface instruction/ data buffers flash memory bus matrix dcode bus icode bus general purpose dma controller dma master port combined ahb flash accelerator 120601 cpu
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 75 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.2.2 flash programming issues since the flash memory does not allow accesses during programming and erase operations, it is necessary for the flash accele rator to force the cpu to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation. under some conditions, this delay could result in a watchdog time-out. the user will ne ed to be aware of this possibility an d take steps to insure that an unwanted watchdog reset does not cause a syst em failure while programming or erasing the flash memory. in order to preclude the possibility of stale data being read from the flash memory, the flash accelerator buffers are automatically invalidated at the beginning of any flash programming or erase operatio n. any subseque nt read from a flash address will cause a new fetch to be initiated after the flash operation has completed.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 76 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.3 register description the flash accelerator is contro lled by the register shown in table 48 . more detailed descriptions follow. [1] reset value reflects the data stored in defined bits only. it does not include reserved bits content. 4.4 flash accelerator configuration register configuration bits select the flash access time, as shown in ta b l e 4 9 . the lower bits of flashcfg control internal flash accelerator functions and should not be altered. following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks. changing the flashcfg register value causes the flash accelerator to invalidate all of the holding latches, resulting in new reads of flash information as required. this guarantees synchronization of the flash accelerator to cpu operation. table 48. summary of flash accelerator registers name description access reset value [1] address flashcfg flash accelerator configuration register. controls flash access timing. see table 49 . r/w 0x303a 0x400f c000 table 49. flash accelerator configuration register (flashcfg - address 0x400f c000) bit description bit symbol value description reset value 11:0 - - reserved, user software should not change these bits from the reset value. 0x03a 15:12 flashtim flash access time. the value of this field plus 1 give s the number of cpu clocks used for a flash access. warning: improper setting of this value may result in incorrect operation of the device. 0x3 0000 flash accesses use 1 cpu clock. use for up to 20 mhz cpu clock with power boost off (see section 3.12.6 ). 0001 flash accesses use 2 cpu clocks. use for up to 40 mhz cpu clock with power boost off (see section 3.12.6 ). 0010 flash accesses use 3 cpu clocks. use for up to 60 mhz cpu clock with power boost off (see section 3.12.6 ). 0011 flash accesses use 4 cpu clocks. use for up to 80 mhz cpu clock with power boost off (see section 3.12.6 ). use this setting for operation from 100 to 120 mhz operation with power boost on. 0100 flash accesses use 5 cpu clocks. use for up to 100 mhz cpu clock with power boost off (see section 3.12.6 ). 0101 flash accesses use 6 cpu clocks. ?safe? setting for any allowed conditions. other intended for potential future higher speed devices. 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 77 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator 4.5 operation simply put, the flash accelera tor attempts to have the next instruction that will be needed in its latches in time to prevent cpu fetch stalls. the flash accelerator includes an array of eight 128-bit buffers to store both instructions and data in a configurable manner. each 128-bit buffer in the array can include four 32-bi t instructions, eight 16 -bit instructions or some combination of the two. during sequentia l code execution, a buffer typically contains the current instruction and the entire flash line that contains that instruction, or one flash line of data containing a previously requeste d address. buffers are marked according to how they are used (as instruction or data buffers), and when they have been accessed. this information is used to carry out the buffer replacement strategy. the cpu provides a separate bus for inst ruction access (i-code) and data access (d-code) in the code memory space. these buses, plus the general purpose dma controllers?s master port, are arbitrated by the ahb multilayer matrix. any access to the flash memory?s address space is presented to the flash accelerator. if a flash instruction fetch and a flash data a ccess from the cpu occu r at the same time, the multilayer matrix gives precedence to the data access. this is because a stalled data access always slows down exec ution, while a stalled instruction fetch often does not. when the flash data access is concluded, any flash fetch or prefetch that had been in progress is re-initiated. branches and other program flow changes ca use a break in the sequential flow of instruction fetches described above. buffer replacement strategy in the flash accelerator attempts to maximize the chances that potent ially reusable information is retained until it is needed again. if an attempt is made to write directly to t he flash memory without using the normal flash programming interface (via boot rom function calls), the flash accelerator generates an error condition. the cpu treats this error as a data abort. the gpdma handles error conditions as described in section 35.4.1.6.3 . when an instruction fetch is not satisfied by ex isting contents of the buffer array, nor has a prefetch been initiated for that flash line, the cpu will be stalled while a fetch is initiated for the related 128-bit flash line. if a prefetch has been initiated but not yet completed, the cpu is stalled for a shorter time since the re quired flash access is already in progress. typically, a flash prefetch is begun whenever an access is made to a just prefetched address, or to a buffer whose immediate successor is not already in another buffer. a prefetch in progress may be aborted by a da ta access, in order to minimize cpu stalls. a prefetched flash line is latched within the flash memory, but the flash accelerator does not capture the line in a buffer until the cpu presents an address that is contained within the prefetched flash line. if the core presents an instruction address that is not already buffered and is not contained in the prefetched flash line, the prefetched line will be discarded. some special cases include the possibility that the cpu will request a data access to an address already contained in an instruction buffer. in this case, the data w ill be read from the buffer as if it was a data buffer. the reverse case, if the cpu requests an instruction address that can be satisfied from an existing data buffer, causes the instruction to be
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 78 of 942 nxp semiconductors UM10562 chapter 4: lpc408x/407x flash accelerator supplied from the data buffer, and the buffer to be changed into an instruction buffer. this causes the buffer to be handled differently when the flash accelerator is determining which buffer is to be overwritten next.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 79 of 942 5.1 features ? nested vectored interrupt controller that is an integral part of the arm cortex-m4 ? tightly coupled interrupt controller provides low interrupt latency ? controls system exceptions and peripheral interrupts ? the nvic supports 40 vectored interrupts in these devices ? 32 programmable interrupt priority levels , with hardware priority level masking ? relocatable vector table ? non-maskable interrupt ? software interr upt generation 5.2 description the nested vectored interrupt controller (nvic) is an integral part of the cortex-m4. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. the nvic handles inte rrupts in addition to system exceptions. exceptions include reset, nmi, hard fault, memmanage fault, bus fault, usage fault, svcall, debug monitor, pendsv, and systick. see the arm cortex-m4 user guide referred to in section 40.1 for details of nvic operation. 5.3 interrupt sources ta b l e 5 0 lists the interrupt sources for each pe ripheral function. each peripheral device may have one or more interrupt lines to the vectored interrupt controller. each line may represent more than one interrupt source, as noted. exception numbers relate to where entries ar e stored in the exception vector table. interrupt numbers are used in some other contexts, such as software interrupts. note that system exceptions are hard-wired into the cortex-m4 and are not shown in the table. some other information about the systi ck interrupt can be found in the system tick timer chapter, section 25.1 in addition, the nvic handles the non-maskab le interrupt (nmi). in order for nmi to operate from an external signal, the nmi func tion must be connected to the related device pin (p2[10] / eint0n / nmi). wh en connected, a logic 1 on the pin will cause the nmi to be processed. for details, refer to the cortex-m4 user guide that is an appendix to this user manual. UM10562 chapter 5: lpc408x/407x n ested vectored interrupt controller (nvic) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 80 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s) 0 16 0x40 wdt watchdog interrupt (wdint) 1 17 0x44 timer 0 match 0 - 1 (mr0, mr1) capture 0 - 1 (cr0, cr1) 2 18 0x48 timer 1 match 0 - 2 (mr0, mr1, mr2) capture 0 - 1 (cr0, cr1) 3 19 0x4c timer 2 match 0-3 capture 0-1 4 20 0x50 timer 3 match 0-3 capture 0-1 5 21 0x54 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 6 22 0x58 uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem control change end of auto-baud (abeo) auto-baud time-out (abto) 7 23 0x5c uart 2 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 8 24 0x60 uart 3 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) 9 25 0x64 pwm1 match 0 - 6 of pwm1 capture 0-1 of pwm1 10 26 0x68 i 2 c0 si (state change) 11 27 0x6c i 2 c1 si (state change) 12 28 0x70 i 2 c2 si (state change) 13 29 0x74 (unused) -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 81 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 14 30 0x78 ssp0 tx fifo half empty of ssp0 rx fifo half full of ssp0 rx timeout of ssp0 rx overrun of ssp0 15 31 0x7c ssp 1 tx fifo half empty rx fifo half full rx timeout rx overrun 16 32 0x80 pll0 (main pll) pll0 lock (plock0) 17 33 0x84 rtc and event monitor/recorder counter increment (rtccif), alarm (rtcalf) ev0, ev1, ev2 18 34 0x88 external interrupt external interrupt 0 (eint0) 19 35 0x8c external interrupt external interrupt 1 (eint1) 20 36 0x90 external interrupt external interrupt 2 (eint2) 21 37 0x94 external interrupt external interrupt 3 (eint3) 22 38 0x98 adc a/d converter end of conversion 23 39 0x9c bod brown out detect 24 40 0xa0 usb usb_int_req_lp, usb_int_req_hp, usb_int_req_dma, usb_host_int, usb_atx_int, usb_otg_int, usb_i2c_int 25 41 0xa4 can can common, can 0 tx, can 0 rx, can 1 tx, can 1 rx 26 42 0xa8 dma controller interrupt status of all dma channels 27 43 0xac i 2 s irq, dmareq1, dmareq2 28 44 0xb0 ethernet wakeupint, softint, txdoneint, txfinishedint, txerrorint, txunderrunint, rxdoneint, rxfinishedint, rxerrorint, rxoverrunint. 29 45 0xb4 sd card interface rxdataavlbl, txdataavlbl, rxfifoempty, txfifoempty, rxfifofull, txfifofull, rxfifohalffull, txfifohalfempty, rxactive, txactive, cmdactive, datablockend, startbiterr, dataend, cmdsent, cmdrespend, rxoverrun, txunderrun, datatimeout, cmdtimeout, datacrcfail, cmdcrcfail 30 46 0xb8 motor control pwm iper[2:0], ipw[2:0], icap[2:0], fes 31 47 0xbc quadrature encoder inx_int, tim_int, velc_int, dir_int, err_int, enclk_int, pos0_int, pos1_int, pos2_int , rev_int, pos0rev_int, pos1rev_int, pos2rev_int 32 48 0xc0 pll1 (alt pll) pll1 lock (plock1) 33 49 0xc4 usb activity interrupt usb_need_clk 34 50 0xc8 can activity interrupt can1wake, can2wake 35 51 0xcc uart4 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) end of auto-baud (abeo) auto-baud time-out (abto) table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 82 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.4 vector table remapping the cortex-m4 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. th is is controlled via the vector table offset register (vtor) contained in the cortex-m4. the vector table may be located anywhere wi thin the bottom 1 gb of cortex-m4 address space. the vector table should be located on a 256 word (1024 byte) boundary to insure alignment. see the arm cortex-m4 user guide referred to in section 40.1 for details of the vector table offset feature. arm describes bit 29 of the vtor (tbloff) as selecting a memory region, either code or sram. for simplicity, this bit can be thought as simply part of the address offset since the split between the ?code? space and t he ?sram? space occurs at the location corresponding to bit 29 in a memory address. examples: to place the vector table at the beginning of the main sram, starting at address 0x1000 0000, place the value 0x1000 0000 in the vtor register. this indicates address 0x1000 0000 in the code space, since bit 29 of the vtor equals 0. to place the vector table at the beginning of the peripheral sram, starting at address 0x2000 0000, place the value 0x2000 0000 in the vtor register. this indicates address 0x2000 0000 in the sram space, since bit 29 of the vtor equals 1. 36 52 0xd0 ssp2 tx fifo half empty of ssp2 rx fifo half full of ssp2 rx timeout of ssp2 rx overrun of ssp2 37 53 0xd4 lcd controller ber, vcompi, lnbui, fufi, crsri 38 54 0xd8 gpio interrupts p0xrei, p2xrei, p0xfei, p2xfei 39 55 0xdc pwm0 match 0 - 6 of pwm0 capture 0-1 of pwm0 40 56 0xe0 eeprom ee_prog_done, ee_rw_done table 50. connection of interrupt sources to the vectored interrupt controller interrupt id exception number vector offset function flag(s)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 83 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5 register description the following table summarizes the registers in the nvic as implemented in lpc408x/407x devices. see the arm cortex-m4 user guide referred to in section 40.1 for functional details of the nvic. table 51. nvic register map name description access reset value address table iser0 to iser1 interrupt set-enable registers. these registers allow enabling interrupts and reading back the interrupt enables for specific peripheral functions. rw 0 iser0 - 0xe000 e100 iser1 - 0xe000 e104 52 53 icer0 to icer1 interrupt clear-enable registers. these registers allow disabling interrupts and reading back the interrupt enables for specific peripheral functions. rw 0 icer0 - 0xe000 e180 icer1 - 0xe000 e184 54 55 ispr0 to ispr1 interrupt set-pending registers. these registers allow changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. rw 0 ispr0 - 0xe000 e200 ispr1 - 0xe000 e204 56 57 icpr0 to icpr1 interrupt clear-pending registers. these registers allow changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. rw 0 icpr0 - 0xe000 e280 icpr1 - 0xe000 e284 58 59 iabr0 to iabr1 interrupt active bit registers. these registers allow reading the current interrupt active state for specific peripheral functions. ro 0 iabr0 - 0xe000 e300 iabr1 - 0xe000 e304 60 61 ipr0 to ipr10 interrupt priority registers. these registers allow assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. rw 0 ipr0 - 0xe000 e400 ipr1 - 0xe000 e404 ipr2 - 0xe000 e408 ipr3 - 0xe000 e40c ipr4 - 0xe000 e410 ipr5 - 0xe000 e414 ipr6 - 0xe000 e418 ipr7 - 0xe000 e41c ipr8 - 0xe000 e420 ipr9 - 0xe000 e424 ipr10 - 0xe000 e428 62 63 64 65 66 67 68 69 70 71 72 stir software trigger interrupt register. this register allows software to generate an interrupt. wo - stir - 0xe000 ef00 73
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 84 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.1 interrupt set-enab le register 0 register the iser0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. the remaining interrupts are enabled via the iser1 register ( section 5.5.2 ). disabling interrupts is do ne through the icer0 and icer1 registers ( section 5.5.3 and section 5.4 ). table 52. interrupt set-ena ble register 0 register bit name function 0 ise_wdt watchdog timer interrupt enable. write: writing 0 has no effect, writing 1 enables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ise_timer0 timer 0 interrupt enable. see functional description for bit 0. 2 ise_timer1 timer 1 interrupt enable. see functional description for bit 0. 3 ise_timer2 timer 2 interrupt enable. see functional description for bit 0. 4 ise_timer3 timer 3 interrupt enable. see functional description for bit 0. 5 ise_uart0 uart0 interrupt enable. see functional description for bit 0. 6 ise_uart1 uart1 interrupt enable. see functional description for bit 0. 7 ise_uart2 uart2 interrupt enable. see functional description for bit 0. 8 ise_uart3 uart3 interrupt enable. see functional description for bit 0. 9 ise_pwm1 pwm1 interrupt enable. see functional description for bit 0. 10 ise_i2c0 i 2 c0 interrupt enable. see functional description for bit 0. 11 ise_i2c1 i 2 c1 interrupt enable. see functional description for bit 0. 12 ise_i2c2 i 2 c2 interrupt enable. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 ise_ssp0 ssp0 interrupt enable. see functional description for bit 0. 15 ise_ssp1 ssp1 interrupt enable. see functional description for bit 0. 16 ise_pll0 pll0 (main pll) interrupt enable. see functional description for bit 0. 17 ise_rtc real time clock (rtc) and event monitor/recorder interrupt enable. see description of bit 0. 18 ise_eint0 external interrupt 0 interrupt enable. see functional description for bit 0. 19 ise_eint1 external interrupt 1 interrupt enable. see functional description for bit 0. 20 ise_eint2 external interrupt 2 interrupt enable. see functional description for bit 0. 21 ise_eint3 external interrupt 3 interrupt enable. see functional description for bit 0. 22 ise_adc adc interrupt enable. see functional description for bit 0. 23 ise_bod bod interrupt enable. see functional description for bit 0. 24 ise_usb usb interrupt enable. see functional description for bit 0. 25 ise_can can interrupt enable. see functional description for bit 0. 26 ise_dma gpdma interrupt enable. see functional description for bit 0. 27 ise_i2s i 2 s interrupt enable. see functional description for bit 0. 28 ise_enet ethernet interrupt enable. see functional description for bit 0. 29 ise_sd sd card interface interrupt enable. see functional description for bit 0. 30 ise_mcpwm motor control pwm interrupt enable. see functional description for bit 0. 31 ise_qei quadrature encoder interface interrupt enable. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 85 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.2 interrupt set-enab le register 1 register the iser1 register allows enabling the seco nd group of peripheral interrupts, or for reading the enabled state of those interrupts. disabling interrupts is done through the icer0 and icer1 registers ( section 5.5.3 and section 5.4 ). table 53. interrupt set-ena ble register 1 register bit name function 0 ise_pll1 pll1 (alt pll) interrupt enable. write: writing 0 has no effect, writing 1 enables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ise_usbact usb activity interrupt enable. see functional description for bit 0. 2 ise_canact can activity interrupt enable. see functional description for bit 0. 3 ise_uart4 uart4 interrupt enable. see functional description for bit 0. 4 ise_ssp2 ssp2 interrupt enable. see functional description for bit 0. 5 ise_lcd lcd interrupt enable. see functional description for bit 0. 6 ise_gpio gpio interrupt enable. see functional description for bit 0. 7 ise_pwm0 pwm0 interrupt enable. see functional description for bit 0. 8 ise_flash flash and eeprom interrupt enable. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 86 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.3 interrupt clear-enable register 0 the icer0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. the remain ing interrupts are disabled via the icer1 register ( section 5.4 ). enabling interrupts is done th rough the iser0 and iser1 registers ( section 5.5.1 and section 5.5.2 ). table 54. interrupt clear-enable register 0 bit name function 0 ice_wdt watchdog timer interrupt disable. write: writing 0 has no effect, writing 1 disables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ice_timer0 timer 0 interrupt disable. see functional description for bit 0. 2 ice_timer1 timer 1 interrupt disable. see functional description for bit 0. 3 ice_timer2 timer 2 interrupt disable. see functional description for bit 0. 4 ice_timer3 timer 3 interrupt disable. see functional description for bit 0. 5 ice_uart0 uart0 interrupt disable. see functional description for bit 0. 6 ice_uart1 uart1 interrupt disable. see functional description for bit 0. 7 ice_uart2 uart2 interrupt disable. see functional description for bit 0. 8 ice_uart3 uart3 interrupt disable. see functional description for bit 0. 9 ice_pwm1 pwm1 interrupt disable. see functional description for bit 0. 10 ice_i2c0 i 2 c0 interrupt disable. see functional description for bit 0. 11 ice_i2c1 i 2 c1 interrupt disable. see functional description for bit 0. 12 ice_i2c2 i 2 c2 interrupt disable. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 ice_ssp0 ssp0 interrupt disable. s ee functional descr iption for bit 0. 15 ice_ssp1 ssp1 interrupt disable. s ee functional descr iption for bit 0. 16 ice_pll0 pll0 (main pll) interrupt disable. see functional description for bit 0. 17 ice_rtc real time clock (rtc) and event monitor/recorder interrupt disable. see description of bit 0. 18 ice_eint0 external interrupt 0 interrupt disable. see functional description for bit 0. 19 ice_eint1 external interrupt 1 interrupt disable. see functional description for bit 0. 20 ice_eint2 external interrupt 2 interrupt disable. see functional description for bit 0. 21 ice_eint3 external interrupt 3 interrupt disable. see functional description for bit 0. 22 ice_adc adc interrupt disable. see functional description for bit 0. 23 ice_bod bod interrupt disable. see functional description for bit 0. 24 ice_usb usb interrupt disable. see functional description for bit 0. 25 ice_can can interrupt disable. see functional description for bit 0. 26 ice_dma gpdma interrupt disable. see functional description for bit 0. 27 ice_i2s i 2 s interrupt disable. see functional description for bit 0. 28 ice_enet ethernet interrupt disable. see functional description for bit 0. 29 ice_sd sd card interface interrupt disable. see functional description for bit 0. 30 ice_mcpwm motor control pwm interrupt disable. see functional description for bit 0. 31 ice_qei quadrature encoder interface interrupt disable. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 87 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.4 interrupt clear-enable register 1 register the icer1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. enabling interrupts is done through the iser0 and iser1 registers ( section 5.5.1 and section 5.5.2 ). table 55. interrupt clear-enable register 1 register bit name function 0 ice_pll1 pll1 (alt pll) interrupt disable. write: writing 0 has no effect, writing 1 disables the interrupt. read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled. 1 ice_usbact usb activity interrupt disabl e. see functional description for bit 0. 2 ice_canact can activity interrupt disable. see functional description for bit 0. 3 ice_uart4 uart4 interrupt disable. see functional description for bit 0. 4 ice_ssp2 ssp2 interrupt disable. s ee functional descr iption for bit 0. 5 ice_lcd lcd interrupt disable. see functional description for bit 0. 6 ice_gpio gpio interrupt disable. see functional description for bit 0. 7 ice_pwm0 pwm0 interrupt disable. see functional description for bit 0. 8 ice_eeprom eeprom interrupt disable. se e functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 88 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.5 interrupt set-pend ing register 0 register the ispr0 register allows setting the pending st ate of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. the remaining interrupts can have their pending state set via the ispr1 register ( section 5.5.6 ). clearing the pending state of interrupts is done through the icpr0 and icpr1 registers ( section 5.5.7 and section 5.5.8 ). table 56. interrupt set-pen ding register 0 register bit name function 0 isp_wdt watchdog timer interrupt pending set. write: writing 0 has no effect, writing 1 changes the interrupt state to pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 isp_timer0 timer 0 interrupt pending set. see functional description for bit 0. 2 isp_timer1 timer 1 interrupt pending set. see functional description for bit 0. 3 isp_timer2 timer 2 interrupt pending set. see functional description for bit 0. 4 isp_timer3 timer 3 interrupt pending set. see functional description for bit 0. 5 isp_uart0 uart0 interrupt pending set. see functional description for bit 0. 6 isp_uart1 uart1 interrupt pending set. see functional description for bit 0. 7 isp_uart2 uart2 interrupt pending set. see functional description for bit 0. 8 isp_uart3 uart3 interrupt pending set. see functional description for bit 0. 9 isp_pwm1 pwm1 interrupt pending set. see functional description for bit 0. 10 isp_i2c0 i 2 c0 interrupt pending set. see functional description for bit 0. 11 isp_i2c1 i 2 c1 interrupt pending set. see functional description for bit 0. 12 isp_i2c2 i 2 c2 interrupt pending set. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 isp_ssp0 ssp0 interrupt pending set. s ee functional descr iption for bit 0. 15 isp_ssp1 ssp1 interrupt pending set. s ee functional descr iption for bit 0. 16 isp_pll0 pll0 (main pll) interrupt pending set. see functional description for bit 0. 17 isp_rtc real time clock (rtc) and event monitor/recorder interrupt pending set. see description of bit 0. 18 isp_eint0 external interrupt 0 interrupt pending set. see functional description for bit 0. 19 isp_eint1 external interrupt 1 interrupt pending set. see functional description for bit 0. 20 isp_eint2 external interrupt 2 interrupt pending set. see functional description for bit 0. 21 isp_eint3 external interrupt 3 interrupt pending set. see functional description for bit 0. 22 isp_adc adc interrupt pending set. see functional description for bit 0. 23 isp_bod bod interrupt pending set. see functional description for bit 0. 24 isp_usb usb interrupt pending set. see functional description for bit 0. 25 isp_can can interrupt pending set. see functional description for bit 0. 26 isp_dma gpdma interrupt pending set. see functional description for bit 0. 27 isp_i2s i 2 s interrupt pending set. see functional description for bit 0. 28 isp_enet ethernet interrupt pending set. see functional description for bit 0. 29 isp_sd sd card interface interrupt pending set. see functional description for bit 0. 30 isp_mcpwm motor control pwm interrupt pending set. see functional description for bit 0. 31 isp_qei quadrature encoder interface interrupt pending set. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 89 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.6 interrupt set-pend ing register 1 register the ispr1 register allows setting the pendin g state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. clearing the pending state of interrupts is done through the icpr0 and icpr1 registers ( section 5.5.7 and section 5.5.8 ). table 57. interrupt set-pen ding register 1 register bit name function 0 isp_pll1 pll1 (alt pll) interrupt pending set. write: writing 0 has no effect, writing 1 changes the interrupt state to pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 isp_usbact usb activity interrupt pending se t. see functional de scription for bit 0. 2 isp_canact can activity interrupt pending set. see functional description for bit 0. 3 isp_uart4 uart4 interrupt pending set. see functional description for bit 0. 4 isp_ssp2 ssp2 interrupt pending set. see functional description for bit 0. 5 isp_lcd lcd interrupt pending set. see functional description for bit 0. 6 isp_gpio gpio interrupt pending set. see functional description for bit 0. 7 isp_pwm0 pwm0 interrupt pending set. see functional description for bit 0. 8 isp_eeprom eeprom interrupt pending set. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 90 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.7 interrupt clear-pe nding register 0 register the icpr0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. the remaining interrupts can have their pending state cleared via the icpr1 register ( section 5.5.8 ). setting the pending state of interrupts is done through the ispr0 and ispr1 registers ( section 5.5.5 and section 5.5.6 ). table 58. interrupt clear-pending register 0 register bit name function 0 icp_wdt watchdog timer interrupt pending clear. write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 icp_timer0 timer 0 interrupt pending clear. see functional description for bit 0. 2 icp_timer1 timer 1 interrupt pending clear. see functional description for bit 0. 3 icp_timer2 timer 2 interrupt pending clear. see functional description for bit 0. 4 icp_timer3 timer 3 interrupt pending clear. see functional description for bit 0. 5 icp_uart0 uart0 interrupt pending clear. see functional description for bit 0. 6 icp_uart1 uart1 interrupt pending clear. see functional description for bit 0. 7 icp_uart2 uart2 interrupt pending clear. see functional description for bit 0. 8 icp_uart3 uart3 interrupt pending clear. see functional description for bit 0. 9 icp_pwm1 pwm1 interrupt pending clear. see functional description for bit 0. 10 icp_i2c0 i 2 c0 interrupt pending clear. see functional description for bit 0. 11 icp_i2c1 i 2 c1 interrupt pending clear. see functional description for bit 0. 12 icp_i2c2 i 2 c2 interrupt pending clear. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 icp_ssp0 ssp0 interrupt p ending clear. see functiona l description for bit 0. 15 icp_ssp1 ssp1 interrupt p ending clear. see functiona l description for bit 0. 16 icp_pll0 pll0 (main pll) interrupt pending clear. see functional description for bit 0. 17 icp_rtc real time clock (rtc) and event monitor/recorder interrupt pending clear. see description of bit 0. 18 icp_eint0 external interrupt 0 interrupt pending clear. see functional description for bit 0. 19 icp_eint1 external interrupt 1 interrupt pending clear. see functional description for bit 0. 20 icp_eint2 external interrupt 2 interrupt pending clear. see functional description for bit 0. 21 icp_eint3 external interrupt 3 interrupt pending clear. see functional description for bit 0. 22 icp_adc adc interrupt pending clear. see functional description for bit 0. 23 icp_bod bod interrupt pending clear. see functional description for bit 0. 24 icp_usb usb interrupt pending clear. see functional description for bit 0. 25 icp_can can interrupt pending clear. see functional description for bit 0. 26 icp_dma gpdma interrupt pending clear. see functional description for bit 0. 27 icp_i2s i 2 s interrupt pending clear. see functional description for bit 0. 28 icp_enet ethernet interrupt pending clear. see functional description for bit 0. 29 icp_sd sd card interface interrupt pending clear. see functional description for bit 0. 30 icp_mcpwm motor control pwm interrupt pending clear. see functional description for bit 0. 31 icp_qei quadrature encoder interface interrupt pending clear. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 91 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.8 interrupt clear-pe nding register 1 register the icpr1 register allows clearing the pendi ng state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. setting the pending state of interrupts is done through the ispr0 and ispr1 registers ( section 5.5.5 and section 5.5.6 ). table 59. interrupt clear-pending register 1 register bit name function 0 icp_pll1 pll1 (alt pll) interrupt pending clear. write: writing 0 has no effect, writing 1 changes the interrupt state to not pending. read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending. 1 icp_usbact usb activity interrupt pending clear. see functional description for bit 0. 2 icp_canact can activity interrupt pending clear. see functional description for bit 0. 3 icp_uart4 uart4 interrupt pending clear. see functional description for bit 0. 4 icp_ssp2 ssp2 interrupt pending clear. see functional description for bit 0. 5 icp_lcd lcd interrupt pending clear. see functional description for bit 0. 6 icp_gpio gpio interrupt pending clear. see functional description for bit 0. 7 icp_pwm0 pwm0 interrupt pending clear. see functional description for bit 0. 8 icp_eeprom eeprom interrupt pending clear. see functional description for bit 0. 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 92 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.9 interrupt acti ve bit register 0 the iabr0 register is a read-onl y register that allows reading the active state of the first 32 peripheral interrupts. bits in iabr are set while the corresponding interrupt service routines are in progress. additional interrupt s can have their active state read via the iabr1 register ( section 5.5.10 ). table 60. interrupt ac tive bit register 0 bit name function 0 iab_wdt watchdog timer interrupt active. read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 iab_timer0 timer 0 interrupt active. see functional description for bit 0. 2 iab_timer1 timer 1 interrupt active. see functional description for bit 0. 3 iab_timer2 timer 2 interrupt active. see functional description for bit 0. 4 iab_timer3 timer 3 interrupt active. see functional description for bit 0. 5 iab_uart0 uart0 interrupt active. see functional description for bit 0. 6 iab_uart1 uart1 interrupt active. see functional description for bit 0. 7 iab_uart2 uart2 interrupt active. see functional description for bit 0. 8 iab_uart3 uart3 interrupt active. see functional description for bit 0. 9 iab_pwm1 pwm1 interrupt active. see functional description for bit 0. 10 iab_i2c0 i 2 c0 interrupt active. see functional description for bit 0. 11 iab_i2c1 i 2 c1 interrupt active. see functional description for bit 0. 12 iab_i2c2 i 2 c2 interrupt active. see functional description for bit 0. 13 - reserved. read value is undefined, only zero should be written. 14 iab_ssp0 ssp0 interrupt active. see functional description for bit 0. 15 iab_ssp1 ssp1 interrupt active. see functional description for bit 0. 16 iab_pll0 pll0 (main pll) interrupt active. see functional description for bit 0. 17 iab_rtc real time clock (rtc) and event monitor/recorder interrupt active. see description of bit 0. 18 iab_eint0 external interrupt 0 interrupt active. see functional description for bit 0. 19 iab_eint1 external interrupt 1 interrupt active. see functional description for bit 0. 20 iab_eint2 external interrupt 2 interrupt active. see functional description for bit 0. 21 iab_eint3 external interrupt 3 interrupt active. see functional description for bit 0. 22 iab_adc adc interrupt active. see functional description for bit 0. 23 iab_bod bod interrupt active. see functional description for bit 0. 24 iab_usb usb interrupt active. see functional description for bit 0. 25 iab_can can interrupt active. see functional description for bit 0. 26 iab_dma gpdma interrupt active. see functional description for bit 0. 27 iab_i2s i 2 s interrupt active. see functional description for bit 0. 28 iab_enet ethernet interrupt active. see functional description for bit 0. 29 iab_sd repetitive interrupt timer interrupt active. see functional description for bit 0. 30 iab_mcpwm motor control pwm interrupt active. see functional description for bit 0. 31 iab_qei quadrature encoder interface interrupt active. see functional description for bit 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 93 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.10 interrupt acti ve bit register 1 the iabr1 register is a read-o nly register that allows reading the active state of the second group of peripheral interrupts. bits in iabr are set while the corresponding interrupt service routin es are in progress. table 61. interrupt ac tive bit register 1 bit name function 0 iab_pll1 pll1 (alt pll) interrupt active. read: 0 indicates that the interrupt is not active, 1 indicates that the interrupt is active. 1 iab_usbact usb activity interrupt active . see functional description for bit 0. 2 iab_canact can activity interrupt active. see functional description for bit 0. 3 iab_uart4 uart4 interrupt active. see functional description for bit 0. 4 iab_ssp2 ssp2 interrupt active. see functional description for bit 0. 5 iab_lcd lcd interrupt active. see functional description for bit 0. 6 iab_gpio gpio interrupt active. see functional description for bit 0. 7 iab_pwm0 pwm0 interrupt active. see functional description for bit 0. 8 iab_eeprom eeprom interrupt active. see functional description for bit 0. 31:9 - reserved. the value read from a reserved bit is not defined.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 94 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.11 interrupt priority register 0 the ipr0 register controls the priority of the first 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.12 interrupt priority register 1 the ipr1 register controls the priority of th e second group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.13 interrupt priority register 2 the ipr2 register controls the priority of t he third group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. table 62. interrupt priority register 0 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_wdt watchdog timer interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_timer0 timer 0 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_timer1 timer 1 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_timer2 timer 2 interrupt priority. see functional description for bits 7-3. table 63. interrupt priority register 1 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_timer3 timer 3 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_uart0 uart0 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_uart1 uart1 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_uart2 uart2 interrupt priority. see functional description for bits 7-3. table 64. interrupt priority register 2 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_uart3 uart3 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_pwm1 pwm1 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_i2c0 i 2 c0 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_i2c1 i 2 c1 interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 95 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.14 interrupt priority register 3 the ipr3 register controls the priority of t he fourth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.15 interrupt priority register 4 the ipr4 register controls the priority of t he fifth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.16 interrupt priority register 5 the ipr5 register controls the priority of t he sixth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. table 65. interrupt priority register 3 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_i2c2 i 2 c2 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 - reserved. read value is undefined, only zero should be written. 18:8 unimplemented these bits ignore writes, and read as 0. 23:19 ip_ssp0 ssp0 interrupt pr iority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_ssp1 ssp1 interrupt pr iority. see functional description for bits 7-3. table 66. interrupt priority register 4 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_pll0 pll0 (main pll) interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_rtc real time clock (rtc) interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_eint0 external interrupt 0 interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_eint1 external interrupt 1 interrupt priority. see functional description for bits 7-3. table 67. interrupt priority register 5 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_eint2 external interrupt 2 interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_eint3 external interrupt 3 interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_adc adc interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_bod bod interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 96 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.17 interrupt priority register 6 the ipr6 register controls the priority of the seventh group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.18 interrupt priority register 7 the ipr7 register controls the priority of the eighth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.19 interrupt priority register 8 the ipr8 register controls the priority of the ninth and last group of 4 peripheral interrupts. each interrupt can have one of 32 prio rities, where 0 is the highest priority. table 68. interrupt priority register 6 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_usb usb interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_can can interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_dma gpdma interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_i2s i 2 s interrupt priority. see functional description for bits 7-3. table 69. interrupt priority register 7 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_enet ethernet interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_sd sd card interface interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_mcpwm motor control pwm interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_qei quadrature encoder interface interrupt pr iority. see functional description for bits 7-3. table 70. interrupt priority register 8 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_pll1 pll1 (alt pll) interrupt priority. 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_usbact usb activity inte rrupt priority. see functio nal description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_canact can activity interrupt priority. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_uart4 uart4 interrupt priority. see functional description for bits 7-3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 97 of 942 nxp semiconductors UM10562 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.5.20 interrupt priority register 9 the ipr9 register controls the priority of t he tenth group of 4 peripheral interrupts. each interrupt can have one of 32 priorities, where 0 is the highest priority. 5.5.21 interrupt priority register 10 the ipr10 register controls the priority of th e eleventh group of 4 peripheral interrupts. each interrupt can have one of 32 prio rities, where 0 is the highest priority. 5.5.22 software trigge r interrupt register the stir register provides an alternate way for software to generate an interrupt, in addition to using the ispr registers. th is mechanism can only be used to generate peripheral interrupts, not system exceptions. by default, only privileged software can writ e to the stir register. unprivileged software can be given this ab ility if privileged software sets the usersetmpend bit in the ccr register (see the arm cortex-m4 user guide referred to in section 40.1 for details). table 71. interrupt priority register 9 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_ssp2 ssp2 interrupt priority . 0 = highest priority. 31 (0x1f) = lowest priority. 10:8 unimplemented these bits ignore writes, and read as 0. 15:11 ip_lcd lcd controller interrupt priority. see functional description for bits 7-3. 18:16 unimplemented these bits ignore writes, and read as 0. 23:19 ip_gpio priority of gpio interrupts. see functional description for bits 7-3. 26:24 unimplemented these bits ignore writes, and read as 0. 31:27 ip_pwm0 pwm0 interrupt priority. see functional description for bits 7-3. table 72. interrupt priority register 10 bit name function 2:0 unimplemented these bits ignore writes, and read as 0. 7:3 ip_eeprom eeprom programming in terrupt. 0 = highest priority. 31 (0x1f) = lowest priority. 31:8 unimplemented these bits ignore writes, and read as 0. table 73. software trigger interrupt register bit name function 8:0 intid writing a value to this field generates an interrupt for the specified interrupt id (see ta b l e 5 0 ). 31:9 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 98 of 942 6.1 pin configuration for information about the individual lpc408x/407 x devices, refer to specific data sheets. ta b l e 7 4 lists pins in order by pin name, and in cludes description of each potential pin function. see the iocon registers ( section 7.4.1 ) to configure pins for the desired function. i/o pins are 5v tolerant and have input hyster esis unless otherwise indicated in the table below. crystal pins, power pins, and reference voltage pins are not 5v tolerant. in addition, when pins are selected to be a to d converter inputs, they are no longer 5v tolerant and must be limited to the voltage at the adc positive reference pin (vrefp). UM10562 chapter 6: lpc408x/407x pin configuration rev. 1 ? 13 september 2012 user manual table 74. pin description symbol type iocon select [1] description p0[0] to p0[31] i/o port 0: port 0 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p0[0]/ can_rd1/ u3_txd/ i2c1_sda/ u0_txd i/o 0 p0[0] ? general purpose digital input/output pin. i1 can_rd1 ? can1 receiver input. o2 u3_txd ? transmitter output for uart 3. i/o 3 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 4 u0_txd ? transmitter output for uart 0. p0[1]/ can1_td/ u3_rxd/ i2c1_scl/ u0_rxd i/o 0 p0[1] ? general purpose digital input/output pin. o1 can1_td ? can1 transmitter output. i2 u3_rxd ? receiver input for uart 3. i/o 3 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i4 u0_rxd ? receiver input for uart 0. p0[2]/ u0_txd/ u3_txd i/o 0 p0[2] ? general purpose digital input/output pin. o1 u0_txd ? transmitter output for uart 0. used for isp communication, see section 38.1 . o2 u3_txd ? transmitter output for uart 3. p0[3]/ u0_rxd/ u3_rxd i/o 0 p0[3] ? general purpose digital input/output pin. i1 u0_rxd ? receiver input for uart 0. used for isp communication, see section 38.1 . i2 u3_rxd ? receiver input for uart 3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 99 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[4]/ i2s_rx_sck/ can_rd2/ t2_cap0/ cmp_rosc/ lcd_vd[0] i/o 0 p0[4] ? general purpose digital input/output pin. i/o 1 i2s_rx_sck ? i 2 s receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i2 can_rd2 ? can2 receiver input. i3 t2_cap0 ? capture input for timer 2, channel 0. o5 cmp_rosc ? comparator relaxation oscillator output. o7 lcd_vd[0] ? lcd data. p0[5]/ i2s_rx_ws/ can_td2/ t2_cap1/ cmp_reset/ lcd_vd[1] i/o 0 p0[5] ? general purpose digital input/output pin. i/o 1 i2s_rx_ws ? i 2 s receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o2 can_td2 ? can2 transmitter output. i3 t2_cap1 ? capture input for timer 2, channel 1. o5 cmp_reset ? comparator reset input. o7 lcd_vd[1] ? lcd data. p0[6]/ i2s_rx_sda/ ssp1_ssel/ t2_mat0/ u1_rts/ cmp_rosc/ lcd_vd[8] i/o 0 p0[6] ? general purpose digital input/output pin. i/o 1 i2s_rx_sda ? i 2 s receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o 2 ssp1_ssel1 ? slave select for ssp1. o3 t2_mat0 ? match output for timer 2, channel 0. o4 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o5 cmp_rosc ? comparator relaxation oscillator output. o7 lcd_vd[8] ? lcd data. p0[7]/ i2s_tx_sck/ ssp1_sck/ t2_mat1/ rtc_ev0/ cmp_vref/ lcd_vd[9] i/o 0 p0[7] ? general purpose digital input/output pin. i/o 1 i2s_tx_sck ? i 2 s transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i/o 2 ssp1_sck ? serial clock for ssp1. o3 t2_mat1 ? match output for timer 2, channel 1. i4 rtc_ev0 ? event input 0 to event monitor/recorder. o5 cmp_vref ? comparator voltage reference input. o7 lcd_vd[9] ? lcd data. p0[8]/ i2s_tx_ws/ ssp1_miso/ t2_mat2/ rtc_ev1/ cmp1_in[4]/ lcd_vd[16] i/o 0 p0[8] ? general purpose digital input/output pin. i/o 1 i2s_tx_ws ? i 2 s transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i/o 2 ssp1_miso ? master in slave out for ssp1. o3 t2_mat2 ? match output for timer 2, channel 2. i4 rtc_ev1 ? event input 1 to event monitor/recorder. o5 cmp1_in[4] ? comparator input. o7 lcd_vd[16] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 100 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[9]/ i2s_tx_sda/ ssp1_mosi/ t2_mat3/ rtc_ev2/ cmp1_in[3]/ lcd_vd[17] i/o 0 p0[9] ? general purpose digital input/output pin. i/o 1 i2s_tx_sda ? i 2 s transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . i/o 2 ssp1_mosi ? master out slave in for ssp1. o3 t2_mat3 ? match output for timer 2, channel 3. i4 rtc_ev2 ? event input 2 to event monitor/recorder. o5 cmp1_in[3] ? comparator input. o7 lcd_vd[17] ? lcd data. p0[10]/ u2_txd/ i2c2_sda/ t3_mat0/ lcd_vd[5] i/o 0 p0[10] ? general purpose digital input/output pin. o1 u2_txd ? transmitter output for uart 2. i/o 2 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat0 ? match output for timer 3, channel 0. o7 lcd_vd[5] ? lcd data. p0[11]/ u2_rxd/ i2c2_scl/ t3_mat1/ lcd_vd[10] i/o 0 p0[11] ? general purpose digital input/output pin. i1 u2_rxd ? receiver input for uart 2. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat1 ? match output for timer 3, channel 1. o7 lcd_vd[10] ? lcd data. p0[12]/ usb_ppwr2 / ssp1_miso/ ad0[6] i/o 0 p0[12] ? general purpose digital input/output pin. o1 usb_ppwr2 ? port power enable signal for usb port 2. i/o 2 ssp1_miso ? master in slave out for ssp1. i3 ad0[6] ? a/d converter 0, input 6. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). p0[13]/ usb_up_led2/ ssp1_mosi/ ad0[7] i/o 0 p0[13] ? general purpose digital input/output pin. o1 usb_up_led2 ? usb port 2 goodlink led indicator. it is low when device is configured (non-control endpoints enabled) or when host is enabled and has detected a device on the bus. it is high when the device is not configured, when host is enabled and has not detected a device on the bus, or during global suspend. it toggles between low and high when host is enabled and detects activity on the bus. i/o 2 ssp1_mosi ? master out slave in for ssp1. i3 ad0[7] ? a/d converter 0, input 7. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). p0[14]/ usb_hsten2 / ssp1_ssel/ usb_connect2 i/o 0 p0[14] ? general purpose digital input/output pin. o1 usb_hsten2 ? host enabled status for usb port 2. i/o 2 ssp1_ssel ? slave select for ssp1. o3 usb_connect2 ? softconnect control for usb port 2. the usb_connect pin indicates when the pull-up resistor must be enabled when running in usb device mode. if it is used in usb device mode, this function can be implemented by using another gpio pin. if the chip is only used in usb host mode, there is no need to use this pin. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 101 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[15]/ u1_txd/ ssp0_sck/ spifi_io[2] i/o 0 p0[15] ? general purpose digital input/output pin. o1 u1_txd ? transmitter output for uart 1. i/o 2 ssp0_sck ? serial clock for ssp0. i/o 5 spifi_io[2] ? data bit 2 for spifi. p0[16]/ u1_rxd/ ssp0_ ssel/ spifi_io[3] i/o 0 p0 [16] ? general purpose digital input/output pin. i1 u1_rxd ? receiver input for uart 1. i/o 2 ssp0_ssel ? slave select for ssp0. i/o 5 spifi_io[3] ? data bit 3 for spifi. p0[17]/ u1_cts/ ssp0_miso/ spifi_io[1] i/o 0 p0[17] ? general purpose digital input/output pin. i1 u1_cts ? clear to send input for uart 1. i/o 2 ssp0_miso ? master in slave out for ssp0. i/o 5 spifi_io[1] ? data bit 1 for spifi. p0[18]/ u1_dcd/ ssp0_mosi/ spifi_io[0] i/o 0 p0[18] ? general purpose digital input/output pin. i1 u1_dcd ? data carrier detect input for uart 1. i/o 2 ssp0_mosi ? master out slave in for ssp0. i/o 5 spifi_io[0] ? data bit 0 for spifi. p0[19]/ u1_dsr/ sd_clk/ i2c1_sda/ lcd_vd[13] i/o 0 p0[19] ? general purpose digital input/output pin. i1 u1_dsr ? data set ready input for uart 1. o2 sd_clk ? clock output line for sd card interface. i/o 3 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o7 lcd_vd[13] ? lcd data. p0[20]/ u1_dtr/ sd_cmd/ i2c1_scl/ lcd_vd[14] i/o 0 p0[20] ? general purpose digital input/output pin. o1 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o 2 sd_cmd ? command line for sd card interface. i/o 3 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o7 lcd_vd[14] ? lcd data. p0[21]/ u1_ri/ sd_pwr/ u4_oe/ can_rd1 i/o 0 p0[21] ? general purpose digital input/output pin. i1 u1_ri ? ring indicator input for uart 1. o2 sd_pwr ? power supply enable for external sd card power supply. o3 u4_oe ? rs-485/eia-485 output enable signal for uart 4. i4 can_rd1 ? can1 receiver input. i/o 5 u4_sclk ? uart 4 clock input or output in synchronous mode. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 102 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[22]/ u1_rts/ sd_dat[0]/ u4_txd/ can_td1/ spifi_clk i/o 0 p0[22] ? general purpose digital input/output pin. o1 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. i/o 2 sd_dat[0] ? data line 0 for sd card interface. o3 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). o4 can_td1 ? can1 transmitter output. o5 spifi_clk ? clock output for spifi. p0[23]/ ad0[0]/ i2s_rx_sck/ t3_cap0 i/o 0 p0[23] ? general purpose digital input/output pin. i1 ad0[0] ? a/d converter 0, input 0. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_sck ? receive clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . i3 t3_cap0 ? capture input for timer 3, channel 0. p0[24]/ ad0[1]/ i2s_rx_ws/ t3_cap1 i/o 0 p0[24] ? general purpose digital input/output pin. i1 ad0[1] ? a/d converter 0, input 1. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_ws ? receive word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . i3 t3_cap1 ? capture input for timer 3, channel 1. p0[25]/ ad0[2]/ i2s_rx_sda/ u3_txd i/o 0 p0[25] ? general purpose digital input/output pin. i1 ad0[2] ? a/d converter 0, input 2. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 2 i2s_rx_sda ? receive data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o3 u3_txd ? transmitter output for uart 3. p0[26]/ ad0[3]/ dac_out/ u3_rxd i/o 0 p0[26] ? general purpose digital input/output pin. i1 ad0[3] ? a/d converter 0, input 3. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). o2 dac_out ? d/a converter output. when configured as the dac output, the digital function of the pin must be disabled (see section 7.4.1 ). i3 u3_rxd ? receiver input for uart 3. p0[27]/ i2c0_sda/ usb_sda i/o 0 p0[27] ? general purpose digital input/output pin. i/o 1 i2c0_sda ? i 2 c0 data input/output. (this pin uses a specialized i 2 c pad, see section 22.1 for details). i/o 2 usb_sda ? i 2 c serial data for communication with an external usb transceiver. p0[28]/ i2c0_scl/ usb_scl i/o 0 p0[28] ? general purpose digital input/output pin. i/o 1 i2c0_scl0 ? i 2 c0 clock input/output (this pin uses a specialized i 2 c pad, see section 22.1 for details). i/o 2 usb_scl ? i 2 c serial clock for communication with an external usb transceiver. p0[29]/ usb_d+1/ eint0 i/o 0 p0[29] ? general purpose digital input/output pin. when used as gpio, p0[29] shares a direction control with p0[30]. i/o 1 usb_d+1 ? usb port 1 bidirectional d+ line. i2 eint0 ? external interrupt 0 input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 103 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p0[30]/ usb_d ? 1/ eint1 i/o 0 p0[30] ? general purpose digital input/output pin. when used as gpio, p0[30] shares a direction control with p0[29]. i/o 1 usb_d ? 1 ? usb port 1 bidirectional d ? line. i2 eint1 ? external interrupt 1 input. p0[31]/ usb_d+2 i/o 0 p0[31] ? general purpose digital input/output pin. i/o 1 usb_d+2 ? usb port 2 bidirectional d+ line. p1[0] to p1[31] i/o port 1: port 1 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p1[0]/ enet_txd0/ t3_cap1/ ssp2_sck i/o 0 p1[0] ? general purpose digital input/output pin. o1 enet_txd0 ? ethernet transmit data 0 (rmii/mii interface). i3 t3_cap1 ? capture input for timer 3, channel 1. i/o 4 ssp2_sck ? serial clock for ssp2. p1[1]/ enet_txd1/ t3_mat3/ ssp2_mosi i/o 0 p1[1] ? general purpose digital input/output pin. o1 enet_txd1 ? ethernet transmit data 1 (rmii/mii interface). o3 t3_mat3 ? match output for timer 3, channel 3. i/o 4 ssp2_mosi ? master out slave in for ssp2. p1[2]/ enet_txd2/ sd_clk/ pwm0[1] i/o 0 p1[2] ? general purpose digital input/output pin. o1 enet_txd2 ? ethernet transmit data 2 (mii interface). o2 sd_clk ? clock output line for sd card interface. o3 pwm0[1] ? pulse width modulator 0, output 1. p1[3]/ enet_txd3/ sd_cmd/ pwm0[2] i/o 0 p1[3] ? general purpose digital input/output pin. o1 enet_txd3 ? ethernet transmit data 3 (mii interface). i/o 2 sd_cmd ? command line for sd card interface. o3 pwm0[2] ? pulse width modulator 0, output 2. p1[4]/ enet_tx_en / t3_mat2/ ssp2_miso i/o 0 p1[4] ? general purpose digital input/output pin. o1 enet_tx_en ? ethernet transmit data enable (rmii/mii interface). o3 t3_mat2 ? match output for timer 3, channel 2. i/o 4 ssp2_miso ? master in slave out for ssp2. p1[5]/ enet_tx_er/ sd_pwr/ pwm0[3]/ cmp1_in[2] i/o 0 p1[5] ? general purpose digital input/output pin. o1 enet_tx_er ? ethernet transmit error (mii interface). o2 sd_pwr ? power supply enable for external sd card power supply. o3 pwm0[3] ? pulse width modulator 0, output 3. o5 cmp1_in[2] ? comparator input. p1[6]/ enet_tx_clk/ sd_dat[0]/ pwm0[4]/ cmp0_in[4] i/o 0 p1[6] ? general purpose digital input/output pin. i1 enet_tx_clk ? ethernet transmit clock (mii interface). i/o 2 sd_dat[0] ? data line 0 for sd card interface. o3 pwm0[4] ? pulse width modulator 0, output 4. o5 cmp0_in[4] ? comparator input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 104 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[7]/ enet_col/ sd_dat[1]/ pwm0[5] / cmp1_in[1] i/o 0 p1[7] ? general purpose digital input/output pin. i1 enet_col ? ethernet collision detect (mii interface). i/o 2 sd_dat[1] ? data line 1 for sd card interface. o3 pwm0[5] ? pulse width modulator 0, output 5. o5 cmp1_in[1] ? comparator input. p1[8]/ enet_crs (enet_crs_dv)/ t3_mat1/ ssp2_ssel i/o 0 p1[8] ? general purpose digital input/output pin. i1 enet_crs (enet_crs_dv) ? ethernet carrier sense (mii interface) or ethernet carrier sense/data valid (rmii interface). o3 t3_mat1 ? match output for timer 3, channel 1. i/o 4 ssp2_ssel ? slave select for ssp2. p1[9]/ enet_rxd0/ t3_mat0 i/o 0 p1[9] ? general purpose digital input/output pin. i1 enet_rxd0 ? ethernet receive data 0 (rmii/mii interface). o3 t3_mat0 ? match output for timer 3, channel 0. p1[10]/ enet_rxd1/ t3_cap0 i/o 0 p1[10] ? general purpose digital input/output pin. i1 enet_rxd1 ? ethernet receive data 1 (rmii/mii interface). i3 t3_cap0 ? capture input for timer 3, channel 0. p1[11]/ enet_rxd2/ sd_dat[2]/ pwm0[6] i/o 0 p1[11] ? general purpose digital input/output pin. i1 enet_rxd2 ? ethernet receive data 2 (mii interface). i/o 2 sd_dat[2] ? data line 2 for sd card interface. o3 pwm0[6] ? pulse width modulator 0, output 6. p1[12]/ enet_rxd3/ sd_dat[3]/ pwm0_cap0/ cmp1_out i/o 0 p1[12] ? general purpose digital input/output pin. i1 enet_rxd3 ? ethernet receive data (mii interface). i/o 2 sd_dat[3] ? data line 3 for sd card interface. i3 pwm0_cap0 ? capture input for pwm0, channel 0. o5 cmp1_out ? comparator 1 output. p1[13]/ enet_rx_dv i/o 0 p1[13] ? general purpose digital input/output pin. i1 enet_rx_dv ? ethernet receive data valid (mii interface). p1[14]/ enet_rx_er/ t2_cap0/ cmp0_in[1] i/o 0 p1[14] ? general purpose digital input/output pin. i1 enet_rx_er ? ethernet receive erro r (rmii/mii interface). i3 t2_cap0 ? capture input for timer 2, channel 0. o5 cmp0_in[1] ? comparator input. p1[15]/ enet_rx_clk (enet_ref_clk)/ i2c2_sda i/o 0 p1[15] ? general purpose digital input/output pin. i1 enet_rx_clk (enet_ref_clk) ? ethernet receive clock (mii interface) or ethernet reference clock (rmii interface). i/o 3 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). p1[16]/ enet_mdc/ i2s_tx_mclk/ cmp0_in[2] i/o 0 p1[16] ? general purpose digital input/output pin. o1 enet_mdc ? ethernet miim clock. o2 i2s_tx_mclk ? i 2 s transmitter master clock output. o5 cmp0_in[2] ? comparator input. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 105 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[17]/ enet_mdio/ i2s_rx_mclk/ cmp0_in[3] i/o 0 p1[17] ? general purpose digital input/output pin. i/o 1 enet_mdio ? ethernet miim data input and output. o2 i2s_rx_mclk ? i 2 s receiver master clock output. o5 cmp0_in[3] ? comparator input. p1[18]/ usb_up_led1/ pwm1[1]/ t1_cap0/ ssp1_miso i/o 0 p1[18] ? general purpose digital input/output pin. o1 usb_up_led1 ? usb port 1 goodlink led indicator. it is low when device is configured (non-control endpoints enabled) or when host is enabled and has detected a device on the bus. it is high when the device is not configured, when host is enabled and has not detected a device on the bus, or during global suspend. it toggles between low and high when host is enabled and detects activity on the bus. o2 pwm1[1] ? pulse width modulator 1, channel 1 output. i3 t1_cap0 ? capture input for timer 1, channel 0. i/o 5 ssp1_miso ? master in slave out for ssp1. p1[19]/ usb_tx_e1 / usb_ppwr1 / t1_cap1/ mc_0a/ ssp1_sck/ u2_oe i/o 0 p1[19] ? general purpose digital input/output pin. o1 usb_tx_e1 ? transmit enable signal for usb port 1 (otg transceiver). o2 usb_ppwr1 ? port power enable signal for usb port 1. i3 t1_cap1 ? capture input for timer 1, channel 1. o4 mc_0a ? motor control pwm channel 0, output a. i/o 5 ssp1_sck ? serial clock for ssp1. o6 u2_oe ? rs-485/eia-485 output enable signal for uart 2. p1[20]/ usb_tx_dp1/ pwm1[2]/ qei_pha/ mc_fb0/ ssp0_sck/ lcd_vd[6]/ lcd_vd[10] i/o 0 p1[20] ? general purpose digital input/output pin. o1 usb_tx_dp1 ? d+ transmit data for usb port 1 (otg transceiver). o2 pwm1[2] ? pulse width modulator 1, channel 2 output. i3 qei_pha ? quadrature encoder interface pha input. i4 mc_fb0 ? motor control pwm channel 0 feedback input. i/o 5 ssp0_sck0 ? serial clock for ssp0. o6 lcd_vd[6] ? lcd data. o7 lcd_vd[10] ? lcd data. p1[21]/ usb_tx_dm1/ pwm1[3]/ ssp0_ssel/ mc_abort / lcd_vd[7]/ lcd_vd[11] i/o 0 p1[21] ? general purpose digital input/output pin. o1 usb_tx_dm1 ? d ? transmit data for usb port 1 (otg transceiver). o2 pwm1[3] ? pulse width modulator 1, channel 3 output. i/o 3 ssp0_ssel ? slave select for ssp0. i4 mc_abort ? motor control pwm, active low fast abort. o6 lcd_vd[7] ? lcd data. o7 lcd_vd[11] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 106 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[22]/ usb_rcv1/ usb_pwrd1/ t1_mat0/ mc_0b/ ssp1_mosi/ lcd_vd[8]/ lcd_vd[12] i/o 0 p1[22] ? general purpose digital input/output pin. i1 usb_rcv1 ? differential receive data for usb port 1 (otg transceiver). i2 usb_pwrd1 ? power status for usb port 1 (host power switch). when using the chip in usb host mode, the usb_pwrd input must be enabled. the usb host controller will only detect a device connect event when the port power bit is set in the ohci and the usb_pwrd bit is asserted for the corresponding port. o3 t1_mat0 ? match output for timer 1, channel 0. o4 mc_0b ? motor control pwm channel 0, output b. i/o 5 ssp1_mosi ? master out slave in for ssp1. o6 lcd_vd[8] ? lcd data. o7 lcd_vd[12] ? lcd data. p1[23]/ usb_rx_dp1/ pwm1[4]/ qei_phb/ mc_fb1/ ssp0_miso/ lcd_vd[9]/ lcd_vd[13] i/o 0 p1[23] ? general purpose digital input/output pin. i1 usb_rx_dp1 ? d+ receive data for usb port 1 (otg transceiver). o2 pwm1[4] ? pulse width modulator 1, channel 4 output. i3 qei_phb ? quadrature encoder interface phb input. i4 mc_fb1 ? motor control pwm channel 1 feedback input. i/o 5 ssp0_miso ? master in slave out for ssp0. o6 lcd_vd[9] ? lcd data. o7 lcd_vd[13] ? lcd data. p1[24]/ usb_rx_dm1/ pwm1[5]/ qei_idx/ mc_fb2/ ssp0_mosi/ lcd_vd[10]/ lcd_vd[14] i/o 0 p1[24] ? general purpose digital input/output pin. i1 usb_rx_dm1 ? d ? receive data for usb po rt 1 (otg transceiver). o2 pwm1[5] ? pulse width modulator 1, channel 5 output. i3 qei_idx ? quadrature en coder interface index input. i4 mc_fb2 ? motor control pwm channel 2 feedback input. i/o 5 ssp0_mosi ? master out slave in for ssp0. o6 lcd_vd[10]/lcd_vd[14] ? lcd data. o7 lcd_vd[10]/lcd_vd[14] ? lcd data. p1[25]/ usb_ls1 / usb_hsten1 / t1_mat1/ mc_1a/ clkout/ lcd_vd[11]/ lcd_vd[15] i/o 0 p1[25] ? general purpose digital input/output pin. o1 usb_ls1 ? low speed status for usb port 1 (otg transceiver). o2 usb_hsten1 ? host enabled status for usb port 1. o3 t1_mat1 ? match output for timer 1, channel 1. o4 mc_1a ? motor control pwm channel 1, output a. o5 clkout ? selectable clock output. o6 lcd_vd[11] ? lcd data. o7 lcd_vd[15] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 107 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[26]/ usb_sspnd1 / pwm1[6]/ t0_cap0/ mc_1b/ ssp1_ssel/ lcd_vd[12]/ lcd_vd[20] i/o 0 p1[26] ? general purpose digital input/output pin. o1 usb_sspnd1 ? usb port 1 bus suspend status (otg transceiver). o2 pwm1[6] ? pulse width modulator 1, channel 6 output. i3 t0_cap0 ? capture input for timer 0, channel 0. o4 mc_1b ? motor control pwm channel 1, output b. i/o 5 ssp1_ssel ? slave select for ssp1. o6 lcd_vd[12] ? lcd data. o7 lcd_vd[20] ? lcd data. p1[27]/ usb_int1 / usb_ovrcr1 / t0_cap1/ clkout/ lcd_vd[13]/ lcd_vd[21] i/o 0 p1[27] ? general purpose digital input/output pin. i1 usb_int1 ? usb port 1 otg transceiver interrupt (otg transceiver). i2 usb_ovrcr1 ? usb port 1 over-current status. the usb_ovrcr pin is used to set status in the ohci controller to inform the host firmware that there is an overcurrent condition. it is possible to use instead a gpio pin and observe that pin for overcurrent situations. i3 t0_cap1 ? capture input for timer 0, channel 1. o4 clkout ? selectable clock output. o6 lcd_vd[13] ? lcd data. o7 lcd_vd[21] ? lcd data. p1[28]/ usb_scl1/ pwm1_cap0/ t0_mat0/ mc_2a/ ssp0_ssel/ lcd_vd[14]/ lcd_vd[22] i/o 0 p1[28] ? general purpose digital input/output pin. i/o 1 usb_scl1 ? usb port 1 i 2 c serial clock (o tg transceiver). i2 pwm1_cap0 ? capture input for pwm1, channel 0. o3 t0_mat0 ? match output for timer 0, channel 0. o4 mc_2a ? motor control pwm channel 2, output a. i/o 5 ssp0_ssel ? slave select for ssp0. o6 lcd_vd[14] ? lcd data. o7 lcd_vd[22] ? lcd data. p1[29]/ usb_sda1/ pwm1_cap1/ t0_mat1/ mc_2b/ u4_txd/ lcd_vd[15]/ lcd_vd[23] i/o 0 p1[29] ? general purpose digital input/output pin. i/o 1 usb_sda1 ? usb port 1 i 2 c serial data (otg transceiver). i2 pwm1_cap1 ? capture input for pwm1, channel 1. o3 t0_mat1 ? match output for timer 0, channel 1. o4 mc_2b ? motor control pwm channel 2, output b. o5 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). o6 lcd_vd[15] ? lcd data. o7 lcd_vd[23] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 108 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p1[30]/ usb_pwrd2/ usb_vbus/ ad0[4]/ i2c0_sda/ u3_oe i/o 0 p1[30] ? general purpose digital input/output pin. i1 usb_pwrd2 ? power status for usb port 2. when using the chip in usb host mode, the usb_pwrd input must be enabled. the usb host controller will only detect a device connect event when the port power bit is set in the ohci and the usb_pwrd bit is asserted for the corresponding port. i2 usb_vbus ? monitors the presence of usb bus power. note: this signal must be high for usb reset to occur. i3 ad0[4] ? a/d converter 0, input 4. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 4 i2c0_sda ? i 2 c0 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o5 u3_oe ? rs-485/eia-485 output enable signal for uart 3. p1[31]/ usb_ovrcr2 / ssp1_sck/ ad0[5]/ i2c0_scl i/o 0 p1[31] ? general purpose digital input/output pin. i1 usb_ovrcr2 ? over-current status for usb port 2. the usb_ovrcr pin is used to set status in the ohci controller to inform the host firmware that there is an overcurrent condition. it is possible to use instead a gpio pin and observe that pin for overcurrent situations. i/o 2 ssp1_sck ? serial clock for ssp1. i3 ad0[5] ? a/d converter 0, input 5. when configured as an adc input, the digital function of the pin must be disabled (see section 7.4.1 ). i/o 4 i2c0_scl ? i 2 c0 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). p2[0] to p2[31] i/o port 2: port 2 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p2[0]/ pwm1[1]/ u1_txd/ lcd_pwr i/o 0 p2[0] ? general purpose digital input/output pin. o1 pwm1[1] ? pulse width modulator 1, channel 1 output. o2 u1_txd ? transmitter output for uart 1. o7 lcd_pwr ? lcd panel power enable. p2[1]/ pwm1[2]/ u1_rxd/ lcd_le i/o 0 p2[1] ? general purpose digital input/output pin. o1 pwm1[2] ? pulse width modulator 1, channel 2 output. i2 u1_rxd ? receiver input for uart 1. o7 lcd_le ? line end signal. p2[2]/ pwm1[3]/ u1_cts/ t2_mat3/ tracedata[3]/ lcd_dclk i/o 0 p2[2] ? general purpose digital input/output pin. o1 pwm1[3] ? pulse width modulator 1, channel 3 output. i2 u1_cts ? clear to send input for uart 1. o3 t2_mat3 ? match output for timer 2, channel 3. o5 tracedata[3] ? trace data, bit 3. o7 lcd_dclk ? lcd panel clock. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 109 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[3]/ pwm1[4]/ u1_dcd/ t2_mat2/ tracedata[2]/ lcd_fp i/o 0 p2[3] ? general purpose digital input/output pin. o1 pwm1[4] ? pulse width modulator 1, channel 4 output. i2 u1_dcd ? data carrier detect input for uart 1. o3 t2_mat2 ? match output for timer 2, channel 2. o5 tracedata[2] ? trace data, bit 2. o7 lcd_fp ? frame pulse (stn). vertical synchronization pulse (tft). p2[4]/ pwm1[5]/ u1_dsr/ t2_mat1/ tracedata[1]/ lcd_enab_m i/o 0 p2[4] ? general purpose digital input/output pin. o1 pwm1[5] ? pulse width modulator 1, channel 5 output. i2 u1_dsr ? data set ready input for uart 1. o3 t2_mat1 ? match output for timer 2, channel 1. o5 tracedata[1] ? trace data, bit 1. o7 lcd_enab_m ? stn ac bias drive or tft data enable output. p2[5]/ pwm1[6]/ u1_dtr/ t2_mat0/ tracedata[0]/ lcd_lp i/o 0 p2[5] ? general purpose digital input/output pin. o1 pwm1[6] ? pulse width modulator 1, channel 6 output. o2 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o3 t2_mat0 ? match output for timer 2, channel 0. o5 tracedata[0] ? trace data, bit 0. o7 lcd_lp ? line synchronization pulse (stn). horizontal synchronization pulse (tft). p2[6]/ pwm1_cap0/ u1_ri/ t2_cap0/ u2_oe/ traceclk/ lcd_vd[0]/ lcd_vd[4] i/o 0 p2[6] ? general purpose digital input/output pin. i1 pwm1_cap0 ? capture input for pwm1, channel 0. i2 u1_ri ? ring indicator input for uart 1. i3 t2_cap0 ? capture input for timer 2, channel 0. o4 u2_oe ? rs-485/eia-485 output enable signal for uart 2. o5 traceclk ? trace clock. o6 lcd_vd[0] ? lcd data. o7 lcd_vd[4] ? lcd data. p2[7]/ can_rd2/ u1_rts/ spifi_cs / lcd_vd[1]/ lcd_vd[5] i/o 0 p2[7] ? general purpose digital input/output pin. i1 can_rd2 ? can2 receiver input. o2 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o5 spifi_cs ? chip select output for spifi. o6 lcd_vd[1] ? lcd data. o7 lcd_vd[5] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 110 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[8]/ can_td2/ u2_txd/ u1_cts/ enet_mdc/ lcd_vd[2]/ lcd_vd[6] i/o 0 p2[8] ? general purpose digital input/output pin. o1 can_td2 ? can2 transmitter output. o2 u2_txd ? transmitter output for uart 2. i3 u1_cts ? clear to send input for uart 1. o4 enet_mdc ? ethernet miim clock. o6 lcd_vd[2] ? lcd data. o7 lcd_vd[6] ? lcd data. p2[9]/ usb_connect1/ u2_rxd/ u4_rxd/ enet_mdio/ lcd_vd[3]/ lcd_vd[7] i/o 0 p2[9] ? general purpose digital input/output pin. o1 usb_connect1 ? usb1 softconnect contro l. the usb_connect pin indicates when the pull-up resistor must be enabled when running in usb device mode. if it is used in usb device mode, this function can be implemented by using another gpio pin. if the chip is only used in usb host mode, there is no need to use this pin. i2 u2_rxd ? receiver input for uart 2. i3 u4_rxd ? receiver input for uart 4. i/o 4 enet_mdio ? ethernet miim data input and output. i6 lcd_vd[3] ? lcd data. i7 lcd_vd[7] ? lcd data. p2[10]/ eint0/ nmi i/o 0 p2[10] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. note: a low on this pin while reset is low forces the on-chip boot loader to take over control of the part after a reset and go into isp mode. see section 38.3 . i1 eint0 ? external interrupt 0 input. i2 nmi ? non-maskable interrupt input. p2[11]/ eint1/ sd_dat[1]/ i2s_tx_sck/ lcd_clkin i/o 0 p2[11] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint1 ? external interrupt 1 input. i/o 2 sd_dat[1] ? data line 1 for sd card interface. i/o 3 i2s_tx_sck ? transmit clock. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s-bus specification . o7 lcd_clkin ? lcd clock. p2[12]/ eint2/ sd_dat[2]/ i2s_tx_ws/ lcd_vd[4]/ lcd_vd[3]/ lcd_vd[8]/ lcd_vd[18] i/o 0 p2[12] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint2 ? external interrupt 2 input. i/o 2 sd_dat[2] ? data line 2 for sd card interface. i/o 3 i2s_tx_ws ? transmit word select. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s-bus specification . o4 lcd_vd[4] ? lcd data. o5 lcd_vd[3] ? lcd data. o6 lcd_vd[8] ? lcd data. o7 lcd_vd[18] ? lcd data. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 111 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[13]/ eint3/ sd_dat[3]/ i2s_tx_sda/ lcd_vd[5]/ lcd_vd[9]/ lcd_vd[19] i/o 0 p2[13] ? general purpose digital input/output pin. this pin includes a 5 ns input glitch filter. i1 eint3 ? external interrupt 3 input. i/o 2 sd_dat[3] ? data line 3 for sd card interface. i/o 3 i2s_tx_sda ? transmit data. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s-bus specification . o5 lcd_vd[5] ? lcd data. o6 lcd_vd[9] ? lcd data. o7 lcd_vd[19] ? lcd data. p2[14]/ emc_cs2 / i2c1_sda/ t2_cap0 i/o 0 p2[14] ? general purpose digital input/output pin. o1 emc_cs2 ? low active chip select 2 signal. i/o 2 i2c1_sda ? i 2 c1 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i3 t2_cap0 ? capture input for timer 2, channel 0. p2[15]/ emc_cs3 / i2c1_scl/ t2_cap1 i/o 0 p2[15] ? general purpose digital input/output pin. o1 emc_cs3 ? low active chip select 3 signal. i/o 2 i2c1_scl ? i 2 c1 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i3 t2_cap1 ? capture input for timer 2, channel 1. p2[16]/ emc_cas i/o 0 p2[16] ? general purpose digital input/output pin. o1 emc_cas ? low active sdram column address strobe. p2[17]/ emc_ras i/o 0 p2[17] ? general purpose digital input/output pin. o1 emc_ras ? low active sdram row address strobe. p2[18]/ emc_clk0 i/o 0 p2[18] ? general purpose digital input/output pin. o1 emc_clk0 ? sdram clock 0. p2[19]/ emc_clk1 i/o 0 p2[19] ? general purpose digital input/output pin. o1 emc_clk1 ? sdram clock 1. p2[20]/ emc_dycs0 i/o 0 p2[20] ? general purpose digital input/output pin. o1 emc_dycs0 ? sdram chip select 0. p2[21]/ emc_dycs1 i/o 0 p2[21] ? general purpose digital input/output pin. o1 emc_dycs1 ? sdram chip select 1. p2[22]/ emc_dycs2 / ssp0_sck/ t3_cap0 i/o 0 p2[22] ? general purpose digital input/output pin. o1 emc_dycs2 ? sdram chip select 2. i/o 2 ssp0_sck ? serial clock for ssp0. i3 t3_cap0 ? capture input for timer 3, channel 0. p2[23]/ emc_dycs3 / ssp0_ssel/ t3_cap1 i/o 0 p2[23] ? general purpose digital input/output pin. o1 emc_dycs3 ? sdram chip select 3. i/o 2 ssp0_ssel ? slave select for ssp0. i3 t3_cap1 ? capture input for timer 3, channel 1. p2[24]/ emc_cke0 i/o 0 p2[24] ? general purpose digital input/output pin. o1 emc_cke0 ? sdram clock enable 0. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 112 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p2[25]/ emc_cke1 i/o 0 p2[25] ? general purpose digital input/output pin. o1 emc_cke1 ? sdram clock enable 1. p2[26]/ emc_cke2/ ssp0_miso/ t3_mat0 i/o 0 p2[26] ? general purpose digital input/output pin. o1 emc_cke2 ? sdram clock enable 2. i/o 2 ssp0_miso ? master in slave out for ssp0. o3 t3_mat0 ? match output for timer 3, channel 0. p2[27]/ emc_cke3/ ssp0_mosi/ t3_mat1 i/o 0 p2[27] ? general purpose digital input/output pin. o1 emc_cke3 ? sdram clock enable 3. i/o 2 ssp0_mosi ? master out slave in for ssp0. o3 t3_mat1 ? match output for timer 3, channel 1. p2[28]/ emc_dqm0 i/o 0 p2[28] ? general purpose digital input/output pin. o1 emc_dqm0 ? data mask 0 used with sdram and static devices. p2[29]/ emc_dqm1 i/o 0 p2[29] ? general purpose digital input/output pin. o1 emc_dqm1 ? data mask 1 used with sdram and static devices. p2[30]/ emc_dqm2/ i2c2_sda/ t3_mat2 i/o 0 p2[30] ? general purpose digital input/output pin. o1 emc_dqm2 ? data mask 2 used with sdram and static devices. i/o 2 i2c2_sda ? i 2 c2 data input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat2 ? match output for timer 3, channel 2. p2[31]/ emc_dqm3/ i2c2_scl/ t3_mat3 i/o 0 p2[31] ? general purpose digital input/output pin. o1 emc_dqm3 ? data mask 3 used with sdram and static devices. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o3 t3_mat3 ? match output for timer 3, channel 3. p3[0] to p3[31] i/o port 3: port 3 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p3[0]/ emc_d[0] i/o 0 p3[0] ? general purpose digital input/output pin. i/o 1 emc_d[0] ? external memory data line 0. p3[1]/ emc_d[1] i/o 0 p3[1] ? general purpose digital input/output pin. i/o 1 emc_d[1] ? external memory data line 1. p3[2]/ emc_d[2] i/o 0 p3[2] ? general purpose digital input/output pin. i/o 1 emc_d[2] ? external memory data line 2. p3[3]/ emc_d[3] i/o 0 p3[3] ? general purpose digital input/output pin. i/o 1 emc_d[3] ? external memory data line 3. p3[4]/ emc_d[4] i/o 0 p3[4] ? general purpose digital input/output pin. i/o 1 emc_d[4] ? external memory data line 4. p3[5]/ emc_d[5] i/o 0 p3[5] ? general purpose digital input/output pin. i/o 1 emc_d[5] ? external memory data line 5. p3[6]/ emc_d[6] i/o 0 p3[6] ? general purpose digital input/output pin. i/o 1 emc_d[6] ? external memory data line 6. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 113 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[7]/ emc_d[7] i/o 0 p3[7] ? general purpose digital input/output pin. i/o 1 emc_d[7] ? external memory data line 7. p3[8]/ emc_d[8] i/o 0 p3[8] ? general purpose digital input/output pin. i/o 1 emc_d[8] ? external memory data line 8. p3[9]/ emc_d[9] i/o 0 p3[9] ? general purpose digital input/output pin. i/o 1 emc_d[9] ? external memory data line 9. p3[10]/ emc_d[10] i/o 0 p3[10] ? general purpose digital input/output pin. i/o 1 emc_d[10] ? external memory data line 10. p3[11]/ emc_d[11] i/o 0 p3[11] ? general purpose digital input/output pin. i/o 1 emc_d[11] ? external memory data line 11. p3[12]/ emc_d[12] i/o 0 p3[12] ? general purpose digital input/output pin. i/o 1 emc_d[12] ? external memory data line 12. p3[13]/ emc_d[13] i/o 0 p3[13] ? general purpose digital input/output pin. i/o 1 emc_d[13] ? external memory data line 13. p3[14]/ emc_d[14] i/o 0 p3[14] ? general purpose digital input/output pin. i/o 1 emc_d[14] ? external memory data line 14. on por, this pin serves as the boot0 pin (see p3[15] description below. p3[15]/ emc_d[15] i/o 0 p3[15] ? general purpose digital input/output pin. i/o 1 emc_d[15] ? external memory data line 15. boot[1:0] = 00 selects 8-bit external memory on emc_cs1 . boot[1:0] = 01 is reserved. do not use. boot[1:0] = 10 selects 32-bit external memory on emc_cs1 . boot[1:0] = 11 selects 16-bit external memory on emc_cs1 . p3[16]/ emc_d[16]/ pwm0[1]/ u1_txd i/o 0 p3[16] ? general purpose digital input/output pin. i/o 1 emc_d[16] ? external memory data line 16. o2 pwm0[1] ? pulse width modulator 0, output 1. o3 u1_txd ? transmitter output for uart 1. p3[17]/ emc_d[17]/ pwm0[2]/ u1_rxd i/o 0 p3[17] ? general purpose digital input/output pin. i/o 1 emc_d[17] ? external memory data line 17. o2 pwm0[2] ? pulse width modulator 0, output 2. i3 u1_rxd ? receiver input for uart 1. p3[18]/ emc_d[18]/ pwm0[3]/ u1_cts i/o 0 p3[18] ? general purpose digital input/output pin. i/o 1 emc_d[18] ? external memory data line 18. o2 pwm0[3] ? pulse width modulator 0, output 3. i3 u1_cts ? clear to send input for uart 1. p3[19]/ emc_d[19]/ pwm0[4]/ u1_dcd i/o 0 p3[19] ? general purpose digital input/output pin. i/o 1 emc_d[19] ? external memory data line 19. o2 pwm0[4] ? pulse width modulator 0, output 4. i3 u1_dcd ? data carrier detect input for uart 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 114 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[20]/ emc_d[20]/ pwm0[5]/ u1_dsr i/o 0 p3[20] ? general purpose digital input/output pin. i/o 1 emc_d[20] ? external memory data line 20. o2 pwm0[5] ? pulse width modulator 0, output 5. i3 u1_dsr ? data set ready input for uart 1. p3[21]/ emc_d[21]/ pwm0[6]/ u1_dtr i/o 0 p3[21] ? general purpose digital input/output pin. i/o 1 emc_d[21] ? external memory data line 21. o2 pwm0[6] ? pulse width modulator 0, output 6. o3 u1_dtr ? data terminal ready output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. p3[22]/ emc_d[22]/ pwm0_cap0/ u1_ri i/o 0 p3[22] ? general purpose digital input/output pin. i/o 1 emc_d[22] ? external memory data line 22. i2 pwm0_cap0 ? capture input for pwm0, channel 0. i3 u1_ri ? ring indicator input for uart 1. p3[23]/ emc_d[23]/ pwm1_cap0/ t0_cap0 i/o 0 p3[23] ? general purpose digital input/output pin. i/o 1 emc_d[23] ? external memory data line 23. i2 pwm1_cap0 ? capture input for pwm1, channel 0. i3 t0_cap0 ? capture input for timer 0, channel 0. p3[24]/ emc_d[24]/ pwm1[1]/ t0_cap1 i/o 0 p3[24] ? general purpose digital input/output pin. i/o 1 emc_d[24] ? external memory data line 24. o2 pwm1[1] ? pulse width modulator 1, output 1. i3 t0_cap1 ? capture input for timer 0, channel 1. p3[25]/ emc_d[25]/ pwm1[2]/ t0_mat0 i/o 0 p3[25] ? general purpose digital input/output pin. i/o 1 emc_d[25] ? external memory data line 25. o2 pwm1[2] ? pulse width modulator 1, output 2. o3 t0_mat0 ? match output for timer 0, channel 0. p3[26]/ emc_d[26]/ pwm1[3]/ t0_mat1/ stclk i/o 0 p3[26] ? general purpose digital input/output pin. i/o 1 emc_d[26] ? external memory data line 26. o2 pwm1[3] ? pulse width modulator 1, output 3. o3 t0_mat1 ? match output for timer 0, channel 1. i4 stclk ? system tick timer clock input. p3[27]/ emc_d[27]/ pwm1[4]/ t1_cap0 i/o 0 p3[27] ? general purpose digital input/output pin. i/o 1 emc_d[27] ? external memory data line 27. o2 pwm1[4] ? pulse width modulator 1, output 4. i3 t1_cap0 ? capture input for timer 1, channel 0. p3[28]/ emc_d[28]/ pwm1[5]/ t1_cap1 i/o 0 p3[28] ? general purpose digital input/output pin. i/o 1 emc_d[28] ? external memory data line 28. o2 pwm1[5] ? pulse width modulator 1, output 5. i3 t1_cap1 ? capture input for timer 1, channel 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 115 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p3[29]/ emc_d[29]/ pwm1[6]/ t1_mat0 i/o 0 p3[29] ? general purpose digital input/output pin. i/o 1 emc_d[29] ? external memory data line 29. o2 pwm1[6] ? pulse width modulator 1, output 6. o3 t1_mat0 ? match output for timer 1, channel 0. p3[30]/ emc_d[30]/ u1_rts/ t1_mat1 i/o 0 p3[30] ? general purpose digital input/output pin. i/o 1 emc_d[30] ? external memory data line 30. o2 u1_rts ? request to send output for uart 1. can also be configured to be an rs-485/eia-485 output enable signal for uart 1. o3 t1_mat1 ? match output for timer 1, channel 1. p3[31]/ emc_d[31]/ t1_mat2 i/o 0 p3[31] ? general purpose digital input/output pin. i/o 1 emc_d[31] ? external memory data line 31. o3 t1_mat2 ? match output for timer 1, channel 2. p4[0] to p4[31] i/o port 4: port 4 provides up to 32 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p4[0]/ emc_a[0] i/o 0 p4[0] ? ]general purpose digital input/output pin. i/o 1 emc_a[0] ? external memory address line 0. p4[1]/ emc_a[1] i/o 0 p4[1] ? general purpose digital input/output pin. i/o 1 emc_a[1] ? external memory address line 1. p4[2]/ emc_a[2] i/o 0 p4[2] ? general purpose digital input/output pin. i/o 1 emc_a[2] ? external memory address line 2. p4[3]/ emc_a[3] i/o 0 p4[3] ? general purpose digital input/output pin. i/o 1 emc_a[3] ? external memory address line 3. p4[4]/ emc_a[4] i/o 0 p4[4] ? general purpose digital input/output pin. i/o 1 emc_a[4] ? external memory address line 4. p4[5]/ emc_a[5] i/o 0 p4[5] ? general purpose digital input/output pin. i/o 1 emc_a[5] ? external memory address line 5. p4[6]/ emc_a[6] i/o 0 p4[6] ? general purpose digital input/output pin. i/o 1 emc_a[6] ? external memory address line 6. p4[7]/ emc_a[7] i/o 0 p4[7] ? general purpose digital input/output pin. i/o 1 emc_a[7] ? external memory address line 7. p4[8]/ emc_a[8] i/o 0 p4[8] ? general purpose digital input/output pin. i/o 1 emc_a[8] ? external memory address line 8. p4[9]/ emc_a[9] i/o 0 p4[9] ? general purpose digital input/output pin. i/o 1 emc_a[9] ? external memory address line 9. p4[10]/ emc_a[10] i/o 0 p4[10] ? general purpose digital input/output pin. i/o 1 emc_a[10] ? external memory address line 10. p4[11]/ emc_a[11] i/o 0 p4[11] ? general purpose digital input/output pin. i/o 1 emc_a[11] ? external memory address line 11. p4[12]/ emc_a[12] i/o 0 p4[12] ? general purpose digital input/output pin. i/o 1 emc_a[12] ? external memory address line 12. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 116 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p4[13]/ emc_a[13] i/o 0 p4[13] ? general purpose digital input/output pin. i/o 1 emc_a[13] ? external memory address line 13. p4[14]/ emc_a[14] i/o 0 p4[14] ? general purpose digital input/output pin. i/o 1 emc_a[14] ? external memory address line 14. p4[15]/ emc_a[15] i/o 0 p4[15] ? general purpose digital input/output pin. i/o 1 emc_a[15] ? external memory address line 15. p4[16]/ emc_a[16] i/o 0 p4[16] ? general purpose digital input/output pin. i/o 1 emc_a[16] ? external memory address line 16. p4[17]/ emc_a[17] i/o 0 p4[17] ? general purpose digital input/output pin. i/o 1 emc_a[17] ? external memory address line 17. p4[18]/ emc_a[18] i/o 0 p4[18] ? general purpose digital input/output pin. i/o 1 emc_a[18] ? external memory address line 18. p4[19]/ emc_a[19] i/o 0 p4[19] ? general purpose digital input/output pin. i/o 1 emc_a[19] ? external memory address line 19. p4[20]/ emc_a[20]/ i2c2_sda/ ssp1_sck i/o 0 p4[20] ? general purpose digital input/output pin. i/o 1 emc_a[20] ? external memory address line 20. i/o 2 i2c2_sda ? i 2 c2 data input/output ((this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 3 ssp1_sck ? serial clock for ssp1. p4[21]/ emc_a[21]/ i2c2_scl/ ssp1_ssel i/o 0 p4[21] ? general purpose digital input/output pin. i/o 1 emc_a[21] ? external memory address line 21. i/o 2 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). i/o 3 ssp1_ssel ? slave select for ssp1. p4[22]/ emc_a[22]/ u2_txd/ ssp1_miso i/o 0 p4[22] ? general purpose digital input/output pin. i/o 1 emc_a[22] ? external memory address line 22. o2 u2_txd ? transmitter output for uart 2. i/o 3 ssp1_miso ? master in slave out for ssp1. p4[23]/ emc_a[23]/ u2_rxd/ ssp1_mosi i/o 0 p4[23] ? general purpose digital input/output pin. i/o 1 emc_a[23] ? external memory address line 23. i2 u2_rxd ? receiver input for uart 2. i/o 3 ssp1_mosi ? master out slave in for ssp1. p4[24]/ emc_oe i/o 0 p4[24] ? general purpose digital input/output pin. o1 emc_oe ? low active output enable signal. p4[25]/ emc_we i/o 0 p4[25] ? general purpose digital input/output pin. o1 emc_we ? low active write enable signal. p4[26]/ emc_bls0 i/o 0 p4[26] ? general purpose digital input/output pin. o1 emc_bls0 ? low active byte lane select signal 0. p4[27]/ emc_bls1 i/o 0 p4[27] ? general purpose digital input/output pin. o1 emc_bls1 ? low active byte lane select signal 1. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 117 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration p4[28]/ emc_bls2 / u3_txd/ t2_mat0/ lcd_vd[6]/ lcd_vd[10]/ lcd_vd[2] i/o 0 p4 [28] ? general purpose digital input/output pin. o1 emc_bls2 ? low active byte lane select signal 2. o2 txd3 ? transmitter output for uart 3. o3 t2_mat0 ? match output for timer 2, channel 0. o5 lcd_vd[6] ? lcd data. o6 lcd_vd[10] ? lcd data. o7 lcd_vd[2] ? lcd data. p4[29]/ emc_bls3 / u3_rxd/ t2_mat1/ i2c2_scl/ lcd_vd[7]/ lcd_vd[11]/ lcd_vd[3] i/o 0 p4[29] ? general purpose digital input/output pin. o1 emc_bls3 ? low active byte lane select signal 3. i2 u3_rxd ? receiver input for uart 3. o3 t2_mat1 ? match output for timer 2, channel 1. i/o 4 i2c2_scl ? i 2 c2 clock input/output (this pin does not use a specialized i 2 c pad, see section 22.1 for details). o5 lcd_vd[7] ? lcd data. o6 lcd_vd[11] ? lcd data. o7 lcd_vd[3] ? lcd data. p4[30]/ emc_cs0 / cmp0_out i/o 0 p4[30] ? general purpose digital input/output pin. o1 emc_cs0 ? low active chip select 0 signal. o5 cmp0_out ? comparator 0 output. p4[31]/ emc_cs1 i/o 0 p4[31] ? general purpose digital input/output pin. o1 emc_cs1 ? low active chip select 1 signal. p5[0] to p5[4] i/o port 5: port 5 provides up to 5 i/o pins, depending on the package. each pin has individual direction control, pin mode configuration, and function selection. p5[0]/ emc_a[24]/ t2_mat2 i/o 0 p5[0] ? general purpose digital input/output pin. i/o 1 emc_a[24] ? external memory address line 24. o3 t2_mat2 ? match output for timer 2, channel 2. p5[1]/ emc_a[25]/ t2_mat3 i/o 0 p5[1] ? general purpose digital input/output pin. i/o 1 emc_a[25] ? external memory address line 25. o3 t2_mat3 ? match output for timer 2, channel 3. p5[2]/ t3_mat2/ i2c0_sda i/o 0 p5[2] ? general purpose digital input/output pin. o3 t3_mat2 ? match output for timer 3, channel 2. i/o 5 i2c0_sda ? i 2 c0 data input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus). p5[3]/ u4_rxd/ i2c0_scl i/o 0 p5[3] ? general purpose digital input/output pin. i4 u4_rxd ? receiver input for uart 4. i/o 5 i2c0_scl0 ? i 2 c0 clock input/output (this pin uses a specialized i 2 c pad that supports i 2 c fast mode plus. p5[4]/ u0_oe/ t3_mat3/ u4_txd i/o 0 p5[4] ? general purpose digital input/output pin. o1 u0_oe ? rs-485/eia-485 output enable signal for uart 0. o3 t3_mat3 ? match output for timer 3, channel 3. o4 u4_txd ? transmitter output for uart 4 (input/output in smart card mode). table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 118 of 942 nxp semiconductors UM10562 chapter 6: lpc408x/407x pin configuration [1] these values are used in the func field of the iocon registers, described in section 7.4.1 . [2] these pins provide s pecial analog functionality. rtc_alarm o rtc_alarm ? rtc controlled output. this pin has a low drive strength and is powered by v bat (see data sheet for details). it is driven high when an rtc alarm is generated. usb_d ? 2i / o usb_d ? 2 ? usb port 2 bidirectional d ? line. jtag_tdo (swo) o jtag_tdo ? test data out for jtag interface. swo ? serial wire trace output. jtag_tdi i tdi ? test data in for jtag interface. this pin includes an internal pull-up, see section 39.1 . jtag_tms (swdio) i tms ? test mode select for jtag interface. this pin includes an internal pull-up, see section 39.1 . swdio ? serial wire debug data input/output. jtag_ trst i trst ? test reset for jtag interface. this pin includes an internal pull-up, see section 39.1 . jtag_tck (swdclk) i tck ? test clock for jtag interface. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. swdclk ? serial wire clock. rstout o reset status output. a low output on this pin indicates that the device is in the reset state, for any reason . this reflects the reset input pin and all internal reset sources. reset i external reset input. a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin includes a 20 ns input glitch filter. xtal1 [2] i input to the oscillator circuit and internal clock generator circuits. xtal2 [2] o output from the oscillator amplifier. rtcx1 [2] i input to the rtc 32 khz ultra-low power oscillator circuit. rtcx2 [2] o output from the rtc 32 khz ultra-low power oscillator circuit. v ss [2] i ground: 0 v reference for digital io pins. v ssreg [2] i ground: 0 v reference for internal logic. v ssa [2] i analog ground: 0 v power supply and reference for the adc and dac. this should be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(3v3) [2] i 3.3 v supply voltage: this is the power supply voltage for i/o other than pins in the vbat domain. v dd(reg)(3v3) [2] i 3.3 v regulator supply voltage: this is the power supply for the on-chip voltage regulator that supplies internal logic. v dda [2] i analog 3.3 v pad supply voltage: this can be connected to the same supply as v dd(3v3) but should be isolated to minimize noise and error. this voltage is used to power the adc and dac. note: this pin should be ti ed to 3.3v if the adc and dac are not used. vrefp [2] i adc positive reference voltage: this should be the same voltage as v dda , but should be isolated to minimize noise and error. the voltage level on this pin is used as a reference for adc and dac. note: this pin should be tied to 3.3v if the adc and dac are not used. vbat [2] i rtc power supply: 3.3 v on this pin supplies power to the rtc. table 74. pin description ?continued symbol type iocon select [1] description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 119 of 942 7.1 introduction a separate register is provided to configure each gpio pin. this configuration includes which internal function is connected to the pi n, the output mode (plain, pull-up, pull-down, or repeater), open drain mode control, hysteres is enable, slew rate control, and buffer setup for analog functions. some pins include additional special controls, such as for i 2 c buffer modes. these registers are summarized in table 75 . [1] which pins are available depends on the part number and package combination. 7.2 description the pin connect block allows most pins of the microcontroller to have more than one potential function. configuration registers co ntrol the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropr iate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. selection of a single function on a port pin excludes other peripheral functions available on the same pin. however, the gpio input stays connected and may be read by software or used to contribute to the gpio interrupt feature. 7.3 iocon registers the iocon registers control the functions of device pins. each gpio pin has a dedicated control register to select its function and characteristics. each pin has a unique set of functional capabilities. not all pin characterist ics are selectable on all pins. for instance, pins that have an i 2 c function can be configured for different i 2 c-bus modes, while pins that have an analog alternate function have an analog mode can be selected.details of the iocon registers are in section 7.4.1 . the following sections describe specific characteristics of pins. UM10562 chapter 7: lpc408x/40 7x i/o configuration rev. 1 ? 13 september 2012 user manual table 75. summary of i/o pin configuration registers port registers detail table port 0 pins iocon_p0_nn, where nn is the port pin number, from 0 to 31 [1] table 76 port 1 pins iocon_p1_nn, where nn is the port pin number, from 0 to 31 [1] table 77 port 2 pins iocon_p2_nn, where nn is the port pin number, from 0 to 31 [1] table 78 port 3 pins iocon_p3_nn, where nn is the port pin number, from 0 to 31 [1] table 79 port 4 pins iocon_p4_nn, where nn is the port pin number, from 0 to 31 [1] table 80 port 5 pins iocon_p5_nn, where nn is the port pin number, from 0 to 4 [1] table 81
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 120 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration multiple connections since a particular peripheral function may be allowed on more than one pin, it is possible to configure more than one pin to perform the same function. if a peripheral output function is configured to appear on more than one pin, it will in fact be routed to those pins. if a peripheral input function is defined as coming from more than one source, the values will be logically combined, possib ly resulting in incorrec t peripheral operation. therefore care should be taken to avoid this situation. 7.3.1 pin function the func bits in the iocon registers can be set to gpio (typically value 000) or to a special function. for pins set to gpio, the fi ondir registers determi ne whether the pin is configured as an input or output (see section 8.5.1.1 ). for any special function, the pin direction is controlled automatically depending on the function. the fiondir registers have no effect for special functions. fig 14. i/o configurations 100818 pin configured as digital output px[y] esd esd v dd data output output enable open-drain enable strong pull-up strong pull-down weak pull-up weak pull-down pull-down enable pull-up enable repeater mode enable 10 ns glitch filter enable input invert pin configured as digital input enable glitch filter digital input pin configured as analog input analog input v dd v dd enable analog input
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 121 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.3.2 pin mode the mode bits in the iocon register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode. the possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. the default value is pull-up enabled. the repeater mode enables the pull-up resistor if the pin is high and enables the pull-down resistor if the pin is low. this causes the pin to re tain its last know n state if it is configured as an input and is not driven externally. such state retention is not applicable to the deep power-down mode. repeater mode may typically be used to prevent a pin from floating (and potentially using significant power if it floats to an indeterm inate state) if it is temporarily not driven. 7.3.3 hysteresis the input buffer for digital functions can be configured with or without hysteresis. see the appropriate specific device data sheet for quantitative details. 7.3.4 input inversion this option is included to save users from having to include an external inverter on an input that is only available in the opposite pola rity from an external source. do not set this option on a gpio output. doing so can result in inadvertent toggling of an output with input inversion selected, as a result of operations on other pins in the same port. for example, if software reads a gpio port register, modifies other bits/outputs in the value, and writes the result back to the port regi ster, any output in the port that has input inversion selected will change state. 7.3.5 analog/digital mode in analog mode, the analog input connection is enabled. in digital mode, the analog input connection is disabled. this protects the a nalog input from voltages outside the range of the analog power supply and reference that may sometimes be present on digital pins, since they are typically 5v tolerant. if analog mode is selected, the mode field should be ?inactive? (00); the hys, inv, filtr, slew, and od settings have no effect. for an unconnected pin that has an analog function, keep the admode bit set to 1 (digital mode), and pull-up or pull-down mode selected in the mode field. 7.3.6 input filter type a and w pins include a filter that can be selectively enabled. the filter suppresses input pulses smaller than about 10 ns. 7.3.7 output slew rate the slew bits of digital outputs that do not need to switch state very quickly should be set to ?standard?. this settin g allows multiple outputs to switch simultaneously without noticeably degrading the power/ground distribu tion of the device, and has only a small effect on signal transition time . this is particularly import ant if analog accuracy is significant to the application. see the relevant specific device data sheet for more details.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 122 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.3.8 i 2 c modes pins that support i 2 c with specialized pad electronics (p 0[27], p0[28], p5[2], and p5[3]) have additional configuration bits. these are not hardwired so that the pins can be more easily used for non-i 2 c functions. the hs bit applies to standard, fast-mode, and fast-mode plus i 2 c, and is available for all the pins noted above. the hidrive bit applies only to pins p5[2] and p5[3], and is used to select between standard mode and fast-mode i 2 c or fast-mode plus i 2 c. ? for any i 2 c mode, clear the hs bit so that the input glitch filter is enabled. clear the hidrive bit if it exists for that pin to se lect the correct drive strength for standard mode or fast-mode i 2 c ? for fast-mode plus i 2 c operation, set the hidrive bit to select the correct drive strength for fast-mode plus i 2 c. ? for non-i 2 c operation, these pins remain open-drain and can only drive low, regardless of how hs and hidrive are set. they would typically be used with an external pull-up resistor if they are used as outputs unless they are used only to sink current. leave hs = 1 and hidrive = 0 (if ap plicable) to maximize compatibility with other gpio pins. 7.3.9 open-drain mode when output is selected, either by selecting a special function in the func field, or by selecting the gpio function for a pin having a 1 in its fiondir register, a 1 in the od bit selects open-drain operation, that is, a 1 disables the high-drive transistor. this option has no effect on the primary i 2 c pins. note that the properties of a pin in this simulated open-drain mode are somewhat different t han those of a true open drain output. 7.3.10 dac enable the pin that includes the dac output as a potential function includes an enable for the function that must be set if the dac output is used.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 123 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4 register description the pin connect block contains an i/o control register (iocon) for each pin that has programmable attributes, and selects peripheral functions associated with that pin. these registers are shown by gpio port number in tables 7?76 through 7?81 . [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. [2] iocon types are d (standard digital pin), and other pins with a speciali zed function: a (analog), u (usb), i (i2c), and w. table 76. i/o control registers for port 0 port pin register access reset value [1] address iocon type [2] 208-pin 180-pin 144-pin 80-pin p0[0] iocon_p0_00 r/w 0x030 0x4002 c000 d (tables 82 , 83 )xxxx p0[1] iocon_p0_01 r/w 0x030 0x4002 c004 d (tables 82 , 83 )xxxx p0[2] iocon_p0_02 r/w 0x030 0x4002 c008 d (tables 82 , 83 )xxxx p0[3] iocon_p0_03 r/w 0x030 0x4002 c00c d (tables 82 , 83 )xxxx p0[4] iocon_p0_04 r/w 0x030 0x4002 c010 d (tables 82 , 83 )x x x - p0[5] iocon_p0_05 r/w 0x030 0x4002 c014 d (tables 82 , 83 )x x x - p0[6] iocon_p0_06 r/w 0x030 0x4002 c018 d (tables 82 , 83 )xxxx p0[7] iocon_p0_07 r/w 0x0a0 0x4002 c01c w (tables 90 , 91 )xxxx p0[8] iocon_p0_08 r/w 0x0a0 0x4002 c020 w (tables 90 , 91 )xxxx p0[9] iocon_p0_09 r/w 0x0a0 0x4002 c024 w (tables 90 , 91 )xxxx p0[10] iocon_p0_10 r/w 0x030 0x4002 c028 d (tables 82 , 83 )xxxx p0[11] iocon_p0_11 r/w 0x030 0x4002 c02c d (tables 82 , 83 )xxxx p0[12] iocon_p0_12 r/w 0x1b0 0x4002 c030 a (tables 84 , 85 )x x x - p0[13] iocon_p0_13 r/w 0x1b0 0x4002 c034 a (tables 84 , 85 )x x x - p0[14] iocon_p0_14 r/w 0x030 0x4002 c038 d (tables 82 , 83 )x x x - p0[15] iocon_p0_15 r/w 0x030 0x4002 c03c d (tables 82 , 83 )xxxx p0[16] iocon_p0_16 r/w 0x030 0x4002 c040 d (tables 82 , 83 )xxxx p0[17] iocon_p0_17 r/w 0x030 0x4002 c044 d (tables 82 , 83 )xxxx p0[18] iocon_p0_18 r/w 0x030 0x4002 c048 d (tables 82 , 83 )xxxx p0[19] iocon_p0_19 r/w 0x030 0x4002 c04c d (tables 82 , 83 )x x x - p0[20] iocon_p0_20 r/w 0x030 0x4002 c050 d (tables 82 , 83 )x x x - p0[21] iocon_p0_21 r/w 0x030 0x4002 c054 d (tables 82 , 83 )x x x - p0[22] iocon_p0_22 r/w 0x030 0x4002 c058 d (tables 82 , 83 )xxxx p0[23] iocon_p0_23 r/w 0x1b0 0x4002 c05c a (tables 84 , 85 )x x x - p0[24] iocon_p0_24 r/w 0x1b0 0x4002 c060 a (tables 84 , 85 )x x x - p0[25] iocon_p0_25 r/w 0x1b0 0x4002 c064 a (tables 84 , 85 )xxxx p0[26] iocon_p0_26 r/w 0x1b0 0x4002 c068 a (tables 84 , 85 )xxxx p0[27] iocon_p0_27 r/w 0 0x4002 c06c i (tables 88 , 89 )x x x - p0[28] iocon_p0_28 r/w 0 0x4002 c070 i (tables 88 , 89 )x x x - p0[29] iocon_p0_29 r/w 0 0x4002 c074 u (tables 86 , 87 )xxxx p0[30] iocon_p0_30 r/w 0 0x4002 c078 u (tables 86 , 87 )xxxx p0[31] iocon_p0_31 r/w 0 0x4002 c07c u (tables 86 , 87 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 124 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 77. i/o control registers for port 1 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p1[0] iocon_p1_00 r/w 0x030 0x4002 c080 d (tables 82 , 83 )xxxx p1[1] iocon_p1_01 r/w 0x030 0x4002 c084 d (tables 82 , 83 )xxxx p1[2] iocon_p1_02 r/w 0x030 0x4002 c088 d (tables 82 , 83 )x x - - p1[3] iocon_p1_03 r/w 0x030 0x4002 c08c d (tables 82 , 83 )x x - - p1[4] iocon_p1_04 r/w 0x030 0x4002 c090 d (tables 82 , 83 )xxxx p1[5] iocon_p1_05 r/w 0x030 0x4002 c094 w (tables 90 , 91 )x x - - p1[6] iocon_p1_06 r/w 0x030 0x4002 c098 w (tables 90 , 91 )x x - - p1[7] iocon_p1_07 r/w 0x030 0x4002 c09c w (tables 90 , 91 )x x - - p1[8] iocon_p1_08 r/w 0x030 0x4002 c0a0 d (tables 82 , 83 )xxxx p1[9] iocon_p1_09 r/w 0x030 0x4002 c0a4 d (tables 82 , 83 )xxxx p1[10] iocon_p1_10 r/w 0x030 0x4002 c0a8 d (tables 82 , 83 )xxxx p1[11] iocon_p1_11 r/w 0x030 0x4002 c0ac d (tables 82 , 83 )x x - - p1[12] iocon_p1_12 r/w 0x030 0x4002 c0b0 d (tables 82 , 83 )x x - - p1[13] iocon_p1_13 r/w 0x030 0x4002 c0b4 d (tables 82 , 83 )x x - - p1[14] iocon_p1_14 r/w 0x030 0x4002 c0b8 w (tables 90 , 91 )xxxx p1[15] iocon_p1_15 r/w 0x030 0x4002 c0bc d (tables 82 , 83 )xxxx p1[16] iocon_p1_16 r/w 0x030 0x4002 c0c0 w (tables 90 , 91 )x x x - p1[17] iocon_p1_17 r/w 0x030 0x4002 c0c4 w (tables 90 , 91 )x x x - p1[18] iocon_p1_18 r/w 0x030 0x4002 c0c8 d (tables 82 , 83 )xxxx p1[19] iocon_p1_19 r/w 0x030 0x4002 c0cc d (tables 82 , 83 )xxxx p1[20] iocon_p1_20 r/w 0x030 0x4002 c0d0 d (tables 82 , 83 )xxxx p1[21] iocon_p1_21 r/w 0x030 0x4002 c0d4 d (tables 82 , 83 )x x x - p1[22] iocon_p1_22 r/w 0x030 0x4002 c0d8 d (tables 82 , 83 )xxxx p1[23] iocon_p1_23 r/w 0x030 0x4002 c0dc d (tables 82 , 83 )xxxx p1[24] iocon_p1_24 r/w 0x030 0x4002 c0e0 d (tables 82 , 83 )xxxx p1[25] iocon_p1_25 r/w 0x030 0x4002 c0e4 d (tables 82 , 83 )xxxx p1[26] iocon_p1_26 r/w 0x030 0x4002 c0e8 d (tables 82 , 83 )xxxx p1[27] iocon_p1_27 r/w 0x030 0x4002 c0ec d (tables 82 , 83 )x x x - p1[28] iocon_p1_28 r/w 0x030 0x4002 c0f0 d (tables 82 , 83 )xxxx p1[29] iocon_p1_29 r/w 0x030 0x4002 c0f4 d (tables 82 , 83 )xxxx p1[30] iocon_p1_30 r/w 0x1b0 0x4002 c0f8 a (tables 84 , 85 )xxxx p1[31] iocon_p1_31 r/w 0x1b0 0x4002 c0fc a (tables 84 , 85 )xxxx
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 125 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 78. i/o control registers for port 2 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p2[0] iocon_p2_00 r/w 0x030 0x4002 c100 d (tables 82 , 83 )xxxx p2[1] iocon_p2_01 r/w 0x030 0x4002 c104 d (tables 82 , 83 )xxxx p2[2] iocon_p2_02 r/w 0x030 0x4002 c108 d (tables 82 , 83 )xxxx p2[3] iocon_p2_03 r/w 0x030 0x4002 c10c d (tables 82 , 83 )xxxx p2[4] iocon_p2_04 r/w 0x030 0x4002 c110 d (tables 82 , 83 )xxxx p2[5] iocon_p2_05 r/w 0x030 0x4002 c114 d (tables 82 , 83 )xxxx p2[6] iocon_p2_06 r/w 0x030 0x4002 c118 d (tables 82 , 83 )xxxx p2[7] iocon_p2_07 r/w 0x030 0x4002 c11c d (tables 82 , 83 )xxxx p2[8] iocon_p2_08 r/w 0x030 0x4002 c120 d (tables 82 , 83 )xxxx p2[9] iocon_p2_09 r/w 0x030 0x4002 c124 d (tables 82 , 83 )xxxx p2[10] iocon_p2_10 r/w 0x030 0x4002 c128 d (tables 82 , 83 )xxxx p2[11] iocon_p2_11 r/w 0x030 0x4002 c12c d (tables 82 , 83 )x x x - p2[12] iocon_p2_12 r/w 0x030 0x4002 c130 d (tables 82 , 83 )x x x - p2[13] iocon_p2_13 r/w 0x030 0x4002 c134 d (tables 82 , 83 )x x x - p2[14] iocon_p2_14 r/w 0x030 0x4002 c138 d (tables 82 , 83 )x - - - p2[15] iocon_p2_15 r/w 0x030 0x4002 c13c d (tables 82 , 83 )x - - - p2[16] iocon_p2_16 r/w 0x030 0x4002 c140 d (tables 82 , 83 )x x - - p2[17] iocon_p2_17 r/w 0x030 0x4002 c144 d (tables 82 , 83 )x x - - p2[18] iocon_p2_18 r/w 0x030 0x4002 c148 d (tables 82 , 83 )x x - - p2[19] iocon_p2_19 r/w 0x030 0x4002 c14c d (tables 82 , 83 )x x - - p2[20] iocon_p2_20 r/w 0x030 0x4002 c150 d (tables 82 , 83 )x x - - p2[21] iocon_p2_21 r/w 0x030 0x4002 c154 d (tables 82 , 83 )x x - - p2[22] iocon_p2_22 r/w 0x030 0x4002 c158 d (tables 82 , 83 )x - - - p2[23] iocon_p2_23 r/w 0x030 0x4002 c15c d (tables 82 , 83 )x - - - p2[24] iocon_p2_24 r/w 0x030 0x4002 c160 d (tables 82 , 83 )x x - - p2[25] iocon_p2_25 r/w 0x030 0x4002 c164 d (tables 82 , 83 )x x - - p2[26] iocon_p2_26 r/w 0x030 0x4002 c168 d (tables 82 , 83 )x - - - p2[27] iocon_p2_27 r/w 0x030 0x4002 c16c d (tables 82 , 83 )x - - - p2[28] iocon_p2_28 r/w 0x030 0x4002 c170 d (tables 82 , 83 )x x - - p2[29] iocon_p2_29 r/w 0x030 0x4002 c174 d (tables 82 , 83 )x x - - p2[30] iocon_p2_30 r/w 0x030 0x4002 c178 d (tables 82 , 83 )x - - - p2[31] iocon_p2_31 r/w 0x030 0x4002 c17c d (tables 82 , 83 )x - - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 126 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 79. i/o control registers for port 3 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p3[0] iocon_p3_00 r/w 0x030 0x4002 c180 d (tables 82 , 83 )x x x - p3[1] iocon_p3_01 r/w 0x030 0x4002 c184 d (tables 82 , 83 )x x x - p3[2] iocon_p3_02 r/w 0x030 0x4002 c188 d (tables 82 , 83 )x x x - p3[3] iocon_p3_03 r/w 0x030 0x4002 c18c d (tables 82 , 83 )x x x - p3[4] iocon_p3_04 r/w 0x030 0x4002 c190 d (tables 82 , 83 )x x x - p3[5] iocon_p3_05 r/w 0x030 0x4002 c194 d (tables 82 , 83 )x x x - p3[6] iocon_p3_06 r/w 0x030 0x4002 c198 d (tables 82 , 83 )x x x - p3[7] iocon_p3_07 r/w 0x030 0x4002 c19c d (tables 82 , 83 )x x x - p3[8] iocon_p3_08 r/w 0x030 0x4002 c1a0 d (tables 82 , 83 )x x - - p3[9] iocon_p3_09 r/w 0x030 0x4002 c1a4 d (tables 82 , 83 )x x - - p3[10] iocon_p3_10 r/w 0x030 0x4002 c1a8 d (tables 82 , 83 )x x - - p3[11] iocon_p3_11 r/w 0x030 0x4002 c1ac d (tables 82 , 83 )x x - - p3[12] iocon_p3_12 r/w 0x030 0x4002 c1b0 d (tables 82 , 83 )x x - - p3[13] iocon_p3_13 r/w 0x030 0x4002 c1b4 d (tables 82 , 83 )x x - - p3[14] iocon_p3_14 r/w 0x030 0x4002 c1b8 d (tables 82 , 83 )x x - - p3[15] iocon_p3_15 r/w 0x030 0x4002 c1bc d (tables 82 , 83 )x x - - p3[16] iocon_p3_16 r/w 0x030 0x4002 c1c0 d (tables 82 , 83 )x - - - p3[17] iocon_p3_17 r/w 0x030 0x4002 c1c4 d (tables 82 , 83 )x - - - p3[18] iocon_p3_18 r/w 0x030 0x4002 c1c8 d (tables 82 , 83 )x - - - p3[19] iocon_p3_19 r/w 0x030 0x4002 c1cc d (tables 82 , 83 )x - - - p3[20] iocon_p3_20 r/w 0x030 0x4002 c1d0 d (tables 82 , 83 )x - - - p3[21] iocon_p3_21 r/w 0x030 0x4002 c1d4 d (tables 82 , 83 )x - - - p3[22] iocon_p3_22 r/w 0x030 0x4002 c1d8 d (tables 82 , 83 )x - - - p3[23] iocon_p3_23 r/w 0x030 0x4002 c1dc d (tables 82 , 83 )x x x - p3[24] iocon_p3_24 r/w 0x030 0x4002 c1e0 d (tables 82 , 83 )x x x - p3[25] iocon_p3_25 r/w 0x030 0x4002 c1e4 d (tables 82 , 83 )x x x - p3[26] iocon_p3_26 r/w 0x030 0x4002 c1e8 d (tables 82 , 83 )x x x - p3[27] iocon_p3_27 r/w 0x030 0x4002 c1ec d (tables 82 , 83 )x - - - p3[28] iocon_p3_28 r/w 0x030 0x4002 c1f0 d (tables 82 , 83 )x - - - p3[29] iocon_p3_29 r/w 0x030 0x4002 c1f4 d (tables 82 , 83 )x - - - p3[30] iocon_p3_30 r/w 0x030 0x4002 c1f8 d (tables 82 , 83 )x - - - p3[31] iocon_p3_31 r/w 0x030 0x4002 c1fc d (tables 82 , 83 )x - - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 127 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 80. i/o control registers for port 4 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p4[0] iocon_p4_00 r/w 0x030 0x4002 c200 d (tables 82 , 83 )x x x - p4[1] iocon_p4_01 r/w 0x030 0x4002 c204 d (tables 82 , 83 )x x x - p4[2] iocon_p4_02 r/w 0x030 0x4002 c208 d (tables 82 , 83 )x x x - p4[3] iocon_p4_03 r/w 0x030 0x4002 c20c d (tables 82 , 83 )x x x - p4[4] iocon_p4_04 r/w 0x030 0x4002 c210 d (tables 82 , 83 )x x x - p4[5] iocon_p4_05 r/w 0x030 0x4002 c214 d (tables 82 , 83 )x x x - p4[6] iocon_p4_06 r/w 0x030 0x4002 c218 d (tables 82 , 83 )x x x - p4[7] iocon_p4_07 r/w 0x030 0x4002 c21c d (tables 82 , 83 )x x x - p4[8] iocon_p4_08 r/w 0x030 0x4002 c220 d (tables 82 , 83 )x x x - p4[9] iocon_p4_09 r/w 0x030 0x4002 c224 d (tables 82 , 83 )x x x - p4[10] iocon_p4_10 r/w 0x030 0x4002 c228 d (tables 82 , 83 )x x x - p4[11] iocon_p4_11 r/w 0x030 0x4002 c22c d (tables 82 , 83 )x x x - p4[12] iocon_p4_12 r/w 0x030 0x4002 c230 d (tables 82 , 83 )x x x - p4[13] iocon_p4_13 r/w 0x030 0x4002 c234 d (tables 82 , 83 )x x x - p4[14] iocon_p4_14 r/w 0x030 0x4002 c238 d (tables 82 , 83 )x x x - p4[15] iocon_p4_15 r/w 0x030 0x4002 c23c d (tables 82 , 83 )x x x - p4[16] iocon_p4_16 r/w 0x030 0x4002 c240 d (tables 82 , 83 )x x - - p4[17] iocon_p4_17 r/w 0x030 0x4002 c244 d (tables 82 , 83 )x x - - p4[18] iocon_p4_18 r/w 0x030 0x4002 c248 d (tables 82 , 83 )x x - - p4[19] iocon_p4_19 r/w 0x030 0x4002 c24c d (tables 82 , 83 )x x - - p4[20] iocon_p4_20 r/w 0x030 0x4002 c250 d (tables 82 , 83 )x - - - p4[21] iocon_p4_21 r/w 0x030 0x4002 c254 d (tables 82 , 83 )x - - - p4[22] iocon_p4_22 r/w 0x030 0x4002 c258 d (tables 82 , 83 )x - - - p4[23] iocon_p4_23 r/w 0x030 0x4002 c25c d (tables 82 , 83 )x - - - p4[24] iocon_p4_24 r/w 0x030 0x4002 c260 d (tables 82 , 83 )x x x - p4[25] iocon_p4_25 r/w 0x030 0x4002 c264 d (tables 82 , 83 )x x x - p4[26] iocon_p4_26 r/w 0x030 0x4002 c268 d (tables 82 , 83 )x x - - p4[27] iocon_p4_27 r/w 0x030 0x4002 c26c d (tables 82 , 83 )x x - - p4[28] iocon_p4_28 r/w 0x030 0x4002 c270 d (tables 82 , 83 )xxxx p4[29] iocon_p4_29 r/w 0x030 0x4002 c274 d (tables 82 , 83 )xxxx p4[30] iocon_p4_30 r/w 0x030 0x4002 c278 d (tables 82 , 83 )x x x - p4[31] iocon_p4_31 r/w 0x030 0x4002 c27c d (tables 82 , 83 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 128 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 81. i/o control registers for port 5 port pin register access reset value [1] address iocon type 208-pin 180-pin 144-pin 80-pin p5[0] iocon_p5_00 r/w 0x030 0x4002 c280 d (tables 82 , 83 )x x x - p5[1] iocon_p5_01 r/w 0x030 0x4002 c284 d (tables 82 , 83 )x x x - p5[2] iocon_p5_02 r/w 0 0x4002 c288 i (tables 88 , 89 )x x x - p5[3] iocon_p5_03 r/w 0 0x4002 c28c i (tables 88 , 89 )x x x - p5[4] iocon_p5_04 r/w 0x030 0x4002 c290 d (tables 82 , 83 )x x x -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 129 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1 i/o configuration regi ster contents (iocon) the functions of bits in the iocon register for each gpio port pin is described in the following sections. there are some differences in iocon for special port pins compared to most other port pins. these include pins that support analog fu nctions (such as adc inputs and the dac output), the usb d+/d- pins, and specialized i 2 c pins: ? ? type d iocon registers (applies to most gpio port pins) ? ? ? type a iocon registers (applies to pins that include an analog function) ? ? ? type u iocon registers (applies to pins that include a usb d+ or d- function) ? ? ? type i iocon registers (applies to pins that include a specialized i 2 c function) ? ? ? type w iocon registers (these pins are otherwise the same as type d, but include a selectable input glitch filter, and default to pull-down/pull-up disabled). ?
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 130 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.1 type d iocon registers (applies to most gpio port pins) this iocon table applies to all port pins except p0[7 to 9], p0[12 to 13], p0[23 to 31], p1[30 to 31], and p5[2 to 3]. those pins include dac, adc, usb, i 2 c, or input glitch filter functions that alter the contents of the related iocon registers. table 82. type d iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see ta b l e 8 3 for specific values. 000 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 10 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 hys hysteresis. see section 7.3.3 ? hysteresis ? .1 0disable. 1 enable. 6 inv input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 8:7 - reserved. read value is undefined, only zero should be written. na 9 slew driver slew rate. see section 7.3.7 ? output slew rate ? .0 0 standard mode, output slew rate control is enabled. more outputs can be switched simultaneously. 1 fast mode, slew rate control is disabled. re fer to the appropriate specific device data sheet for details. 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 131 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_0 p0[0] can_rd1 u3_txd i2c1_sda u0_txd iocon_p0_1 p0[1] can_td1 u3_rxd i2c1_scl u0_rxd iocon_p0_2 p0[2] u0_txd u3_txd iocon_p0_3 p0[3] u0_rxd u3_rxd iocon_p0_4 p0[4] i2s_rx_sck can_rd2 t2_cap0 cmp_rosc lcd_vd[0] iocon_p0_5 p0[5] i2s_rx_ws can_td2 t2_cap1 cmp_reset lcd_vd[1] iocon_p0_6 p0[6] i2s_rx_sda ssp1_ssel t2_mat0 u1_rts cmp_rosc lcd_vd[8] iocon_p0_10 p0[10] u2_txd i2c2_sda t3_mat0 lcd_vd[5] iocon_p0_11 p0[11] u2_rxd i2c2_scl t3_mat1 lcd_vd[10] iocon_p0_14 p0[14] usb_hsten2 ssp1_ssel usb_connect2 iocon_p0_15 p0[15] u1_txd ssp0_sck spifi_io[2] iocon_p0_16 p0[16] u1_rxd ssp0_ssel spifi_io[3] iocon_p0_17 p0[17] u1_cts ssp0_miso spifi_io[1] iocon_p0_18 p0[18] u1_dcd ssp0_mosi spifi_io[0] iocon_p0_19 p0[19] u1_dsr sd_clk i2c1_sda lcd_vd[13] iocon_p0_20 p0[20] u1_dtr sd_cmd i2c1_scl lcd_vd[14] iocon_p0_21 p0[21] u1_ri sd_pwr u4_oe can_rd1 u4_clk iocon_p0_22 p0[22] u1_rts sd_dat[0] u4_txd can_td1 spifi_clk iocon_p1_0 p1[0] enet_txd0 t3_cap1 ssp2_sck iocon_p1_1 p1[1] enet_txd1 t3_mat3 ssp2_mosi iocon_p1_2 p1[2] enet_txd2 sd_clk pwm0[1] iocon_p1_3 p1[3] enet_ txd3 sd_cmd pwm0[2] iocon_p1_4 p1[4] enet_tx_en t3_mat2 ssp2_miso iocon_p1_8 p1[8] enet_crs t3_mat1 ssp2_ssel iocon_p1_9 p1[9] enet_rxd0 t3_mat0 iocon_p1_10 p1[10] enet_rxd1 t3_cap0 iocon_p1_11 p1[11] enet_rxd2 sd_dat[2] pwm0[6] iocon_p1_12 p1[12] enet_rxd3 sd_dat[3] pwm0_cap0 cmp1_out iocon_p1_13 p1[13] enet_rx_dv
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 132 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p1_15 p1[15] enet_rx_clk i2c2_sda iocon_p1_18 p1[18] usb_up_led1 pwm1[1] t1_cap0 ssp1_miso iocon_p1_19 p1[19] usb_tx_e1 usb_ppwr1 t1_cap1 mc_0a ssp1_sck u2_oe iocon_p1_20 p1[20] usb_tx_d p1 pwm1[2] qei_pha mc_fb0 ssp 0_sck lcd_vd[6] lcd_vd[10] iocon_p1_21 p1[21] usb_tx_d m1 pwm1[3] ssp0_ssel mc_abort lcd_vd[7] lcd_vd[11] iocon_p1_22 p1[22] usb_rcv1 usb_pwrd1 t1_mat0 mc_0b ssp1_mosi lcd_vd[8] lcd_vd[12] iocon_p1_23 p1[23] usb_rx_dp1 pwm1[4] qei_phb mc_fb1 ssp0_miso lcd_vd[9] lcd_vd[13] iocon_p1_24 p1[24] usb_rx_dm1 pwm1[5] qei_idx mc_fb2 ssp0_mosi lcd_vd[10] lcd_vd[14] iocon_p1_25 p1[25] usb_ls1 usb_hsten1 t1_mat1 mc_1a clkout lcd_vd[11] lcd_vd[15] iocon_p1_26 p1[26] usb_sspnd1 pwm1[6] t0_cap0 mc_1b ssp1_ ssel lcd_vd[12] lcd_vd[20] iocon_p1_27 p1[27] usb_int1 usb_ovrcr1 t0_cap1 clkout lcd_vd[13] lcd_vd[21] iocon_p1_28 p1[28] usb_scl1 pwm1_cap0 t0_mat0 mc_2a ssp0_ ssel lcd_vd[14] lcd_vd[22] iocon_p1_29 p1[29] usb_sda1 pwm1_cap1 t0_mat1 mc_2b u4_txd lcd_vd[15] lcd_vd[23] iocon_p2_0 p2[0] pwm1[1] u1_txd lcd_pwr iocon_p2_1 p2[1] pwm1[2] u1_rxd lcd_le iocon_p2_2 p2[2] pwm1[3] u1_cts t2_mat3 tracedata[3] lcd_dclk iocon_p2_3 p2[3] pwm1[4] u1_dcd t2_mat2 tracedata[2] lcd_fp iocon_p2_4 p2[4] pwm1[5] u1_dsr t2_mat1 tracedata[1] lcd_enab_m iocon_p2_5 p2[5] pwm1[6] u1_dtr t2_mat0 tracedata[0] lcd_lp iocon_p2_6 p2[6] pwm1_cap0 u1_ri t2_cap0 u2_oe traceclk lcd_vd[0] lcd_vd[4] iocon_p2_7 p2[7] can_rd2 u1_rts spifi_cs lcd_vd[1] lcd_vd[5] iocon_p2_8 p2[8] can_td2 u2_txd u1_cts enet_mdc lcd_vd[2] lcd_vd[6] iocon_p2_9 p2[9] usb_connec t1 u2_rxd u4_rxd enet_mdio lcd_vd[3] lcd_vd[7] iocon_p2_10 p2[10] eint0 nmi iocon_p2_11 p2[11] eint1 sd_dat[1] i2s_tx_sck lcd_clkin iocon_p2_12 p2[12] eint2 sd_dat[2] i2s_tx_ws lcd_vd[4] lcd_vd[3] lcd_vd[8] lcd_vd[18] iocon_p2_13 p2[13] eint3 sd_dat[3] i2s_tx_sda lcd_vd[5] lcd_vd[9] lcd_vd[19] iocon_p2_14 p2[14] emc_cs2 i2c1_sda t2_cap0 iocon_p2_15 p2[15] emc_cs3 i2c1_scl t2_cap1 iocon_p2_16 p2[16] emc_cas table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 133 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p2_17 p2[17] emc_ras iocon_p2_18 p2[18] emc_clk0 iocon_p2_19 p2[19] emc_clk1 iocon_p2_20 p2[20] emc_dycs0 iocon_p2_21 p2[21] emc_dycs1 iocon_p2_22 p2[22] emc_dycs2 ssp0_sck t3_cap0 iocon_p2_23 p2[23] emc_dycs3 ssp0_ssel t3_cap1 iocon_p2_24 p2[24] emc_cke0 iocon_p2_25 p2[25] emc_cke1 iocon_p2_26 p2[26] emc_cke2 ssp0_miso t3_mat0 iocon_p2_27 p2[27] emc_cke3 ssp0_mosi t3_mat1 iocon_p2_28 p2[28] emc_dqm0 iocon_p2_29 p2[29] emc_dqm1 iocon_p2_30 p2[30] emc_dqm2 i2c2_sda t3_mat2 iocon_p2_31 p2[31] emc_dqm3 i2c2_scl t3_mat3 iocon_p3_0 p3[0] emc_d[0] iocon_p3_1 p3[1] emc_d[1] iocon_p3_2 p3[2] emc_d[2] iocon_p3_3 p3[3] emc_d[3] iocon_p3_4 p3[4] emc_d[4] iocon_p3_5 p3[5] emc_d[5] iocon_p3_6 p3[6] emc_d[6] iocon_p3_7 p3[7] emc_d[7] iocon_p3_8 p3[8] emc_d[8] iocon_p3_9 p3[9] emc_d[9] iocon_p3_10 p3[10] emc_d[10] iocon_p3_11 p3[11] emc_d[11] iocon_p3_12 p3[12] emc_d[12] iocon_p3_13 p3[13] emc_d[13] iocon_p3_14 p3[14] emc_d[14] table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 134 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p3_15 p3[15] emc_d[15] iocon_p3_16 p3[16] emc_d[16] pwm0[1] u1_txd iocon_p3_17 p3[17] emc_d[17] pwm0[2] u1_rxd iocon_p3_18 p3[18] emc_d[18] pwm0[3] u1_cts iocon_p3_19 p3[19] emc_d[19] pwm0[4] u1_dcd iocon_p3_20 p3[20] emc_d[20] pwm0[5] u1_dsr iocon_p3_21 p3[21] emc_d[21] pwm0[6] u1_dtr iocon_p3_22 p3[22] emc_d[22] pwm0_cap0 u1_ri iocon_p3_23 p3[23] emc_d[23] pwm1_cap0 t0_cap0 iocon_p3_24 p3[24] emc_d[24] pwm1[1] t0_cap1 iocon_p3_25 p3[25] emc_d[25] pwm1[2] t0_mat0 iocon_p3_26 p3[26] emc_d[26] pwm1[3] t0_mat1 stclk iocon_p3_27 p3[27] emc_d[27] pwm1[4] t1_cap0 iocon_p3_28 p3[28] emc_d[28] pwm1[5] t1_cap1 iocon_p3_29 p3[29] emc_d[29] pwm1[6] t1_mat0 iocon_p3_30 p3[30] emc_d[30] u1_rts t1_mat1 iocon_p3_31 p3[31] emc_d[31] t1_mat2 iocon_p4_0 p4[0] emc_a[0] iocon_p4_1 p4[1] emc_a[1] iocon_p4_2 p4[2] emc_a[2] iocon_p4_3 p4[3] emc_a[3] iocon_p4_4 p4[4] emc_a[4] iocon_p4_5 p4[5] emc_a[5] iocon_p4_6 p4[6] emc_a[6] iocon_p4_7 p4[7] emc_a[7] iocon_p4_8 p4[8] emc_a[8] iocon_p4_9 p4[9] emc_a[9] iocon_p4_10 p4[10] emc_a[10] iocon_p4_11 p4[11] emc_a[11] iocon_p4_12 p4[12] emc_a[12] table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 135 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration iocon_p4_13 p4[13] emc_a[13] iocon_p4_14 p4[14] emc_a[14] iocon_p4_15 p4[15] emc_a[15] iocon_p4_16 p4[16] emc_a[16] iocon_p4_17 p4[17] emc_a[17] iocon_p4_18 p4[18] emc_a[18] iocon_p4_19 p4[19] emc_a[19] iocon_p4_20 p4[20] emc_a[20] i2c2_sda ssp1_sck iocon_p4_21 p4[21] emc _a[21] i2c2_scl ssp1_ssel iocon_p4_22 p4[22] emc_a[22] u2_txd ssp1_miso iocon_p4_23 p4[23] emc_a[23] u2_rxd ssp1_mosi iocon_p4_24 p4[24] emc_oe iocon_p4_25 p4[25] emc_we iocon_p4_26 p4[26] emc_bls0 iocon_p4_27 p4[27] emc_bls1 iocon_p4_28 p4[28] emc_bls2 u3_txd t2_mat0 lcd_vd[6] lcd_vd[10] lcd_vd[2] iocon_p4_29 p4[29] emc_bls3 u3_rxd t2_mat1 i2c2_scl lcd_vd[7] lcd_vd[11] lcd_vd[3] iocon_p4_30 p4[30] emc_cs0 cmp0_out iocon_p4_31 p4[31] emc_cs1 iocon_p5_0 p5[0] emc_a[24] t2_mat2 iocon_p5_1 p5[1] emc_a[25] t2_mat3 iocon_p5_4 p5[4] u0_oe t3_mat3 u4_txd table 83. type d i/o control regist ers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 136 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.2 type a iocon registers (applies to pins that include an analog function) this iocon table applies to pins p0[12 to 13], p0[23 to 26], and p1[30 to 31]. the presence of the dac output on p0[26] makes th at pin slightly different, see the description of bit 16 below. table 84. type a iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see table 85 for specific values. 0 4:3 mode selects function mode (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 10 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 - reserved. read value is undefined, only zero should be written. na 6 invert input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 admode select analog/digital mode. see section 7.3.5 ? analog/digital mode ? .1 0 analog mode. 1digital mode. 8 filter controls glitch filter. see section 7.3.6 ? input filter ? .1 0 noise pulses below approximately 10 ns are filtered out 1 no input filtering is done 9 - reserved. read value is undefined, only zero should be written. na 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 14:11 - reserved. read value is undefined, only zero should be written. na 16 dacen dac enable control. this bit applies only to p0[26], which includes the dac output function dac_out. see section 7.3.10 ? dac enable ? . 0 0 dac is disabled 1 dac is enabled 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 137 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 85. type a i/o control registers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_12 p0[12] usb_ppwr2 ssp1_miso adc0[6] iocon_p0_13 p0[13] usb_up_led2 ssp1_mosi adc0[7] iocon_p0_23 p0[23] adc0[0] i2s_rx_sck t3_cap0 iocon_p0_24 p0[24] adc0[1] i2s_rx_ws t3_cap1 iocon_p0_25 p0[25] adc0[2] i2s_rx_sda u3_txd iocon_p0_26 p0[26] adc0[3] dac_out u3_rxd iocon_p1_30 p1[30] usb_pwrd2 u sb_vbus adc[4] i2c0_sda u3_oe iocon_p1_31 p1[31] usb_ovrcr2 ssp1_sck adc[5] i2c0_scl
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 138 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.3 type u iocon registers (applies to pins that include a usb d+ or d- function) this iocon table applies to pins p0[29], p0[30], and p0[31]. these special function pins do not include the selectable modes and options of other pins. table 86. type u iocon registers bit description bit symbol description reset value 2:0 func selects pin function. see table 87 for specific values. 000 31:3 - reserved. read value is undefined, only zero should be written. na table 87. type u i/o control registers: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_29 p0[29] usb_d+1 eint0 iocon_p0_30 p0[30] usb_d-1 eint1 iocon_p0_31 p0[31] usb_d+2
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 139 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.4 type i iocon registers (applies to pins that include a specialized i 2 c function) this iocon table applies to pins p0[27 to 28] and p5[2 to 3]. table 88. type i iocon re gisters bit description bit symbol value description reset value 2:0 func selects pin function. see table 89 for specific values. 0 5:3 - reserved. read value is undefined, only zero should be written. na 6 invert input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 - reserved. read value is undefined, only zero should be written. na 8 hs configures i 2 c features for standard mode, fast mode, and fast mode plus operation. see section 7.3.8 ? i 2 c modes ? . 0 0i 2 c 50ns glitch filter and slew rate control enabled. 1i 2 c 50ns glitch filter and slew rate control disabled. 9 hidrive controls sink current capability of the pin, only for p5[2] and p5[3]. see section 7.3.8 ? i 2 c modes ? . 0 0 output drive sink is 4 ma. this is sufficient for standard and fast mode i 2 c. 1 output drive sink is 20 ma. this is needed for fast mode plus i 2 c. refer to the appropriate specific device data sheet for details. 31:10 - reserved. read value is undefined, only zero should be written. na table 89. type i i/o control register s: func values and pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_27 p0[27] i2c0_sda usb_sda1 iocon_p0_28 p0[28] i2c0_scl usb_scl1 iocon_p5_2 p5[2] t3_mat2 i2c0_sda iocon_p5_3 p5[3] u4_rxd i2c0_scl
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 140 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration 7.4.1.5 type w iocon registers (these pins are otherwise the same as type d, but include a selectable input glitch filter, and default to pull-down/pull-up disabled). this iocon table applies to pi ns p0[7], p0[8], and p0[9]. table 90. type w iocon registers bit description bit symbol value description reset value 2:0 func selects pin function. see table 91 for specific values. 000 4:3 mode selects the output functional mode for the pin (on-chip pull-up/pull-down resistor control). see section 7.3.2 ? pin mode ? . 00 00 inactive (no pull-down/pull-up resistor enabled). 01 pull-down resistor enabled. 10 pull-up resistor enabled. 11 repeater mode. 5 hys hysteresis. see section 7.3.3 ? hysteresis ? .1 0 disable. 1 enable. 6 inv input polarity. see section 7.3.4 ? input inversion ? .0 0 input is not inverted (a high on the pin reads as 1) 1 input is inverted (a high on the pin reads as 0) 7 admode select analog/digital mode. see section 7.3.5 ? analog/digital mode ? .1 0 analog mode. 1digital mode. 8 filter controls glitch filter. see section 7.3.6 ? input filter ? .0 0 noise pulses below approximately 10 ns are filtered out 1 no input filtering is done 9 slew driver slew rate. see section 7.3.7 ? output slew rate ? .0 0 standard mode, output slew rate control is enabled. more outputs can be switched simultaneously. 1 fast mode, slew rate control is disabled. refer to the appropriate specific device data sheet for details. 10 od controls open-drain mode. see section 7.3.9 ? open-drain mode ? .0 0 normal push-pull output 1 simulated open-drain output (high drive disabled) 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 141 of 942 nxp semiconductors UM10562 chapter 7: lpc408x/407x i/o configuration table 91. type w i/o control regist ers: func values an d pin functions value of func field in iocon register register 000 001 010 011 100 101 110 111 iocon_p0_7 p0[7] i2s_tx_sck ssp1_sck t2_mat1 rtc_ev0 cmp_vref lcd_vd[9] iocon_p0_8 p0[8] i2s_tx_ws ssp1_miso t2_mat2 rtc_ev1 cmp1_in[4] lcd_vd[16] iocon_p0_9 p0[9] i2s_tx_sda ssp1_mosi t2_mat3 rtc_ev2 cmp1_in[3] lcd_vd[17] iocon_p1_5 p1[5] enet_tx_er sd_pwr pwm0[3] cmp1_in[2] iocon_p1_6 p1[6] enet_tx_clk sd_dat[0] pwm0[4] cmp0_in[4] iocon_p1_7 p1[7] enet_col sd_dat[1] pwm0[5] cmp1_in[1] iocon_p1_14 p1[14] enet_rx_er t2_cap0 cmp0_in[1] iocon_p1_16 p1[16] enet_mdc i2s_tx_mclk cmp0_in[2] iocon_p1_17 p1[17] enet_mdio i2s_rx_mclk cmp0_in[3]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 142 of 942 8.1 basic configuration gpios are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcgpio. this enables the gpios themselves, gpio inte rrupts, and the iocon block. 2. pins: see section 7.4.1 for gpio pins and their modes. 3. wake-up: gpio ports 0 and 2 can be used for wake-up if needed, see ( section 3.12.8 ). 4. interrupts: enable gpio interrupts in enr ( ta b l e 1 0 4 or table 109 ) and enf ( table 105 or table 110 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 8.2 features 8.2.1 digital i/o ports ? accelerated gpio functions: ? gpio registers are located on a peripheral ahb bus for fast i/o timing. ? mask registers allow treating sets of port bits as a group, leaving other bits unchanged. ? all gpio registers are byte, hal f-word, and word addressable. ? entire port value can be written in one instruction. ? gpio registers are accessible by the gpdma. ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? all gpio registers support bit-banding operations by the cpu. ? gpio registers are accessible by the gpdma controller to allow dma of data to or from gpios, synchronized to any dma request. ? direction control of individual port bits. ? all i/os default to input with pull-up after reset. 8.2.2 interrupt generating digital ports ? port 0 and port 2 can provide a single interrupt for any combination of port pins. ? each port pin can be programmed to genera te an interrupt on a rising edge, a falling edge, or both. ? edge detection is asynchronous, so it may operate when clocks are not present, such as during power-down mode. with this feature, level tr iggered interrupts are not needed. ? each enabled interrupt contributes to a wake -up signal that can be used to bring the part out of power-down mode. UM10562 chapter 8: lpc408x/407x gpio rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 143 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio ? registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending gpio interrupts. ? the gpio interrupt function does not require that the pin be configured for gpio. this allows interrupting on a change to a pin that is part of an operating peripheral interface. 8.3 applications ? general purpose i/o ? driving leds or other indicators ? controlling off-chip devices ? sensing digital inputs, detecting edges ? bringing the part out of power-down mode 8.4 pin description table 92. gpio pin description pin name type description p0[31:0]; p1[31:0]; p2[31:0]; p3[31:0]; p4[31:0]; p5[4:0] input/ output general purpose input/output. these are typically s hared with other peripherals functions and will therefore not all be available in an application. packaging options may affect the number of gpios available in a particular device. some pins may be limited by requirements of the alternate functions of the pin. for example, some pins that can be used for i 2 c are special pins, and some of that behavior is inherited by any other function selected on that pin. details may be found in section 6.1 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 144 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5 register description the registers represent the enhanced gpio feat ures available on all of the gpio ports. these registers are located on an ahb bus for fa st read and write timing. they can all be accessed in byte, half-word, and word sizes. a mask register allows access to a group of bits in a single gpio port independently from other bits in the same port. table 93. register overview: gpio (base address 0x2009 8000) name access address offset description reset value table dir0 r/w 0x000 gpio port0 direction control register. 0 95 mask0 r/w 0x010 mask register for port0. 0 96 pin0 r/w 0x014 port0 pin value register using fiomask. 0 97 set0 r/w 0x018 port0 output set register using fiomask. 0 98 clr0 wo 0x01c port0 output clear register using fiomask. - 99 dir1 r/w 0x020 gpio port1 direction control register. 0 95 mask1 r/w 0x030 mask register for port1. 0 96 pin1 r/w 0x034 port1 pin value register using fiomask. 0 97 set1 r/w 0x038 port1 output set register using fiomask. 0 98 clr1 wo 0x03c port1 output clear register using fiomask. - 99 dir2 r/w 0x040 gpio port2 direction control register. 0 95 mask2 r/w 0x050 mask register for port2. 0 96 pin2 r/w 0x054 port2 pin value register using fiomask. 0 97 set2 r/w 0x058 port2 output set register using fiomask. 0 98 clr2 wo 0x05c port2 output clear register using fiomask. - 99 dir3 r/w 0x060 gpio port3 direction control register. 0 95 mask3 r/w 0x070 mask register for port3. 0 96 pin3 r/w 0x074 port3 pin value register using fiomask. 0 97 set3 r/w 0x078 port3 output set register using fiomask. 0 98 clr3 wo 0x07c port3 output clear register using fiomask. - 99 dir4 r/w 0x080 gpio port4 direction control register. 0 95 mask4 r/w 0x090 mask register for port4. 0 96 pin4 r/w 0x094 port4 pin value register using fiomask. 0 97 set4 r/w 0x098 port4 output set register using fiomask. 0 98 clr4 wo 0x09c port4 output clear register using fiomask. - 99 dir5 r/w 0x0a0 gpio port5 direction control register. 0 95 mask5 r/w 0x0b0 mask register for port5. 0 96 pin5 r/w 0x0b4 port5 pin value register using fiomask. 0 97 set5 r/w 0x0b8 port5 output se t register using fiomask. 0 98 clr5 wo 0x0bc port5 output clear register using fiomask. - 99
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 145 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 94. register overview: gpio interrupt (base address 0x4002 8000) name access address offset description reset value [1] table status ro 0x080 gpio overall interrupt status. 0 100 statr0 ro 0x084 gpio interrupt status for rising edge for port 0. 0 101 statf0 ro 0x088 gpio interrupt status for falling edge for port 0. 0 102 clr0 wo 0x08c gpio interrupt clear. - 103 enr0 r/w 0x090 gpio interrupt enable for rising edge for port 0. 0 104 enf0 r/w 0x094 gpio interrupt enable for falling edge for port 0. 0 105 statr2 ro 0x0a4 gpio interrupt status for rising edge for port 0. 0 106 statf2 ro 0x0a8 gpio interrupt status for falling edge for port 0. 0 107 clr2 wo 0x0ac gpio interrupt clear. - 108 enr2 r/w 0x0b0 gpio interrupt enable for rising edge for port 0. 0 109 enf2 r/w 0x0b4 gpio interrupt enable for falling edge for port 0. 0 110
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 146 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.1 gpio port registers 8.5.1.1 gpio port direction register this word accessible register is used to c ontrol the direction of the pins when they are configured as gpio port pins. direction bit for any pin must be set according to the pin functionality. note that gpio pins p0[29] and p0[30] ar e shared with the usb_d+ and usb_d- pins and must have the same direction. if either fi o0dir bit 29 or 30 are configured as zero, both p0[29] and p0[30] will be inputs. if both fio0dir bits 29 and 30 ar e ones, both p0[29] and p0[30] will be outputs. aside from the 32-bit long and word only acce ssible dirx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.2 fast gpio port mask register this register is used to select port pins that will and w ill not be affected by write accesses to the pinx, setx or clrx register. mask regist er also filters out port?s content when the pinx register is read. a zero in this register?s bit enables an access to the corresponding physical pin via a read or write access. if a bit in this register is one, corresponding pin w ill not be changed with write access and if read, will not be reflected in the updated pinx register. for software examples, see section 8.6 . aside from the 32-bit long and word only acce ssible maskx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.3 gpio port pin value register this register provides the value of port pins that are configured to perform only digital functions. the register will give the logic value of the pin re gardless of whether the pin is configured for input or output, or as gpio or an alternate digital function. as an example, table 95. gpio port direction register (dir[0:5] - addresses 0x2009 8000 (dir0) to 0x200980a0 (dir5)) bit description bit symbol description reset value 31:0 pindir fast gpio direction portx control bits. bit 0 in dirx controls pin px[0], bit 31 in dirx controls pin px[31]. 0 = controlled pin is input. 1 = controlled pin is output. 0x0 table 96. fast gpio port mask register (mask[0:5] - addresses 0x2009 8010 (mask0) to 0x2009 80b0 (mask5)) bit description bit symbol description reset value 31:0 pinmask fast gpio physical pin access control. 0 = controlled pin is affected by writes to th e port?s setx, clrx, and pinx registers. current state of the pin can be read from the pinx register. 1 = controlled pin is not affected by writes into the port?s setx, clrx and pinx registers. when the pinx register is read, this bit will not be updated with the state of the physical pin. 0x0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 147 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio a particular port pin may have gpio input, gpio output, uart receive, and pwm output as selectable functions. any configuration of that pin will allo w its current logic state to be read from the corresponding pinx register. if a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. selecting the pin as an a/d input disconnects the digital features of the pin. in that case, the pin value read in the pinx register is not valid. writing to the pinx register st ores the value in the port output register, bypassing the need to use both the setx and clrx registers to ob tain the entire written value. this feature should be used carefully in an application since it affects the entire port. access to a port pin via the pinx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). only pins masked with zeros in the mask register (see section 8.5.1.2 ) will be correlated to the current content of the fast gpio port pin value register. aside from the 32-bit long and word only acce ssible pinx register, every fast gpio port can also be controlled via byte and half-word access. 8.5.1.4 gpio port output set register this register is used to produce a high level output at the port pins configured as gpio in an output mode. writing 1 produces a high level at the corresponding port pins. writing 0 has no effect. if any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the setx has no effect. reading the setx register returns the value of this register, as determined by previous writes to setx and clrx (or pi nx as noted above). this value does not reflect the effect of any outside world influence on the i/o pins. access to a port pin via the setx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). aside from the 32-bit long and word only acce ssible setx register, every fast gpio port can also be controlled via byte and half-word access. table 97. fast gpio port pin value register (pin[0:5] - addresses 0x2009 8014 (pin0) to 0x2009 80b4 (pin5)) bit description bit symbol description reset value 31:0 pinval fast gpio output value set bits. bit 0 in clrx corresponds to pin px[0], bit 31 in clrx corresponds to pin px[31]. 0 = controlled pin output is set to low. 1 = controlled pin output is set to high. 0x0 table 98. fast gpio port output set register (set[0:5] - addresses 0x2009 8018 (set0) to 0x2009 80b8 (set5)) bit description bit symbol description reset value 31:0 pinset fast gpio output value set bits. bit 0 in setx controls pin px[0], bit 31 in setx controls pin px[31]. 0 = controlled pin output is unchanged. 1 = controlled pin output is set to high. 0x0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 148 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.1.5 gpio port output clear register this register is used to produce a low level ou tput at port pins configured as gpio in an output mode. writing 1 produces a low level at the corresponding port pin and clears the corresponding bit in the setx register. writ ing 0 has no effect. if any pin is configured as an input or a secondary function, writing to clrx has no effect. access to a port pin via the clrx register is conditioned by the corresponding bit of the maskx register (see section 8.5.1.2 ). aside from the 32-bit long and word only ac cessible clrx register, every fast gpio port can also be controlled via byte and half-word access. table 99. fast gpio port output clear register (clr[0:5] - addresses 0x2009 801c (clr0) to 0x2009 80bc (clr5)) bit description bit symbol description 31:0 pinclr fast gpio output value clear bits. bit 0 in clrx controls pin px[0], bit 31 controls pin px[31]. 0 = controlled pin output is unchanged. 1 = controlled pin output is set to low.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 149 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2 gpio interrupt registers the following registers configure the pins of port 0 and port 2 to generate interrupts. 8.5.2.1 gpio overall interrupt status register this read-only register indicates the presence of interrupt pending on all of the gpio ports that support gpio interrupts. only st atus one bit per port is required. fig 15. gpio interrupt block diagram apb bus rising edge enable register (gpiointenr) apb bus d q r d q r 1 1 write 1 to gpiointcl gpiointstatr register (read only) falling edge enable register (gpiointenf) gpiointstatus register gpiointstatf register (read only) gpiowake (from intwake register) for each supported gpio pin other pinj ints for each supported gpio port to nvic other port ints plus one existing interrupt to wakeup other port wakeups port wakeup port int one per device pin 120608 pin int table 100. gpio overall interrupt status register (status - address 0x4002 8080) bit description bit symbol value description reset value 0 p0int port 0 gpio interrupt pending. 0 0 no pending interrupts on port 0. 1 at least one pending interrupt on port 0. 1 - reserved. the value read from a reserved bit is not defined. na 2 p2int port 2 gpio interrupt pending. 0 0 no pending interrupts on port 2. 1 at least one pending interrupt on port 2. 31:2 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 150 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.2 gpio interrupt status for port 0 rising edge interrupt each bit in these read-only registers indicates the rising edge interrupt status for port 0. table 101. gpio interrupt status for port 0 ri sing edge interrupt (statr0 - 0x4002 8084) bit description bit symbol description reset value 0 p0_0rei rising edge interrupt status for p0[0]. 0 = no rising edge detected. 1 = rising edge interrupt generated. 0 1 p0_1rei rising edge interrupt status for p0[1]. see bit 0 description. 0 2 p0_2rei rising edge interrupt status for p0[2]. see bit 0 description. 0 3 p0_3rei rising edge interrupt status for p0[3]. see bit 0 description. 0 4 p0_4rei rising edge interrupt status for p0[4]. see bit 0 description. 0 5 p0_5rei rising edge interrupt status for p0[5]. see bit 0 description. 0 6 p0_6rei rising edge interrupt status for p0[6]. see bit 0 description. 0 7 p0_7rei rising edge interrupt status for p0[7]. see bit 0 description. 0 8 p0_8rei rising edge interrupt status for p0[8]. see bit 0 description. 0 9 p0_9rei rising edge interrupt status for p0[9]. see bit 0 description. 0 10 p0_10rei rising edge interrupt status for p0[10]. see bit 0 description. 0 11 p0_11rei rising edge interrupt status for p0[11]. see bit 0 description. 0 12 p0_12rei rising edge interrupt status for p0[12]. see bit 0 description. 0 13 p0_13rei rising edge interrupt status for p0[13]. see bit 0 description. 0 14 p0_14rei rising edge interrupt status for p0[14]. see bit 0 description. 0 15 p0_15rei rising edge interrupt status for p0[15]. see bit 0 description. 0 16 p0_16rei rising edge interrupt status for p0[16]. see bit 0 description. 0 17 p0_17rei rising edge interrupt status for p0[17]. see bit 0 description. 0 18 p0_18rei rising edge interrupt status for p0[18]. see bit 0 description. 0 19 p0_19rei rising edge interrupt status for p0[19]. see bit 0 description. 0 20 p0_20rei rising edge interrupt status for p0[20]. see bit 0 description. 0 21 p0_21rei rising edge interrupt status for p0[21]. see bit 0 description. 0 22 p0_22rei rising edge interrupt status for p0[22]. see bit 0 description. 0 23 p0_23rei rising edge interrupt status for p0[23]. see bit 0 description. 0 24 p0_24rei rising edge interrupt status for p0[24]. see bit 0 description. 0 25 p0_25rei rising edge interrupt status for p0[25]. see bit 0 description. 0 26 p0_26rei rising edge interrupt status for p0[26]. see bit 0 description. 0 27 p0_27rei rising edge interrupt status for p0[27]. see bit 0 description. 0 28 p0_28rei rising edge interrupt status for p0[28]. see bit 0 description. 0 29 p0_29rei rising edge interrupt status for p0[29]. see bit 0 description. 0 30 p0_30rei rising edge interrupt status for p0[30]. see bit 0 description. 0 31 p0_31rei rising edge interrupt status for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 151 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.3 gpio interrupt status for port 0 falling edge interrupt each bit in these read-only re gisters indicates the falling ed ge interrupt status for port 0. table 102. gpio interrupt status for port 0 falling edge interrupt (statf0 - 0x4002 8088) bit description bit symbol description reset value 0 p0_0fei falling edge interrupt status for p0[0]. 0 = no falling edge detected. 1 = falling edge interrupt generated. 0 1 p0_1fei falling edge interrupt status for p0[1]. see bit 0 description. 0 2 p0_2fei falling edge interrupt status for p0[2]. see bit 0 description. 0 3 p0_3fei falling edge interrupt status for p0[3]. see bit 0 description. 0 4 p0_4fei falling edge interrupt status for p0[4]. see bit 0 description. 0 5 p0_5fei falling edge interrupt status for p0[5]. see bit 0 description. 0 6 p0_6fei falling edge interrupt status for p0[6]. see bit 0 description. 0 7 p0_7fei falling edge interrupt status for p0[7]. see bit 0 description. 0 8 p0_8fei falling edge interrupt status for p0[8]. see bit 0 description. 0 9 p0_9fei falling edge interrupt status for p0[9]. see bit 0 description. 0 10 p0_10fei falling edge interrupt status for p0[10]. see bit 0 description. 0 11 p0_11fei falling edge interrupt status for p0[11]. see bit 0 description. 0 12 p0_12fei falling edge interrupt status for p0[12]. see bit 0description. 0 13 p0_13fei falling edge interrupt status for p0[13]. see bit 0 description. 0 14 p0_14fei falling edge interrupt status for p0[14]. see bit 0 description. 0 15 p0_15fei falling edge interrupt status for p0[15]. see bit 0 description. 0 16 p0_16fei falling edge interrupt status for p0[16]. see bit 0 description. 0 17 p0_17fei falling edge interrupt status for p0[17]. see bit 0 description. 0 18 p0_18fei falling edge interrupt status for p0[18]. see bit 0 description. 0 19 p0_19fei falling edge interrupt status for p0[19]. see bit 0 description. 0 20 p0_20fei falling edge interrupt status for p0[20]. see bit 0 description. 0 21 p0_21fei falling edge interrupt status for p0[21]. see bit 0 description. 0 22 p0_22fei falling edge interrupt status for p0[22]. see bit 0 description. 0 23 p0_23fei falling edge interrupt status for p0[23]. see bit 0 description. 0 24 p0_24fei falling edge interrupt status for p0[24]. see bit 0 description. 0 25 p0_25fei falling edge interrupt status for p0[25]. see bit 0 description. 0 26 p0_26fei falling edge interrupt status for p0[26]. see bit 0 description. 0 27 p0_27fei falling edge interrupt status for p0[27]. see bit 0 description. 0 28 p0_28fei falling edge interrupt status for p0[28]. see bit 0 description. 0 29 p0_29fei falling edge interrupt status for p0[29]. see bit 0 description. 0 30 p0_30fei falling edge interrupt status for p0[30]. see bit 0 description. 0 31 p0_31fei falling edge interrupt status for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 152 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.4 gpio interrupt clear register for port 0 writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 0 pin. table 103. gpio interrupt clear register for port 0 (clr0 - 0x4002 808c) bit description bit symbol description 0 p0_0ci clear gpio port interrupts for p0[0]. 0 = no effect. 1 = clear corresponding bits in ionintstatr and ionstatf. 1 p0_1ci clear gpio port interrupts for p0[1]. see bit 0 description. 2 p0_2ci clear gpio port interrupts for p0[2]. see bit 0 description. 3 p0_3ci clear gpio port interrupts for p0[3]. see bit 0 description. 4 p0_4ci clear gpio port interrupts for p0[4]. see bit 0 description. 5 p0_5ci clear gpio port interrupts for p0[5]. see bit 0 description. 6 p0_6ci clear gpio port interrupts for p0[6]. see bit 0 description. 7 p0_7ci clear gpio port interrupts for p0[7]. see bit 0 description. 8 p0_8ci clear gpio port interrupts for p0[8]. see bit 0 description. 9 p0_9ci clear gpio port interrupts for p0[9]. see bit 0 description. 10 p0_10ci clear gpio port interrupts for p0[10]. see bit 0 description. 11 p0_11ci clear gpio port interrupts for p0[11]. see bit 0 description. 12 p0_12ci clear gpio port interrupts for p0[12]. see bit 0 description. 13 p0_13ci clear gpio port interrupts for p0[13]. see bit 0 description. 14 p0_14ci clear gpio port interrupts for p0[14]. see bit 0 description. 15 p0_15ci clear gpio port interrupts for p0[15]. see bit 0 description. 16 p0_16ci clear gpio port interrupts for p0[16]. see bit 0 description. 17 p0_17ci clear gpio port interrupts for p0[17]. see bit 0 description. 18 p0_18ci clear gpio port interrupts for p0[18]. see bit 0 description. 19 p0_19ci clear gpio port interrupts for p0[19]. see bit 0 description. 20 p0_20ci clear gpio port interrupts for p0[20]. see bit 0 description. 21 p0_21ci clear gpio port interrupts for p0[21]. see bit 0 description. 22 p0_22ci clear gpio port interrupts for p0[22]. see bit 0 description. 23 p0_23ci clear gpio port interrupts for p0[23]. see bit 0 description. 24 p0_24ci clear gpio port interrupts for p0[24]. see bit 0 description. 25 p0_25ci clear gpio port interrupts for p0[25]. see bit 0 description. 26 p0_26ci clear gpio port interrupts for p0[26]. see bit 0 description. 27 p0_27ci clear gpio port interrupts for p0[27]. see bit 0 description. 28 p0_28ci clear gpio port interrupts for p0[28]. see bit 0 description. 29 p0_29ci clear gpio port interrupts for p0[29]. see bit 0 description. 30 p0_30ci clear gpio port interrupts for p0[30]. see bit 0 description. 31 p0_31ci clear gpio port interrupts for p0[31]. see bit 0 description.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 153 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.5 gpio interrupt enable for port 0 rising edge each bit in these read-write registers enables the rising edge interrupt for the corresponding port 0 pin. which pins are available depends on the part number and package combination. see the specific device data sheet for details. table 104. gpio interrupt enable for port 0 rising edge (enr0 - 0x4002 8090) bit description bit symbol description reset value 0 p0_0er enable rising edge interrupt for p0[0]. 0 = disable rising edge interrupt. 1 = enable rising edge interrupt. 0 1 p0_1er enable rising edge interrupt for p0[1]. see bit 0 description. 0 2 p0_2er enable rising edge interrupt for p0[2]. see bit 0 description. 0 3 p0_3er enable rising edge interrupt for p0[3]. see bit 0 description. 0 4 p0_4er enable rising edge interrupt for p0[4]. see bit 0 description. 0 5 p0_5er enable rising edge interrupt for p0[5]. see bit 0 description. 0 6 p0_6er enable rising edge interrupt for p0[6]. see bit 0 description. 0 7 p0_7er enable rising edge interrupt for p0[7]. see bit 0 description. 0 8 p0_8er enable rising edge interrupt for p0[8]. see bit 0 description. 0 9 p0_9er enable rising edge interrupt for p0[9]. see bit 0 description. 0 10 p0_10er enable rising edge interrupt for p0[10]. see bit 0 description. 0 11 p0_11er enable rising edge interrupt for p0[11]. see bit 0 description. 0 12 p0_12er enable rising edge interrupt for p0[12]. see bit 0 description. 0 13 p0_13er enable rising edge interrupt for p0[13]. see bit 0 description. 0 14 p0_14er enable rising edge interrupt for p0[14]. see bit 0 description. 0 15 p0_15er enable rising edge interrupt for p0[15]. see bit 0 description. 0 16 p0_16er enable rising edge interrupt for p0[16]. see bit 0 description. 0 17 p0_17er enable rising edge interrupt for p0[17]. see bit 0 description. 0 18 p0_18er enable rising edge interrupt for p0[18]. see bit 0 description. 0 19 p0_19er enable rising edge interrupt for p0[19]. see bit 0 description. 0 20 p0_20er enable rising edge interrupt for p0[20]. see bit 0 description. 0 21 p0_21er enable rising edge interrupt for p0[21]. see bit 0 description. 0 22 p0_22er enable rising edge interrupt for p0[22]. see bit 0 description. 0 23 p0_23er enable rising edge interrupt for p0[23]. see bit 0 description. 0 24 p0_24er enable rising edge interrupt for p0[24]. see bit 0 description. 0 25 p0_25er enable rising edge interrupt for p0[25]. see bit 0 description. 0 26 p0_26er enable rising edge interrupt for p0[26]. see bit 0 description. 0 27 p0_27er enable rising edge interrupt for p0[27]. see bit 0 description. 0 28 p0_28er enable rising edge interrupt for p0[28]. see bit 0 description. 0 29 p0_29er enable rising edge interrupt for p0[29]. see bit 0 description. 0 30 p0_30er enable rising edge interrupt for p0[30]. see bit 0 description. 0 31 p0_31er enable rising edge interrupt for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 154 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.6 gpio interrupt enable for port 0 falling edge each bit in these read-wri te registers enables the fa lling edge interrupt for the corresponding gpio port 0 pin. table 105. gpio interrupt enable for port 0 falling edge (enf0 - address 0x4002 8094) bit description bit symbol description reset value 0 p0_0ef enable falling edge interrupt for p0[0]. 0 = disable falling edge interrupt. 1 = enable falling edge interrupt. 0 1 p0_1ef enable falling edge interrupt for p0[1]. see bit 0 description. 0 2 p0_2ef enable falling edge interrupt for p0[2]. see bit 0 description. 0 3 p0_3ef enable falling edge interrupt for p0[3]. see bit 0 description. 0 4 p0_4ef enable falling edge interrupt for p0[4]. see bit 0 description. 0 5 p0_5ef enable falling edge interrupt for p0[5]. see bit 0 description. 0 6 p0_6ef enable falling edge interrupt for p0[6]. see bit 0 description. 0 7 p0_7ef enable falling edge interrupt for p0[7]. see bit 0 description. 0 8 p0_8ef enable falling edge interrupt for p0[8]. see bit 0 description. 0 9 p0_9ef enable falling edge interrupt for p0[9]. see bit 0 description. 0 10 p0_10ef enable falling edge interrupt for p0[10]. see bit 0 description. 0 11 p0_11ef enable falling edge interrupt for p0[11]. see bit 0 description. 0 12 p0_12ef enable falling edge interrupt for p0[12]. see bit 0 description. 0 13 p0_13ef enable falling edge interrupt for p0[13]. see bit 0 description. 0 14 p0_14ef enable falling edge interrupt for p0[14]. see bit 0 description. 0 15 p0_15ef enable falling edge interrupt for p0[15]. see bit 0 description. 0 16 p0_16ef enable falling edge interrupt for p0[16]. see bit 0 description. 0 17 p0_17ef enable falling edge interrupt for p0[17]. see bit 0 description. 0 18 p0_18ef enable falling edge interrupt for p0[18]. see bit 0 description. 0 19 p0_19ef enable falling edge interrupt for p0[19]. see bit 0 description. 0 20 p0_20ef enable falling edge interrupt for p0[20]. see bit 0 description. 0 21 p0_21ef enable falling edge interrupt for p0[21]. see bit 0 description. 0 22 p0_22ef enable falling edge interrupt for p0[22]. see bit 0 description. 0 23 p0_23ef enable falling edge interrupt for p0[23]. see bit 0 description. 0 24 p0_24ef enable falling edge interrupt for p0[24]. see bit 0 description. 0 25 p0_25ef enable falling edge interrupt for p0[25]. see bit 0 description. 0 26 p0_26ef enable falling edge interrupt for p0[26]. see bit 0 description. 0 27 p0_27ef enable falling edge interrupt for p0[27]. see bit 0 description. 0 28 p0_28ef enable falling edge interrupt for p0[28]. see bit 0 description. 0 29 p0_29ef enable falling edge interrupt for p0[29]. see bit 0 description. 0 30 p0_30ef enable falling edge interrupt for p0[30]. see bit 0 description. 0 31 p0_31ef enable falling edge interrupt for p0[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 155 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.7 gpio interrupt status for port 2 rising edge interrupt each bit in these read-only registers indicates the rising edge interrupt status for port 2. table 106. gpio interrupt status for port 2 rising edge interrupt (statr2 - 0x4002 80a4) bit description bit symbol description reset value 0 p2_0rei status of rising edge interrupt for p2[0]. 0 = no rising edge detected. 1 = rising edge interrupt generated. 0 1 p2_1rei status of rising edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2rei status of rising edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3rei status of rising edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4rei status of rising edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5rei status of rising edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6rei status of rising edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7rei status of rising edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8rei status of rising edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9rei status of rising edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10rei status of rising edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11rei status of rising edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12rei status of rising edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13rei status of rising edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14rei status of rising edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15rei status of rising edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16rei status of rising edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17rei status of rising edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18rei status of rising edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19rei status of rising edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20rei status of rising edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21rei status of rising edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22rei status of rising edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23rei status of rising edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24rei status of rising edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25rei status of rising edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26rei status of rising edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27rei status of rising edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28rei status of rising edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29rei status of rising edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30rei status of rising edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31rei status of rising edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 156 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.8 gpio interrupt status for port 2 falling edge interrupt each bit in these read-only re gisters indicates the falling ed ge interrupt status for port 2. table 107. gpio interrupt status for port 2 falling edge interrupt (statf2 - 0x4002 80a8) bit description bit symbol description reset value 0 p2_0fei status of falling edge interrupt for p2[0]. 0 = no falling edge detected. 1 = falling edge interrupt generated. 0 1 p2_1fei status of falling edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2fei status of falling edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3fei status of falling edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4fei status of falling edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5fei status of falling edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6fei status of falling edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7fei status of falling edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8fei status of falling edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9fei status of falling edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10fei status of falling edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11fei status of falling edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12fei status of falling edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13fei status of falling edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14fei status of falling edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15fei status of falling edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16fei status of falling edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17fei status of falling edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18fei status of falling edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19fei status of falling edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20fei status of falling edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21fei status of falling edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22fei status of falling edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23fei status of falling edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24fei status of falling edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25fei status of falling edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26fei status of falling edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27fei status of falling edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28fei status of falling edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29fei status of falling edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30fei status of falling edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31fei status of falling edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 157 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.9 gpio interrupt clear register for port 2 writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 2 pin. table 108. gpio interrupt clear register for port 0 (clr2 - 0x4002 80ac) bit description bit symbol description 0 p2_0ci clear gpio port interrupts for p2[0]. 0 = no effect. 1 = clear corresponding bits in ionintstatr and ionstatf. 1 p2_1ci clear gpio port interrupts for p2[1]. see bit 0 description. 2 p2_2ci clear gpio port interrupts for p2[2]. see bit 0 description. 3 p2_3ci clear gpio port interrupts for p2[3]. see bit 0 description. 4 p2_4ci clear gpio port interrupts for p2[4]. see bit 0 description. 5 p2_5ci clear gpio port interrupts for p2[5]. see bit 0 description. 6 p2_6ci clear gpio port interrupts for p2[6]. see bit 0 description. 7 p2_7ci clear gpio port interrupts for p2[7]. see bit 0 description. 8 p2_8ci clear gpio port interrupts for p2[8]. see bit 0 description. 9 p2_9ci clear gpio port interrupts for p2[9]. see bit 0 description. 10 p2_10ci clear gpio port interrupts for p2[10]. see bit 0 description. 11 p2_11ci clear gpio port interrupts for p2[11]. see bit 0 description. 12 p2_12ci clear gpio port interrupts for p2[12]. see bit 0 description. 13 p2_13ci clear gpio port interrupts for p2[13]. see bit 0 description. 14 p2_14ci clear gpio port interrupts for p2[14]. see bit 0 description. 15 p2_15ci clear gpio port interrupts for p2[15]. see bit 0 description. 16 p2_16ci clear gpio port interrupts for p2[16]. see bit 0 description. 17 p2_17ci clear gpio port interrupts for p2[17]. see bit 0 description. 18 p2_18ci clear gpio port interrupts for p2[18]. see bit 0 description. 19 p2_19ci clear gpio port interrupts for p2[19]. see bit 0 description. 20 p2_20ci clear gpio port interrupts for p2[20]. see bit 0 description. 21 p2_21ci clear gpio port interrupts for p2[21]. see bit 0 description. 22 p2_22ci clear gpio port interrupts for p2[22]. see bit 0 description. 23 p2_23ci clear gpio port interrupts for p2[23]. see bit 0 description. 24 p2_24ci clear gpio port interrupts for p2[24]. see bit 0 description. 25 p2_25ci clear gpio port interrupts for p2[25]. see bit 0 description. 26 p2_26ci clear gpio port interrupts for p2[26]. see bit 0 description. 27 p2_27ci clear gpio port interrupts for p2[27]. see bit 0 description. 28 p2_28ci clear gpio port interrupts for p2[28]. see bit 0 description. 29 p2_29ci clear gpio port interrupts for p2[29]. see bit 0 description. 30 p2_30ci clear gpio port interrupts for p2[30]. see bit 0 description. 31 p2_31ci clear gpio port interrupts for p2[31]. see bit 0 description.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 158 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.10 gpio interrupt enable for port 2 rising edge each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin. which pins are available depends on the part number and package combination. see the specific device data sheet for details. table 109. gpio interrupt enable for port 2 rising edge (enr2 - 0x4002 80b0) bit description bit symbol description reset value 0 p2_0er enable rising edge interrupt for p2[0]. 0 = disable rising edge interrupt. 1 = enable rising edge interrupt. 0 1 p2_1er enable rising edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2er enable rising edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3er enable rising edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4er enable rising edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5er enable rising edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6er enable rising edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7er enable rising edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8er enable rising edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9er enable rising edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10er enable rising edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11er enable rising edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12er enable rising edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13er enable rising edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14er enable rising edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15er enable rising edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16er enable rising edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17er enable rising edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18er enable rising edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19er enable rising edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20er enable rising edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21er enable rising edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22er enable rising edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23er enable rising edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24er enable rising edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25er enable rising edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26er enable rising edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27er enable rising edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28er enable rising edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29er enable rising edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30er enable rising edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31er enable rising edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 159 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.5.2.11 gpio interrupt enable for port 2 falling edge each bit in these read-wri te registers enables the fa lling edge interrupt for the corresponding gpio port 2 pin. table 110. gpio interrupt enable for port 2 falling edge (enf2 - 0x4002 80b4) bit description bit symbol description reset value 0 p2_0ef enable falling edge interrupt for p2[0]. 0 = disable falling edge interrupt. 1 = enable falling edge interrupt. 0 1 p2_1ef enable falling edge interrupt for p2[1]. see bit 0 description. 0 2 p2_2ef enable falling edge interrupt for p2[2]. see bit 0 description. 0 3 p2_3ef enable falling edge interrupt for p2[3]. see bit 0 description. 0 4 p2_4ef enable falling edge interrupt for p2[4]. see bit 0 description. 0 5 p2_5ef enable falling edge interrupt for p2[5]. see bit 0 description. 0 6 p2_6ef enable falling edge interrupt for p2[6]. see bit 0 description. 0 7 p2_7ef enable falling edge interrupt for p2[7]. see bit 0 description. 0 8 p2_8ef enable falling edge interrupt for p2[8]. see bit 0 description. 0 9 p2_9ef enable falling edge interrupt for p2[9]. see bit 0 description. 0 10 p2_10ef enable falling edge interrupt for p2[10]. see bit 0 description. 0 11 p2_11ef enable falling edge interrupt for p2[11]. see bit 0 description. 0 12 p2_12ef enable falling edge interrupt for p2[12]. see bit 0 description. 0 13 p2_13ef enable falling edge interrupt for p2[13]. see bit 0 description. 0 14 p2_14ef enable falling edge interrupt for p2[14]. see bit 0 description. 0 15 p2_15ef enable falling edge interrupt for p2[15]. see bit 0 description. 0 16 p2_16ef enable falling edge interrupt for p2[16]. see bit 0 description. 0 17 p2_17ef enable falling edge interrupt for p2[17]. see bit 0 description. 0 18 p2_18ef enable falling edge interrupt for p2[18]. see bit 0 description. 0 19 p2_19ef enable falling edge interrupt for p2[19]. see bit 0 description. 0 20 p2_20ef enable falling edge interrupt for p2[20]. see bit 0 description. 0 21 p2_21ef enable falling edge interrupt for p2[21]. see bit 0 description. 0 22 p2_22ef enable falling edge interrupt for p2[22]. see bit 0 description. 0 23 p2_23ef enable falling edge interrupt for p2[23]. see bit 0 description. 0 24 p2_24ef enable falling edge interrupt for p2[24]. see bit 0 description. 0 25 p2_25ef enable falling edge interrupt for p2[25]. see bit 0 description. 0 26 p2_26ef enable falling edge interrupt for p2[26]. see bit 0 description. 0 27 p2_27ef enable falling edge interrupt for p2[27]. see bit 0 description. 0 28 p2_28ef enable falling edge interrupt for p2[28]. see bit 0 description. 0 29 p2_29ef enable falling edge interrupt for p2[29]. see bit 0 description. 0 30 p2_30ef enable falling edge interrupt for p2[30]. see bit 0 description. 0 31 p2_31ef enable falling edge interrupt for p2[31]. see bit 0 description. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 160 of 942 nxp semiconductors UM10562 chapter 8: lpc408x/407x gpio 8.6 gpio usage notes 8.6.1 example: an instantaneous out put of 0s and 1s on a gpio port solution 1: using 32-bit (word) access ible fast gpio registers fio0mask = 0xffff00ff ; fio0pin = 0x0000a500; solution 2: using 16-bit (half-word) accessible fast gpio registers fio0maskl = 0x00ff; fio0pinl = 0xa500; solution 3: using 8-bit (byte) accessible fast gpio registers fio0pin1 = 0xa5; 8.6.2 writing to fioset/fioclr vs. fiopin writing to the fioset/fioclr registers allow a program to easily change a port?s output pin(s) to both high and low levels at the same time. when fioset or fioclr are used, only pin/bit(s) written with 1 will be change d, while those writte n as 0 will remain unaffected. writing to the fiopin register enables instantaneous output of a desired value on the parallel gpio. data written to the fiopin regist er will affect all pins configured as outputs on that port: zeroes in the value will produce low level pin outputs and ones in the value will produce high level pin outputs. a subset of a port?s pins may be changed by using the fiomask register to define which pins are affected. fiomask is set up to contai n zeroes in bits corresponding to pins that will be changed, and ones for all others. solution 2 from section 8.6.1 above illustrates output of 0xa5 on port0 pins 15 to 8 while preserving all other port0 output pins as they were before.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 161 of 942 9.1 how to read this chapter this chapter describes the external memory controller for devices that support external memory. emc configurations vary with diff erent packages for devices that support external memory, see table 111 . [1] in addition to the registers that are common to all emc operations: emccontrol and emcconfig. UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) rev. 1 ? 13 september 2012 user manual table 111. emc configuration device package data bus widths supported pins available dynamic memory configuration registers [1] [2] static memory configuration registers [1] [3] external memory connections 144-pin 8-bit emc_a[15:0] emc_d[7:0] emc_oe emc_we emc_cs1:0 emcstaticconfig1/0 emcstaticwaitwen1/0 emcstaticwaitoen1/0 emcstaticwaitrd1/0 emcstaticwaitpage1/0 emcstaticwaitwr1/0 emcstaticwaitturn1/0 section 9.14.3 180-pin 16-bit, 8-bit emc_a[19:0] emc_d[15:0] emc_oe emc_we emc_bls1:0 emc_cs1:0 emc_dycs1:0 emc_cas emc_ras emc_clk1:0 emc_cke1:0 emc_dqm1:0 emcdynamicconfig1/0 emcdynamicrascas1/0 emcstaticconfig1/0 emcstaticwaitwen1/0 emcstaticwaitoen1/0 emcstaticwaitrd1/0 emcstaticwaitpage1/0 emcstaticwaitwr1/0 emcstaticwaitturn1/0 section 9.14.2 section 9.14.3 208-pin 32-bit, 16-bit, 8-bit emc_a[25:0] emc_d[31:0] emc_oe emc_we emc_bls3:0 emc_cs3:0 emc_dycs3:0 emc_cas emc_ras emc_clk1:0 emc_cke3:0 emc_dqm3:0 emcdynamicconfig3/2/1/0 emcdynamicrascas3/2/1/0 emcstaticconfig3/2/1/0 emcstaticwaitwen3/2/1/0 emcstaticwaitoen3/2/1/0 emcstaticwaitrd3/2/1/0 emcstaticwaitpage3/2/1/0 emcstaticwaitwr3/2/1/0 emcstaticwaitturn3/2/1/0 section 9.14.1 section 9.14.2 section 9.14.3
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 162 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) [2] in addition to the registers that are common to a ll emc dynamic chip selects: emcdynamiccontrol, emcdynamicrefresh, emcdynamicreadconf ig, emcdynamicrp, emcdynamicras, emcdynamicsrex, emcdynamicapr, emcdynam icdal, emcdynamicwr, emcdynamicrc, emcdynamicrfc, emcdynamicxsr, emcdynamicrrd, and emcdynamicmrd [3] in addition to the emcstaticextendedwait register which applies to all static chip selects. 9.2 basic configuration the emc is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcemc. remark: the emc is enabled on reset (pcemc = 1). on por and warm reset, the emc is enabled as well, see table 115 and table 118 . 2. clock: the emc clock can be the same as the cpu clock (the default), or half that. the lower rate is intended to be used primarily when the cpu is running faster than the external bus can support. clock selection for the emc is described in section 3.3.3.1 . 3. pins: select emc pins and pin modes through the relevant iocon registers ( section 7.4.1 ). 4. configuration: see ta b l e 11 5 to table 118 . also see additional emc configurations in section 3.3.7.1 ? system controls and status register ? . in particular make sure that the address shift mode is configured correctly for the application hardware. 5. mpu: default memory space permissions for the cpu do not allow program execution from the address range that includes the dynamic memory chip selects. these permissions can be changed by programming the mpu (see the arm cortex-m4 user guide refe rred to in section 40.1 for details of mpu operation. 6. to set the emc delay clock see the emc del ay clock register in the system control block (see section 3.3.6.1 ). 7. to calibrate the emc clock, see section 3.3.6.2 . 9.3 introduction the external memory controller (emc) is an arm primecell? multiport memory controller peripheral offering support for as ynchronous static memory devices such as ram, rom and flash, as well as dynamic memories such as single data rate sdram. the emc is an advanced microcontroller bus ar chitecture (amba) compliant peripheral.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 163 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.4 features ? static chip selects each support up to 64 mb of data. by enabling the address shift mode, static chip select 0 can support up to 256 mb, and static chip select 1 can support up to 128 mb (see scs register bit 0 ( section 3.3.7.1 ) ? dynamic chip selects each supp ort up to 256 mb of data. ? dynamic memory interface support in cluding single data rate sdram. ? asynchronous static memory device support including ram, rom, and flash, with or without asynchronous page mode. ? low transaction latency. ? read and write buffers to reduce la tency and to improve performance. ? 8-bit, 16-bit, and 32-bit wide static memory support. ? 16-bit and 32-bit wide chip select sdram memory support. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable and write enable delays ? extended wait ? four chip selects for synchro nous memory and four chip selects for static memory devices. ? power-saving modes dynamically co ntrol cke and clkout to sdrams. ? dynamic memory self-refresh mode controlled by software. ? controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts. that is typical 512 mbit, 256 mbit, and 128 mbit parts, with 4, 8, 16, or 32 data bits per device. ? separate reset domains allow the for auto-r efresh through a chip reset if desired. ? programmable delay elements allow fine-tuning emc timing. note: synchronous static memory devices ( synchronous burst mode) are not supported.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 164 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5 emc functional description figure 16 shows a block diagram of the emc. the functions of the emc blocks are described in the following sections: ? ahb slave register interface. ? ahb slave memory interfaces. ? data buffers. ? memory controller state machine. ? pad interface. note: for 32 bit wide chip selects data is tr ansferred to and from dynamic memory in sdram bursts of four. for 16 bit wide chip selects sdram bursts of eight are used. fig 16. emc block diagram programmable delay pad interface ahb bus 120524 emc_d[31:0] emc_a[25:0] emc_we emc_oe emc_bls3:0 emc_cke3:0 emc_dqm3:0 programmable delay memory controller state machine data buffers (4 x 16 word) shared signals static memory signals dynamic memory signals emc_cs3:0 emc_dycs3:0 emc_cas emc_ras fbclkin ahb slave memory interface ahb slave register interface programmable delay emcdlyctl[4:0] emcdlyctl[28:24] emcdlyctl[20:16] emcdlyctl[12:8] programmable delay emcclkdelay emcclk hclk emc_clkout0 emc_clkout1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 165 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5.1 ahb slave register interface the ahb slave register interface block enables the registers of the emc to be programmed. this module also contains most of the registers and performs the majority of the register address decoding. to eliminate the possibility of endianness prob lems, all data transf ers to and from the registers of the emc must be 32 bits wide. note: if an access is attempted with a size other than a word (32 bits), it causes an error response to the ahb bus and the transfer is terminated. 9.5.2 ahb slave memory interface the ahb slave memory interface allo ws access to external memories. 9.5.2.1 memory transaction endianness the endianness of the data transfers to and fr om the external memories is determined by the endian mode (n) bit in the emcconfig register. note: the memory controller must be idle (see the busy field of the emcstatus register) before endianness is changed, so that the data is transferred correctly. 9.5.2.2 memory transaction size memory transactions can be 8, 16, or 32 bits wide. any access attempted with a size greater than a word (32 bits) causes an e rror response to the ahb bus and the transfer is terminated. 9.5.2.3 write protected memory areas write transactions to write-protected memory areas generate an error response to the ahb bus and the transfer is terminated. 9.5.3 pad interface the pad interface block provides the interf ace to the pads. the pad interface uses a feedback clock, fbclkin, from the clkout0 output of the emc to resynchronize sdram read data from the off-chip to on-chip domains. 9.5.4 data buffers the ahb interface reads and writes via buffers to improve memory bandwidth and reduce transaction latency. the emc contains four 16-word buffers. the buffers can be used as read buffers, write buffers, or a combination of both. the buffers are allocated automatically. the buffers must be disabled during sdram initialization. the buffers must be enabled during normal operation. the buffers can be enabled or disabled fo r static memory using the emcstaticconfig registers. 9.5.4.1 write buffers write buffers are used to:
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 166 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) ? merge write transactions so that the number of external transactions are minimized. buffer data until the emc can complete the write transaction, improving ahb write latency. convert all dynamic memory write transactions into quadword bursts on the external memory interface. this enhances tran sfer efficiency for dynamic memory. ? reduce external memory traffic. this improves memory bandwidth and reduces power consumption. write buffer operation: ? if the buffers are enabled, an ahb write operation writes into the least recently used (lru) buffer, if empty. if the lru buffer is not empty, the contents of the buffer are flushed to memory to make space for the ahb write data. ? if a buffer contains write data it is marked as dirty, and its contents are written to memory before the buffer can be reallocated. the write buffers are flushed whenever: ? the memory controller state machine is not busy performing accesses to external memory. the memory controller state machine is not busy performing accesses to external memory, and an ahb interface is writing to a different buffer. note: for dynamic memory, the sm allest buffer flush is a quadword of data. for static memory, the smallest buffer flush is a byte of data. 9.5.4.2 read buffers read buffers are used to: ? buffer read requests from memory. future re ad requests that hit the buffer read the data from the buffer rather than memory, reducing transaction latency. convert all read transactions into quadword bursts on the external memory interface. this enhances transfer efficiency for dynamic memory. ? reduce external memory traffic. this improves memory bandwidth and reduces power consumption. read buffer operation: ? if the buffers are enabled and the read data is contained in one of the buffers, the read data is provided directly from the buffer. ? if the read data is not contained in a buffer, the lru buffer is selected. if the buffer is dirty (contains write data), the write data is flushed to memory. when an empty buffer is available the read command is posted to the memory. a buffer filled by performing a r ead from memory is marked as not-dirty (not containing write data) and its contents are not flushed back to the memory controller unless a subsequent ahb transfer performs a write that hits the buffer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 167 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.5.5 memory controller state machine the memory controller state machine comprises a static memory controller and a dynamic memory controller. 9.5.6 timing control with pr ogrammable delay elements programmable delay elements are provided to allow fine-tuning the timing of various aspects of emc operation in connection with sdram memory. ? for the clock delayed operating mode, separate programmable delays are provided for each potential clock output, clkout0 and clkout1. ? for the command delayed operating mode, a programmable delay is provided to control delay of all command outputs. ? for both operating modes, a programmable delay is provided to control the time at which input data from sdram memory is sampled. the locations of the programmable delays are shown in the emc overall block diagram ( figure 16 ). see descriptions of the emcdlyctl and emccal registers for more information.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 168 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.6 low-power operation in many systems, the contents of the me mory system have to be maintained during low-power sleep modes. the emc provides a mechanism to place the dynamic memories into self-refresh mode. self-refresh mode can be entered by soft ware by setting the srefreq bit in the emcdynamiccontrol register and polling the srefack bit in the emcstatus register. any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the ahb bus. clearing the srefreq bit in the emcdynamiccontrol register returns the memory to normal operation. see the memory data sheet for refresh requirements. note: the static memory can be accessed as normal when the sdram memory is in self-refresh mode. 9.6.1 low-power sdra m deep-sleep mode the emc supports jedec low-power sdram deep-sleep mode. deep-sleep mode can be entered by setting the deep-sleep mode (dp) bit, the dynamic memory clock enable bit (ce), and the dynamic clock control bit (cs) in the emcdynamiccontrol register. the device is then put into a low-power mode where the device is powered down and no longer refreshed. all data in the memory is lost. 9.6.2 low-power sdram partial array refresh the emc supports jedec low-power sdram part ial array refresh. partial array refresh can be programmed by initializing the sdram memory device appropriately. when the memory device is put into self-refresh mode only the memory banks specified are refreshed. the memory banks that are not refreshed lose their data contents.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 169 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.7 memory bank select eight independently-configurable memory chip selects are supported: ? pins emc_cs3 to emc_cs0 are used to select static memory devices. ? pins emc_dycs3 to emc_dycs0 are used to select dynamic memory devices. static memory chip select ranges are each 64 megabytes in size, while dynamic memory chip selects cover a range of 256 megabytes each. table 112 shows the address ranges of the chip selects. 9.8 emc reset the emc receives two reset signals. one is power-on reset (por), asserted when chip power is applied, and when a brown-out condition is detected (see the system control block chapter for details of br own-out detect). the other reset is from the external reset pin and the watchdog timer. a configuration bit in the scs register, called emc_reset_disable, allows control of how the emc is reset (see section 3.3.7.1 ? system controls and status register ? ). the default configuration (emc_reset_disabl e = 0) is that both emc resets are asserted when any type of reset event occurs. in this mode, all registers and functions of the emc are initialized upon any reset condition. if emc_reset_disable is set to 1, many portio ns of the emc are only reset by a power-on or brown-out event, in order to allow the emc to retain its state through a warm reset (external reset or watchdog reset). if the emc is configured correctly, auto-refresh can be maintained through a warm reset. table 112. memory bank selection chip select pin address range memory type size of range emc_cs0 0x8000 0000 - 0x83ff ffff static 64 mb emc_ cs1 0x9000 0000 - 0x93ff ffff static 64 mb emc_ cs2 0x9800 0000 - 0x9bff ffff static 64 mb emc_ cs3 0x9c00 0000 - 0x9fff ffff static 64 mb emc_ dycs0 0xa000 0000 - 0xafff ffff dynamic 256 mb emc_ dycs1 0xb000 0000 - 0xbfff ffff dynamic 256 mb emc_ dycs2 0xc000 0000 - 0xcfff ffff dynamic 256 mb emc_ dycs3 0xd000 0000 - 0xdfff ffff dynamic 256 mb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 170 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.9 address shift mode the emc supports an optional address shift mode for static memories that can simplify board design and potentially increase external memory addressing range in some cases. the latter cases are described in footnotes of ta b l e 3 ? memory usage and details ? in the memory map chapter of this manual. address shift mode is controlled by a configuration bit in the scs register, called emc shift control (see section 3.3.7.1 ? system controls and status register ? ). when the address shift mode is not activated (the emc shift control bit in the scs register = 1), static memory addresses are outp ut as byte addresses. this means that for memories wider than a byte, one or two addr ess lines are not used, and that address connections to memory devices must be shifted in the board design. for example, if a 32-bit wide memory system is connected, the lowest line address of the memory device(s) would be connected to emc address line 2, skipping bits 0 and 1. when the address shift mode is activated (the emc shift control bit in the scs register = 0), static memory addresses are shifted to match the lowest address bit needed for bus width. in this case, the lowest address lin e of the memory device(s) is always to emc address line 0. 9.10 memory mapped i/o and burst disable by default, the emc uses buffering to obtain better external memory access performance. however, in the case of memory mapped i/o devices, the read-ahead operations that occur due to the buffering can cause issues with some such devices. this could be from a change of status in one register caused by reading another register, or could simply cause an unplanned read of a data fifo when another register in the device is read intentionally. to prevent this issue, the use of buffering to read ahead of actual cpu memory read requests can be disabled. the configuration bit that controls this function is called emc burst control, and is found in the scs register (see section 3.3.7.1 ? system controls and status register ? ).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 171 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x extern al memory controller (emc) 9.11 using the emc with sdram 9.11.1 mode register setup when using the emc with sdram, the sdram devices must be configured appropriately for the emc. this includes setting up t he sdrams for a 128-bit sequential burst. the burst configuration is done through a mode register in the sdram memory. figure 17 shows the layout for a jedec standard sdram mode register. fig 17. sdram mode register a10 a11 a9a8a7a6a5a4a3a2a1a0 burst length m2 m1 m0 m3=0 m3=1 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequenctial 1 interleaved cas latency m6 m5 m4 cas latency 000 reserved 001 reserved 010 2 011 3 100 reserved 101 reserved 110 reserved 111 reserved operating mode m8 m7 m6-m0 mode 0 0 defined standard operation - - - others reserved write burst mode m9 mode 0 programmed burst length 1 single location access reserved - address bus 120515 bl cl bt opmode - mode register wb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 172 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) the mode register is loaded by first se nding the ?set mode? command to the sdram using the dynamiccontrol register?s sdra m initialization bits to send a mode command, and then reading the sdram at an address that is partially formed from the new mode register value. the actual value loaded into the mode register is taken by the sdram from the address lines of the emc wh ile they are sending the row address during the read. example to determine the address to read from to l oad the mode register, the portion of the emc address bits that map to the ro w address must be id entified. in this ex ample, we will use: ? a single 8m by 16-bit external sdram chip in row, bank, column mode on cs0 ? cas latency of 2 since the emc uses bursts of 8 for a 16-bit external memory, we need to load the mode register with a burst length of 8 (8 x 16 bits memory width = 128 bits). the mode register configuration needed is 0x023. to load the mode register, we need to do a read from the address constructed as follows: information needed: ? base address for dynamic ch ip select 0, found in ta b l e 3 . for this device, the address is 0xa000 0000. ? mode register value, based on information from both the sdram data sheet, as in figure 17 , and the emc. in this example, the value will be 0x23. this represents a programmed burst length, cas latency of 2, sequential burst type, and a burst length of 8, as described in section 9.5 . ? bank bits and column bits, look up in table 134 . in this example, it is 4 banks and 9 column bits. ? bus width, defined in this example to be 16 bits. the mode register value calculation is: base address + (mode register value << (bank bits + column bits + bus width/16) the shift operation aligns the mode register value with the row address bits. in this example: 0xa000 0000 + (0x23 << (2 + 9 + 1)) = 0xa000 0000 + 0x23000 = 0xa002 3000
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 173 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.12 pin description table 113 shows the interface and control signal pins for the emc. table 113. pad interface and control signal descriptions name type value on por reset value during self-refresh description emc_a[23:0] output 0 depends on static memory accesses external memory address output. used for both static and sdram devices. sdram memories use only bits [14:0]. emc_d[31:0] input/ output data outputs = 0 depends on static memory accesses external memory data lines. these are inputs when data is read from external memory and outputs when data is written to external memory. emc_oe output 1 depends on static memory accesses low active output enable for static memory devices. emc_bls3:0 output 0xf depends on static memory accesses low active byte lane selects. used for static memory devices. emc_we output 1 depends on static memory accesses low active write enable. used for sdram and static memories. emc_cs3:0 output 0xf depends on static memory accesses static memory chip selects. default active low. used for static memory devices. emc_dycs3:0 output 0xf 0xf sdram chip selects. used for sdram devices. emc_cas output 1 1 column address strobe. used for sdram devices. emc_ras output 1 1 row address strobe. used for sdram devices. emc_clk1:0 output follows cclk follows cclk sdram clocks. used for sdram devices. emc_cke3:0 output 0xf 0x0 sdram clock enabl es. used for sdram devices. one is allocated for each chip select. emc_dqm3:0 output 0xf 0xf data mask output to sdrams. used for sdram devices and static memories.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 174 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13 register description this chapter describes the emc register s and provides details required when programming the microcontroller. . the emc clock configuration and clock calibration registers are located in the system control block. see section 3.3.6.1 and section 3.3.6.2 . table 114. register overview: emc (base address 0x2009 0000) register name access address offset description warm reset value [1] por reset value [1] table control r/w 0x000 controls operation of the memory controller. 0x1 0x3 115 status ro 0x004 provides emc status information. - 0x5 116 config r/w 0x008 configures operation of the memory controller - 0x0 117 dynamiccontrol r/w 0x020 controls dynamic memory operation. - 0x006 118 dynamicrefresh r/w 0x024 configures dynamic memory refresh. - 0x0 119 dynamicreadconfig r/w 0x028 configures dynamic memory read strategy. - 0x0 120 dynamicrp r/w 0x030 precharge command period. - 0x0f 121 dynamicras r/w 0x034 active to precharge command period. - 0xf 122 dynamicsrex r/w 0x038 self-refresh exit time. - 0xf 123 dynamicapr r/w 0x03c last-data-out to active command time. - 0xf 124 dynamicdal r/w 0x040 data-in to active command time. - 0xf 125 dynamicwr r/w 0x044 write recovery time. - 0xf 126 dynamicrc r/w 0x048 selects the active to active command period. - 0x1f 127 dynamicrfc r/w 0x04c selects the auto-refresh period. - 0x1f 128 dynamicxsr r/w 0x050 time for exit self-refresh to active command. - 0x1f 129 dynamicrrd r/w 0x054 latency for active bank a to active bank b. - 0xf 130 dynamicmrd r/w 0x058 time for load mode register to active command. -0xf 131 staticextendedwait r/w 0x080 time for long static memory read and write transfers. -0x0 132 dynamicconfig0 r/w 0x100 configuration information for emc_dycs0 .-0x0 133 dynamicrascas0 r/w 0x104 ras and cas latencies for emc_dycs0 . - 0x303 135 dynamicconfig1 r/w 0x120 configuration information for emc_dycs1 .-0x0 133 dynamicrascas1 r/w 0x124 ras and cas latencies for emc_dycs1 . - 0x303 135 dynamicconfig2 r/w 0x140 configuration information for emc_dycs2 .-0x0 133 dynamicrascas2 r/w 0x144 ras and cas latencies for emc_dycs2 . - 0x303 135 dynamicconfig3 r/w 0x160 configuration information for emc_dycs3 .-0x0 133 dynamicrascas3 r/w 0x164 ras and cas latencies for emc_dycs3 . - 0x303 135 staticconfig0 r/w 0x200 configuration for emc_cs0 .- 0 x 0 136 staticwaitwen0 r/w 0x204 delay from emc_cs0 to write enable. - 0x0 137 staticwaitoen0 r/w 0x208 delay from emc_cs0 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd0 r/w 0x20c delay from emc_cs0 to a read access. - 0x1f 139
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 175 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. staticwaitpage0 r/w 0x210 delay for asynchronous page mode sequential accesses for emc_cs0 . -0x1f 140 staticwaitwr0 r/w 0x214 delay from emc_cs0 to a write access. - 0x1f 141 staticwaitturn0 r/w 0x218 number of bus turnaround cycles emc_cs0. -0xf 142 staticconfig1 r/w 0x220 memory configuration for emc_cs1 .-0 x 0 136 staticwaitwen1 r/w 0x224 delay from emc_cs1 to write enable. - 0x0 137 staticwaitoen1 r/w 0x228 delay from emc_cs1 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd1 r/w 0x22c delay from emc_cs1 to a read access. - 0x1f 139 staticwaitpage1 r/w 0x230 delay for asynchronous page mode sequential accesses for emc_cs1 . -0x1f 140 staticwaitwr1 r/w 0x234 delay from emc_cs1 to a write access. - 0x1f 141 staticwaitturn1 r/w 0x238 bus turnaround cycles for emc_cs1 .-0 x f 142 staticconfig2 r/w 0x240 memory configuration for emc_cs2 .-0 x 0 136 staticwaitwen2 r/w 0x244 delay from emc_cs2 to write enable. - 0x0 137 staticwaitoen2 r/w 0x248 delay from emc_cs2 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd2 r/w 0x24c delay from emc_cs2 to a read access. - 0x1f 139 staticwaitpage2 r/w 0x250 delay for asynchronous page mode sequential accesses for emc_cs2 . -0x1f 140 staticwaitwr2 r/w 0x254 delay from emc_cs2 to a write access. - 0x1f 141 emcstaticwaitturn2 r/w 0x258 bus turnaround cycles for emc_cs2 .-0 x f 142 staticconfig3 r/w 0x260 memory configuration for emc_cs3 .-0 x 0 136 staticwaitwen3 r/w 0x264 delay from emc_cs3 to write enable. - 0x0 137 staticwaitoen3 r/w 0x268 delay from emc_cs3 or address change, whichever is later, to output enable. -0x0 138 staticwaitrd3 r/w 0x26c delay from emc_cs3 to a read access. - 0x1f 139 staticwaitpage3 r/w 0x270 delay for asynchronous page mode sequential accesses for emc_cs3 . -0x1f 140 staticwaitwr3 r/w 0x274 delay from emc_cs3 to a write access. - 0x1f 141 staticwaitturn3 r/w 0x278 bus turnaround cycles for emc_cs3 .-0 x f 142 table 114. register overview: emc (base address 0x2009 0000) ?continued register name access address offset description warm reset value [1] por reset value [1] table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 176 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.1 emc control register the emccontrol register is a read/write register that controls operation of the memory controller. the control bits can be altered during normal operation. table 115 shows the bit assignments for the emccontrol register. [1] the external memory cannot be accessed in low-power or disabled state. if a memo ry access is performed an ahb error response is generated. the emc register s can be programmed in low-power and/or disabled state. table 115. emc control register (control - address 0x2009 c000) bit description bit symbol value description reset value 0 e emc enable. indicates if the emc is enabled or disabled: 1 0 disabled 1 enabled (por and warm reset value). disabling the emc reduces power consumption. when the memory controller is disabled the memory is not refreshed. the memory controller is enabled by setting the enable bit, or by reset. this bit must only be modified when the emc is in idle state. [1] 1 m address mirror. indicates normal or reset memory map: 1 0 normal memory map. 1 reset memory map. static memory emc_cs1 is mirrored onto emc_cs0 and emc_dycs0 (por reset value). on por, emc_cs1 is mirrored to both emc_cs0 and emc_dycs0 memory areas. clearing the m bit enables emc_cs0 and emc_dycs0 memory to be accessed. 2 l low-power mode. indicates normal, or low-power mode: 0 0 normal mode (warm reset value). 1 low-power mode. entering low-power mode reduces memory controller power consumption. dynamic memory is refreshed as necessary. the memo ry controller returns to normal functional mode by clearing the low-power mode bit (l), or by por. this bit must only be modified when the emc is in idle state. [1] 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 177 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.2 emc status register the read-only emcstatus register provides emc status information. 9.13.3 emc configuration register the emcconfig register configures the ope ration of the memory controller. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this register is accessed with one wait state. table 116. emc status register (status - address 0x2009 c008) bit description bit symbol value description reset value 0 b busy. this bit is used to ensure that th e memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not. 1 0 emc is idle (warm reset value). 1 emc is busy performing memory transacti ons, commands, auto-ref resh cycles, or is in self-refresh mode (por reset value). 1 s write buffer status.this bit enables the emc to enter low-power mode or disabled mode cleanly. 0 0 write buffers empt y (por reset value) 1 write buffers contain data. 2 sa self-refresh acknowledge. this bit indicates the operating mode of the emc. 1 0 normal mode 1 self-refresh mode (por reset value). 31:3 - reserved. the value read from a reserved bit is not defined. na table 117. emc configuration register (config - address 0x2009 c008) bit description bit symbol value description reset value 0 em endian mode. on power-on reset, the value of the endian bit is 0. all data must be flushed in the emc before switching between little-endian and big-endian modes. 0 0 little-endian mode (por reset value). 1 big-endian mode. 7:1 - reserved. read value is undefined, only zero should be written. na 8 clkr cclk: clkout ratio. this bit must contain 0 for proper operation of the emc. 0 0 1:1 (por reset value) 1 1:2 (this option is not available) 31:9 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 178 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.4 dynamic memory control register the emcdynamiccontrol register controls dy namic memory operation. the control bits can be altered during normal operation. [1] clock enable must be high during sdram initialization. [2] the memory controller exits from power-on reset with the self-refresh bit high. to enter normal functional mode set this bit low. [3] disabling clkout can be performed if there are no sdram memory transactions. when enabled this bit can be used in conjunction wi th the dynamic memory clock control (cs) field. remark: deep-sleep mode can be entered by sett ing the deep-sleep mode (dp) bit, the dynamic memory clock enable bit (ce), and the dynamic clock control bit (cs) to one. the device is then put into a low-power mode where the device is powered down and no longer refreshed. all data in the memory is lost. table 118. dynamic control register (dynamiccontrol - address 0x2009 c020) bit description bit symbol value description reset value 0 ce dynamic memory clock enable. 0 0 clock enable of idle devices are deasserted to save power (por reset value). 1 all clock enables are driven high continuously. [1] 1 cs dynamic memory clock control. when clock control is low the output clock clkout is stopped when there are no sdram transactions. the clock is also stopped during self-refresh mode. 1 0 clkout stops when all sdrams are idle and during self-refresh mode. 1 clkout runs continuously (por reset value). 2 sr self-refresh request, emcsrefreq. by writing 1 to this bit self-refresh can be entered under software control. writing 0 to this bit returns the emc to normal mode. the self-refresh acknowledge bit in the status register must be polled to discover the current operating mode of the emc. [2] 1 0 normal mode. 1 enter self-refresh mo de (por reset value). 4:3 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 5 mmc memory clock control. 0 0 clkout enabled (por reset value). 1 clkout disabled. [3] 6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 8:7 i sdram initialization. 00 0x0 issue sdram normal operation command (por reset value). 0x1 issue sdram mode command. 0x2 issue sdram pall (precharge all) command. 0x3 issue sdram nop (no operation) command) 13:9 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 31:14 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 179 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.5 dynamic memory re fresh timer register the emcdynamicrefresh register configures dynamic memory operation. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. however, these control bits can, if necessary, be altered during normal operation. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. . for example, for the refresh period of 16 s, and a cclk frequency of 50 mhz, the following value must be prog rammed into this register: (16 x 10-6 x 50 x 106) / 16 = 50 or 0x32 if auto-refresh through warm reset is requested (by setting the emc_reset_disable bit), the timing of auto-refresh must be adjusted to allow a sufficient refresh rate when the clock rate is reduced during the wake-up peri od of a reset cycle. during this period, the emc (and all other portions of the device that are being clocked) run from the irc oscillator at 12 mhz. so, 12 mhz must be considered th e cclk rate for refresh calculations if auto-refresh through warm reset is requested. note: the refresh cycles are evenly distributed. however, there might be slight variations when the auto-refresh command is issued depending on the status of the memory controller. table 119. dynamic memory refresh timer register (dynamicrefresh - address 0x2009 c024) bit description bit symbol description reset value 10:0 refresh refresh timer. indicates the mult iple of 16 cclks between sdram refresh cycles. 0x0 = refresh disabled (por reset value). 0x1 - 0x7ff = n x16 = 16n cclks between sdram refresh cycles. for example: 0x1 = 1 x 16 = 16 cclks between sdram refresh cycles. 0x8 = 8 x 16 = 128 cclks between sdram refresh cycles 0 31:11 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 180 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.6 dynamic memory read configuration register the emcdynamicreadconfig register config ures the dynamic memory read strategy. this register must only be modified during s ystem initialization. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects, so a single read strategy must be used for all dynamic memories. table 120 shows the bit assignments for the emcdynamicreadconfig register. when using command delayed strategy, programmable delays can be used to adjust the timing of the control signals output by the emc. see section 9.5.6 and section 3.3.6.1 . 9.13.7 dynamic memory precharge command period register the emcdynamictrp register enables you to program the precharge command period, trp. this register must only be modified durin g system initialization. this value is normally found in sdram data sheets as trp. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 120. dynamic memory read configuration regi ster (dynamicreadconfig - address 0x2009 c028) bit description bit symbol value description reset value 1:0 rd read data strategy 0x0 0x0 clock out delayed strategy, using clkout (command not delayed, clock out delayed). por reset value. 0x1 command delayed strategy, using emcclkdelay (command delayed, clock out not delayed). 0x2 command delayed strategy plus one clock cycle, using emcclkdelay (command delayed, clock out not delayed). 0x3 command delayed strategy plus two clock cycles, using emcclkdelay (command delayed, clock out not delayed). 31:2 - reserved. read value is undefined, only zero should be written. na table 121. dynamic memory precharge command period register (dynamicrp - address 0x2009 c030) bit description bit symbol description reset value 3:0 trp precharge command period. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 181 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.8 dynamic memory active to pr echarge command pe riod register the emcdynamictras register enables you to program the active to precharge command period, tras. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tras. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.9 dynamic memory self-ref resh exit time register the emcdynamictsrex register enables you to program the self-refresh exit time, tsrex. it is recommended that this register is modified du ring system initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tsrex, for devices without this parameter you use the same value as txsr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 122. dynamic memory active to precha rge command period register (dynamicras - address 0x2009 c034) bit description bit symbol description reset value 3:0 tras active to precharge command period. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 123. dynamic memory self refresh exit time register (dynamicsrex - address 0x2009 c038) bit description bit symbol description reset value 3:0 tsrex self-refresh exit time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 182 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.10 dynamic memory last data out to active time register the emcdynamictapr register enables you to program the last-data-out to active command time, tapr. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tapr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.11 dynamic memory data-in to active command time register the emcdynamictdal register enables you to program the data-in to active command time, tdal. it is recommended that this register is modified during syst em initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tdal, or tapw. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 124. dynamic memory last data out to active time register (dynamicapr - address 0x2009 c03c) bit description bit symbol description reset value 3:0 tapr last-data-out to active command time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 125. dynamic memory data in to active command time register (dynamicdal - address 0x2009 c040) bit description bit symbol description reset value 3:0 tdal data-in to active command. 0x0 - 0xe = n clock cycles. the delay is in cclk cycles. 0xf = 15 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 183 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.12 dynamic memory writ e recovery time register the emcdynamictwr register enables you to pr ogram the write recove ry time, twr. it is recommended that this register is modified during system in itialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabl ed mode. this value is normally found in sdram data sheets as twr, tdpl, trwl, or trdl. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.13 dynamic memory active to active command period register the emcdynamictrc register enables you to program the active to active command period, trc. it is recommended that this register is modified during s ystem initialization, or when there are no current or outstanding tr ansactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trc. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 126. dynamic memory write recovery time register (dynamicwr - address 0x2009 c044) bit description bit symbol description reset value 3:0 twr write recovery time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 127. dynamic memory active to active command period re gister (dynamicrc - address 0x2009 c048) bit description bit symbol description reset value 4:0 trc active to active command period. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 184 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.14 dynamic memory auto -refresh period register the emcdynamictrfc register enables you to program the auto-refresh period, and auto-refresh to active command period, trfc. it is recommend ed that this register is modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trfc, or sometimes as trc. this regi ster is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.15 dynamic memory exit self-refresh register the emcdynamictxsr register enables you to program the exit self-refresh to active command time, txsr. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as txsr. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 128. dynamic memory auto refresh period register (dynamicrfc - address 0x2009 c04c) bit description bit symbol description reset value 4:0 trfc auto-refresh period and auto-refresh to active command period. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 129. dynamic memory exit self refresh register (dynamicxsr - address 0x2009 c050) bit description bit symbol description reset value 4:0 txsr exit self-refresh to active command time. 0x0 - 0x1e = n + 1 clock cycles. the delay is in cclk cycles. 0x1f = 32 clock cycles (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 185 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.16 dynamic memory ac tive bank a to active ba nk b time register the emcdynamictrrd register enables you to program the active bank a to active bank b latency, trrd. it is recommended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as trrd. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. 9.13.17 dynamic memory load mode register to active command time the emcdynamictmrd register enables you to pr ogram the load mode register to active command time, tmrd. it is reco mmended that this register is modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this value is normally found in sdram data sheets as tmrd, or trsa. this register is accessed with one wait state. note: this register is used fo r all four dynamic memory chip selects. therefore the worst case value for all of the chip selects must be programmed. table 130. dynamic memory active bank a to active bank b time register (dynamicrrd - address 0x2009 c054) bit description bit symbol description reset value 3:0 trrd active bank a to active bank b latency 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 131. dynamic memory load mode register to active command time (dynamicmrd - address 0x2009 c058) bit description bit symbol description reset value 3:0 tmrd load mode register to active command time. 0x0 - 0xe = n + 1 clock cycles. the delay is in cclk cycles. 0xf = 16 clock cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 186 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.18 static memory extended wait register extendedwait (ew) bit in the emcstaticconfig register is set. it is recommended that this register is modified during system initia lization, or when there are no current or outstanding transactions. however, if necessary, these control bits can be altered during normal operation. this register is accessed with one wait state. for example, for a static memory read/write transfer time of 16 s, and a cclk frequency of 50 mhz, the following value must be progra mmed into this register: (16 x 10-6 x 50 x 106) / 16 - 1 = 49 table 132. static memory extended wait register (staticextendedwait - address 0x2009 c080) bit description bit symbol description reset value 9:0 extendedwait extended wait time out. 16 clock cycles (por reset va lue). the delay is in cclk cycles. 0x0 = 16 clock cycles. 0x1 - 0x3ff = (n+1) x16 clock cycles. 0x0 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 187 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.19 dynamic memory c onfiguration registers the emcdynamicconfig0-3 registers enable you to program the configuration information for the relevant dynamic memory chip select . these registers are normally only modified during system initialization. these registers are accessed with one wait state. table 133 shows the bit assignments for th e emcdynamicconfig0-3 registers. [1] the sdram column and row width and number of banks are computed automatically from the address mapping. [2] the buffers must be disabled during sdram initia lization. the buffers must be enabled during normal operation. table 133. dynamic memory configuration registers (dynamicconfig[0:3], address 0x2009 c100 (dynamicconfig0), 0x2009 c120 (dynamicconfig 1), 0x2009 c140 (dynamicconfig2), 0x2009 c160 (dynamicconfig3)) bit description bit symbol value description reset value 2:0 - reserved. read value is undefined, only zero should be written. na 4:3 md memory device. 0 0x0 sdram (por reset value). 0x1 low-power sdram. 0x2 reserved. 0x3 reserved. 6:5 - reserved. read value is undefined, only zero should be written. na 12:7 am0 see table 134 . 000000 = reset value. [1] 0 13 - reserved. read value is undefined, only zero should be written. na 14 am1 see table 134 . 0 = reset value. 0 18:15 - reserved. read value is undefined, only zero should be written. na 19 b buffer enable. 0 0 buffer disabled for accesses to this chip select (por reset value). 1 buffer enabled for accesse s to this chip select. [2] 20 p write protect. 0 0 writes not protected (por reset value). 1 writes protected. 31:21 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 188 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) address mappings that are not shown in table 134 are reserved. table 134. address mapping 14 12 11:9 8:7 description banks row length column length 16 bit bus width (row, bank, column) 0 0 000 00 16 mbits (2m x 8) 2 11 9 0 0 000 01 16 mbits (1m x 16) 2 11 8 0 0 001 00 64 mbits (8m x 8) 4 12 9 0 0 001 01 64 mbits (4m x 16) 4 12 8 0 0 010 00 128 mbits (16m x 8) 4 12 10 0 0 010 01 128 mbits (8m x 16) 4 12 9 0 0 011 00 256 mbits (32m x 8) 4 13 10 0 0 011 01 256 mbits (16m x 16) 4 13 9 0 0 100 00 512 mbits (64m x 8) 4 13 11 0 0 100 01 512 mbits (32m x 16) 4 13 10 16 bit bus width (bank, row, column) 0 1 000 00 16 mbits (2m x 8) 2 11 9 0 1 000 01 16 mbits (1m x 16) 2 11 8 0 1 001 00 64 mbits (8m x 8) 4 12 9 0 1 001 01 64 mbits (4m x 16) 4 12 8 0 1 010 00 128 mbits (16m x 8) 4 12 10 0 1 010 01 128 mbits (8m x 16) 4 12 9 0 1 011 00 256 mbits (32m x 8) 4 13 10 0 1 011 01 256 mbits (16m x 16) 4 13 9 0 1 100 00 512 mbits (64m x 8) 4 13 11 0 1 100 01 512 mbits (32m x 16) 4 13 10 32 bit bus width (row, bank, column) 1 0 000 00 16 mbits (2m x 8) 2 11 9 1 0 000 01 16 mbits (1m x 16) 2 11 8 1 0 001 00 64 mbits (8m x 8) 4 12 9 1 0 001 01 64 mbits (4m x 16) 4 12 8 1 0 001 10 64 mbits (2m x 32) 4 11 8 1 0 010 00 128 mbits (16m x 8) 4 12 10 1 0 010 01 128 mbits (8m x 16) 4 12 9 1 0 010 10 128 mbits (4m x 32) 4 12 8 1 0 011 00 256 mbits (32m x 8) 4 13 10 1 0 011 01 256 mbits (16m x 16) 4 13 9 1 0 011 10 256 mbits (8m x 32) 4 13 8 1 0 100 00 512 mbits (64m x 8) 4 13 11 1 0 100 01 512 mbits (32m x 16) 4 13 10 32 bit bus width (bank, row, column) 1 1 000 00 16 mbits (2m x 8) 2 11 9 1 1 000 01 16 mbits (1m x 16) 2 11 8
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 189 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) a chip select can be connected to a single memo ry device, in this case the chip select data bus width is the same as the device width. alternatively the chip select can be connected to a number of external devices. in this case the chip select data bus width is the sum of the memory device data bus widths. for example, for a chip select connected to: ? a 32 bit wide memory device, choose a 32 bit wide address mapping. ? a 16 bit wide memory device, choose a 16 bit wide address mapping. ? four x 8 bit wide memory devices, choose a 32 bit wide address mapping. ? two x 8 bit wide memory devices, choose a 16 bit wide address mapping. the sdram bank select pins ba1 and ba0 ar e connected to address lines a14 and a13, respectively. 9.13.20 dynamic memory ras & cas delay registers the emcdynamicrascas0-3 registers enable you to program the ras and cas latencies for the relevant dynamic memory. it is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these regi sters are accessed with one wait state. note: the values programmed into these regist ers must be consistent with the values used to initialize the sdram memory device. 1 1 001 00 64 mbits (8m x 8) 4 12 9 1 1 001 01 64 mbits (4m x 16) 4 12 8 1 1 001 10 64 mbits (2m x 32) 4 11 8 1 1 010 00 128 mbits (16m x 8) 4 12 10 1 1 010 01 128 mbits (8m x 16) 4 12 9 1 1 010 10 128 mbits (4m x 32) 4 12 8 1 1 011 00 256 mbits (32m x 8) 4 13 10 1 1 011 01 256 mbits (16m x 16) 4 13 9 1 1 011 10 256 mbits (8m x 32) 4 13 8 1 1 100 00 512 mbits (64m x 8) 4 13 11 1 1 100 01 512 mbits (32m x 16) 4 13 10 table 134. address mapping 14 12 11:9 8:7 description banks row length column length
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 190 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) table 135. dynamic memory rascas delay regi sters (dynamicrascas[0:3], address 0x2009 c104 (dynamicrascas0), 0x2009 c124 (dynamicras cas1), 0x2009 c144 (dynamicrascas2), 0x2009 c164 (dynamicrascas3)) bit description bit symbol value description reset value 1:0 ras ras latency (active to read/write delay). 11 0x0 reserved. 0x1 one cclk cycle. 0x2 two cclk cycles. 0x3 three cclk cycles (por reset value). 7:2 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - 9:8 cas cas latency. 11 0x0 reserved. 0x1 one cclk cycle. 0x2 two cclk cycles. 0x3 three cclk cycles (por reset value). 31:10 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 191 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.21 static memory configuration registers the emcstaticconfig0-3 registers configure th e static memory configuration. it is recommended that these registers are modified during system initializat ion, or when there are no current or outstanding transactions. th is can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. table 136 shows the bit assignments for the emcstaticconfig0-3 registers. note that synchronous burst mode memory devices are not supported. table 136. static memory configuration registers (s taticconfig[0:3], address 0x2009 c200 (staticconfig0), 0x2009 c220 (staticconfig1), 0x2009 c240 (staticconfig2), 0x2009 c260 (staticconfig3)) bit description bit symbol value description reset value 1:0 mw memory width. 0 0x0 8 bit (por reset value). 0x1 16 bit. 0x2 32 bit. 0x3 reserved. 2 - reserved. read value is undefined, only zero should be written. na 3 pm page mode. in page mode the emc can burst up to four external accesses. therefore devices with asynchronous page mode burst four or higher devices are supported. asynchronous page mode burst two devices are not supported and must be accessed normally. 0 0 disabled (por reset value). 1 asynchronous page mode enabled (page length four). 5:4 - reserved. read value is undefined, only zero should be written. na 6 pc chip select polarity. the value of the chip select polarity on power-on reset is 0. 0 0 active low chip select. 1 active high chip select. 7 pb byte lane state. the byte lane state bit, pb, enables different types of memory to be connected. for byte-wide static memories the bls3:0 signal from the emc is usually connected to we (write enable). in this case for reads all the bls3:0 bits must be high. this means that the byte lane state (pb) bit must be low. 16 bit wide static memory devices usually have the bls3:0 signals connected to the ubn and lbn (upper byte and lower byte) signals in the static memory. in this case a write to a particular byte must assert the appropriate ubn or lbn signal low. for reads, all the ub and lb signals must be asserted low so that the bus is driven. in this case the byte lane state (pb) bit must be high. 0 0 for reads all the bits in bls3:0 are high. for writes the respective active bits in bls3:0 are low (por reset value). 1 for reads the respective active bits in bls3:0 are low. for writes the respective active bits in bls3:0 are low.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 192 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) [1] extended wait and page mode cannot be selected simultaneously. [2] emc may perform burst read access even when the buffer enable bit is cleared. 9.13.22 static memory writ e enable delay registers the emcstaticwaitwen0-3 registers enable you to program the delay from the chip select to the write enable. it is recommended that these registers are mo dified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. 8 ew extended wait (ew) uses the emcstaticextendedwait register to time both the read and write transfers rather than the emcstaticwaitrd and emcstaticwaitwr registers. this enables much longer transactions. [1] 0 0 extended wait disabled (por reset value). 1 extended wait enabled. 18:9 - reserved. read value is undefined, only zero should be written. na 19 b buffer enable [2] 0 0 buffer disabled (por reset value). 1 buffer enabled. 20 p write protect 0 0 writes not protected (por reset value). 1 write protected. 31:21 - reserved. read value is undefined, only zero should be written. na table 136. static memory configuration registers (s taticconfig[0:3], address 0x2009 c200 (staticconfig0), 0x2009 c220 (staticconfig1), 0x2009 c240 (staticconfig2), 0x2009 c260 (staticconfig3)) bit description bit symbol value description reset value table 137. static memory write enable delay registers (staticwaitwen[0:3], address 0x2009 c204 (staticwaitwen0), 0x2009 c224 (staticwaitwen1),0x2009 c244 (staticwaitwen2), 0x2009 c264 (staticwaitwen3)) bit description bit symbol description reset value 3:0 waitwen wait write enable. delay from chip select assertion to write enable. 0x0 = one cclk cycle delay between assertion of chip select and write enable (por reset value). 0x1 - 0xf = (n + 1) cclk cycle delay. the delay is (waitwen +1) x tcclk. 0x0 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 193 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.23 static memory output enable delay registers the emcstaticwaitoen0-3 registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. it is recommended that these registers are modified during system initializ ation, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. 9.13.24 static memory read delay registers the emcstaticwaitrd0-3 registers enable you to program the delay from the chip select to the read access. it is recommended that these registers are mo dified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. it is not used if the extended wait bit is enabl ed in the emcstaticconfig0-3 registers. these registers are accessed with one wait state. [1] the reset value depends on the boot mode. table 138. static memory output enable delay registers (staticwaitoen[0:3], address 0x2009 c208 (staticwaitoen0), 0x0x2009 c228 (staticwaitoen1), 0x0x2009 c248 (staticwaitoen2), 0x0x2009 c268 (staticwaitoen3)) bit description bit symbol description reset value 3:0 waitoen wait output enable. delay from chip select assertion to output enable. 0x0 = no delay (por reset value). 0x1 - 0xf = n cycle delay. the delay is waitoen x tcclk. 0x0 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 139. static memory read delay registers (staticwaitrd[0:3], address 0x2009 c20c (staticwaitrd0), 0x2009 c22c (staticwaitrd1), 0x2009 c24c (staticwaitrd2), 0x2009 c26c (s taticwaitrd3)) bit description bit symbol description reset value 4:0 waitrd non-page mode read wait states or asynchronous page mode read first access wait state. non-page mode read or asynchronous page mode read, first read only: 0x0 - 0x1e = (n + 1) cclk cycl es for read accesses. for non-sequential reads, the wait state time is (waitrd + 1) x tcclk. 0x1f = 32 cclk cycles for re ad accesses (por reset value). 0x1f [1] 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 194 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.25 static memory page mode read delay registers the emcstaticwaitpage0-3 registers enable you to program the delay for asynchronous page mode sequential accesses. it is reco mmended that these registers are modified during system initialization, or when there are no current or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. this register is accessed with one wait state. 9.13.26 static memory write delay registers the emcstaticwaitwr0-3 registers enable you to program the delay from the chip select to the write access. it is recommended that these registers are modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode.these registers are not used if the extended wait (ew) bit is enabled in the emcstaticconfig register. these register s are accessed with one wait state. table 140. static memory page mode read delay registers (staticwaitpage[0:3], address 0x2009 c210 (staticwaitpage0), 2009 c230 (staticwaitpage1), 0x2009 c250 (staticwaitpage2), 0x2009 c270 (s taticwaitpage3)) bit description bit symbol description reset value 4:0 waitpage asynchronous page mode read after the first read wait states. number of wait states for asynchronous page mode read accesses after the first read: 0x0 - 0x1e = (n+ 1) cclk cycle read access time. for asynchronous page mode read for sequential reads, the wait state time for page mode accesses after the first read is (waitpage + 1) x tcclk. 0x1f = 32 cclk cycle read access time (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 141. static memory write delay registers (staticwaitwr[0:3], address 0x2009 c214 (staticwaitwr0), 0x2009 c234 (staticwaitwr1), 0x2009 c254 (staticwaitwr2), 0x2009 c274 (staticwaitwr3)) bit description bit symbol description reset value 4:0 waitwr write wait states. sram wait state time for writ e accesses after the first read: 0x0 - 0x1e = (n + 2) cclk cycle writ e access time. the wait state time for write accesses after the first read is waitwr (n + 2) x tcclk. 0x1f = 33 cclk cycle write ac cess time (por reset value). 0x1f 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 195 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.13.27 static memory turn round delay registers the emcstaticwaitturn0-3 registers enable you to program the number of bus turnaround cycles. it is recommended that these registers are modified during system initialization, or when there are no curren t or outstanding transactions. this can be ensured by waiting until the emc is idle, and then entering low-power, or disabled mode. these registers are accessed with one wait state. to prevent bus contention on the external me mory data bus, the waitturn field controls the number of bus turnaround cycles added between static memory read and write accesses. the waitturn field also controls the number of turnaround cycles between static memory and dy namic memory accesses. table 142. static memory turn-around delay registers (staticwaitturn[0:3], address 0x2009 c218 (staticwaitturn0),0x2009 c238 (staticwaitturn1), 0x2009 c258 (staticwaitturn2), 0x2009 c278 (staticwaitturn3)) bit description bit symbol description reset value 3:0 waitturn bus turn-around cycles. 0x0 - 0xe = (n + 1) cclk turn-around cycles. bus turn-around time is (waitturn + 1) x tcclk. 0xf = 16 cclk turn-around cycles (por reset value). 0xf 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 196 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14 external memory interface external memory interfacing depends on the bank width (32, 16 or 8 bit selected via mw bits in corresponding emcstaticconfig register). if a memory bank is configured to be 32 bits wide, address lines a0 and a1 can be used as non-address lines. if a memory bank is configured to 16 bits wide, a0 is not required. however, 8 bit wide memory banks do require all address lines down to a0. configuring the a1 and/or a0 lines to provide address or non-address function is accomplished using the iocon registers (see section 7.4.1 ). symbol "a_b" in the following figures refers to the highest order address line in the data bus. symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. 9.14.1 32-bit wide memory bank connection a. 32 bit wide memory bank interfaced to four 8 bit memory chips b. 32 bit wide memory bank interfaced to two 16 bit memory chips a[a_b:2] bls[1] d[15:8] ce oe we io[7:0] a[a_m:0] bls[0] d[7:0] ce oe we io[7:0] a[a_m:0] oe cs bls[3] d[31:24] ce oe we io[7:0] a[a_m:0] bls[2] d[23:16] ce oe we io[7:0] a[a_m:0] oe cs we ce oe we ub lb io[15:0] a[a_m:0] d[31:16] bls[2] ce oe we ub lb io[15:0] a[a_m:0] d[15:0] bls[0] a[a_b:2] bls[3] bls[1]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 197 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.2 16-bit wide memory bank connection c. 32 bit wide memory bank interfaced to one 8 bit memory chip fig 18. 32 bit bank external memory interfaces ( bits mw = 10) oe cs we ce oe we b3 b2 b1 b0 io[31:0] a[a_m:0] d[31:0] bls[2] a[a_b:2] bls[3] bls[0] bls[1] a. 16 bit wide memory bank interfaced to two 8 bit memory chips b. 16 bit wide memory bank interfaced to a 16 bit memory chip fig 19. 16 bit bank external memory interfaces (bits mw = 01) oe cs bls[1] d[15:8] ce oe we io[7:0] a[a_m:0] bls[0] d[7:0] ce oe we io[7:0] a[a_m:0] a[a_b:1] oe cs we ce oe we ub lb io[15:0] a[a_m:0] d[15:0] bls[0] a[a_b:1] bls[1]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 198 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.3 8-bit wide memory bank connection fig 20. 8 bit bank external memory interface (bits mw = 00) oe cs we d[7:0] ce oe we io[7:0] a[a_m:0] a[a_b:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 199 of 942 nxp semiconductors UM10562 chapter 9: lpc408x/407x external memory controller (emc) 9.14.4 memory configuration example fig 21. typical memory configuration diagram nce noe q[31:0] a[20:0] nce noe io[15:0] a[15:0] nwe nub nlb nce noe io[15:0] a[15:0] nwe nub nlb nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe nce noe io[7:0] a[16:0] nwe 2mx32 burst mask rom 64kx16 sram, two off 128kx8 sram, four off a[20:0] a[20:0] d[31:0] d[31:0] cs0 oe cs1 cs2 we bls3 bls2 bls1 bls0 a[16:0] a[16:0] a[16:0] a[16:0] a[15:0] a[15:0] d[31:16] d[15:0] d[31:24] d[23:16] d[15:8] d[7:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 200 of 942 10.1 basic configuration the ethernet controller is configur ed using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcenet. remark: on reset, the ethernet block is disabled (pcenet = 0). 2. clock: see section 3.3.3.2 . 3. pins: enable ethernet pins and select th eir modes through the iocon registers, see section 7.4.1 . 4. wake-up: activity on the ethernet po rt can wake up the microcontroller from power-down mode, see section 3.12.8 . 5. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. initialization: see section 10.13.2 . 10.2 introduction the ethernet block contains a full featured 10 mbps or 100 mbps ethernet mac (media access controller) designed to provide opti mized performance thro ugh the use of dma hardware acceleration. features include a generous suite of control registers, half or full duplex operation, flow control, control fram es, hardware acceleration for transmit retry, receive packet filtering and wake-up on lan activity. automatic frame transmission and reception with scatter-gather dma off-loads many operations from the cpu. the ethernet block is an ahb master that dr ives the ahb bus matrix . through the matrix, it has access to all on-chip ram memories. a recommended use of ram by the ethernet is to use one of the ram blocks exclusively for ethernet traffic. that ram would then be accessed only by the ethernet and the cpu, and possibly the gpdma, giving maximum bandwidth to the ethernet function. the ethernet block interfaces between an off-chip ethernet phy using the mii (media independent interface) or rmii (reduced mii) protocol and the on-chip miim (media independent interface management) serial bus, also referred to as mdio (management data input/output). UM10562 chapter 10: lpc408x/407x ethernet rev. 1 ? 13 september 2012 user manual table 143. ethernet acronyms, abbreviations, and definitions acronym or abbreviation definition ahb advanced high-performance bus crc cyclic redundancy check dma direct memory access double-word 64-bit entity fcs frame check sequence (crc) fragment a (part of an) ethernet frame; one or multip le fragments can add up to a single ethernet frame.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 201 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.3 features ? ethernet standards support: ? supports 10 or 100 mbps phy devices including 10 base-t, 100 base-tx, 100 base-fx, and 100 base-t4. ? fully compliant with ieee standard 802.3. ? fully compliant with 802.3x full duplex flow control and half duplex back pressure. ? flexible transmit and receive frame options. ? vlan frame support. ? memory management: ? independent transmit and receive buffers memory mapped to shared sram. ? dma managers with scatter/gather dma and arrays of frame descriptors. ? memory traffic optimized by buffering and prefetching. ? enhanced ethernet features: ? receive filtering. ? multicast and broadcast frame suppor t for both transmit and receive. ? optional automatic fcs inse rtion (crc) for transmit. ? selectable automatic transmit frame padding. frame an ethernet frame consists of destination address, source address, length type field, payload and frame check sequence. half-word 16-bit entity lan local area network mac media access control sublayer mii media independent interface miim mii management octet an 8-bit data entity, used in lieu of "byte" by ieee 802.3 packet a frame that is transported across ethernet; a packet consists of a preamble, a start of frame delimiter and an ethernet frame. phy ethernet physical layer rmii reduced mii rx receive tcp/ip transmission control protocol / internet protocol. the most common high-level protocol used with ethernet. tx transmit vlan virtual lan wol wake-up on lan word 32-bit entity table 143. ethernet acronyms, abbreviations, and definitions acronym or abbreviation definition
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 202 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? over-length frame support for both transmit and receive allows any length frames. ? promiscuous receive mode. ? automatic collision backoff and frame retransmission. ? includes power management by clock switching. ? wake-on-lan power management support allows system wake-up: using the receive filters or a magic frame detection filter. ? physical interface: ? attachment of external phy chip thro ugh standard media independent interface (mii) or standard reduced mii (rmii) interface, soft ware selectable. ? phy register access is available via t he media independent interface management (miim) interface. 10.4 architecture and operation figure 22 shows the internal architecture of the ethernet block. the block diagram for the ethernet block consists of: ? the host registers module containing the registers in the software view and handling ahb accesses to the ethernet block. the ho st registers connect to the transmit and receive data path as well as the mac. ? the dma to ahb interface. this provides an ahb master connection that allows the ethernet block to access on-chip sram for re ading of descriptors, writing of status, and reading and writing data buffers. ? the ethernet mac, which interfaces to the off-chip phy via an mii or rmii interface. ? the transmit data path, including: fig 22. ethernet block diagram register interface (ahb slave) dma interface (ahb master) bus interface receive dma transmit dma receive buffer receive filter transmit retry transmit flow control ethernet mac rmii a dap ter rmii miim host registers ahb bus ethernet block et he rn et phy bus interface
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 203 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? the transmit dma manager which reads descriptors and data from memory and writes status to memory. ? the transmit retry module handling ethernet retry and abort situations. ? the transmit flow control module whic h can insert ethernet pause frames. ? the receive data path, including: ? the receive dma manager which reads desc riptors from memory and writes data and status to memory. ? the ethernet mac which detects frame types by parsing pa rt of the frame header. ? the receive filter which can filter out certain ethernet frames by applying different filtering schemes. ? the receive buffer implementing a delay fo r receive frames to allow the filter to filter out certain frames before storing them to memory. 10.5 dma engine functions the ethernet block is designed to provi de optimized performance via dma hardware acceleration. independent scatter/gather dma engines connected to the ahb bus off-load many data transfers from the cpu. descriptors, which are stored in memory, contain information about fragments of incoming or outgoing ethernet frames. a fragment may be an entire frame or a much smaller amount of data. each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be tr ansmitted or received. descriptors are stored in arrays in memory, which are located by pointer registers in the ethernet block. other registers determine t he size of the arrays, point to the next descriptor in each array that will be used by the dma engine, and point to the next descriptor in each array that will be used by the ethern et device driver. 10.6 overview of dma operation the dma engine makes use of a receive descriptor array and a transmit descriptor array in memory. all or part of an ethernet frame may be contained in a memory buffer associated with a descriptor. when transmitting, the transmit dma engine uses as many descriptors as needed (one or more) to obtain (gather) all of the parts of a frame, and sends them out in sequence. when receiving, the receive dma engine also uses as many descriptors as needed (one or more) to find plac es to store (scatter) all of the data in the received frame. the base address registers for the descriptor array, registers indicating the number of descriptor array entries, and descriptor arra y input/output pointers are contained in the ethernet block. the descriptor entries and all transmit and receive packet data are stored in memory which is not a part of the ether net block. the descriptor entries tell where related frame data is stored in memory, certai n aspects of how the data is handled, and the result status of each ethernet transaction.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 204 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet hardware in the dma engine controls how data incoming from the ethernet mac is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incomi ng data. driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer. the tw o pointers create a circular queue in the descriptor array and allow both the dma hardwa re and the driver software to know which descriptors (if any) are available for their use, including whether the descriptor array is empty or full. similarly, driver software must set up pointe rs to data that will be transmitted by the ethernet mac, giving instructions for each fr agment of data, and advancing the software transmit pointer for outgoing data. hardware in the dma engine reads this information and sends the data to the ethernet mac interface when possible, updating the status and advancing the hardware transmit pointer. 10.7 ethernet packet figure 23 illustrates the different fiel ds in an ethernet packet. a packet consists of a preamble, a start-of-frame delimiter and an ethernet frame. fig 23. ethernet packet fields optional vlan source address desa oct6 desa oct1 desa oct2 desa oct3 desa oct4 desa oct5 srca oct6 srca oct5 srca oct4 srca oct3 srca oct2 srca oct1 lsb oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) msb oct(7) destination address payload fcs ethernet frame preamble 7 bytes ethernet packet start-of-frame delimiter 1 byte time len type
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 205 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the ethernet frame consists of the destinat ion address, the source address, an optional vlan field, the length/type field, the payload and the frame check sequence. each address consists of 6 bytes where each by te consists of 8 bits. bits are transferred starting with the least significant bit. 10.8 overview 10.8.1 partitioning the ethernet block and associated device driver software offer the functionality of the media access control (mac) sublayer of the data link layer in the osi reference model (see ieee std 802.3). the mac sublayer offe rs the service of transmitting and receiving frames to the next higher protocol level, the mac client layer, typically the logical link control sublayer. the device driver software implements the interface to the mac client layer. it sets up registers in the ethernet bl ock, maintains descriptor arrays pointing to frames in memory and receives results back from the ethernet block through interrupts. when a frame is transmitted, the software partially sets up the ethernet frames by providing pointers to the destination address field, source address field, the length/type field, the mac client data field and optionally the crc in the frame check sequence field. preferably concatenation of frame fields s hould be done by using the scatter/gather functionality of the ethernet core to avoid unnecessary copying of data. the hardware adds the preamble and start frame delimiter fields and can optionally add the crc, if requested by software. when a packet is re ceived the hardware strips the preamble and start frame delimiter and passes the rest of th e packet - the ethernet frame - to the device driver, including destination address, source a ddress, length/type field, mac client data and frame check sequence (fcs). apart from the mac, the ethernet block contai ns receive and transmit dma managers that control receive and transmit data stream s between the mac and the ahb interface. frames are passed via descriptor arrays locat ed in host memory, so that the hardware can process many frames without software/cpu support. frames can consist of multiple fragments that are accessed with scatter/gather dma. the dma managers optimize memory bandwidth using prefetching and buffering. a receive filter block is used to identify rece ived frames that are not addressed to this ethernet station, so that they can be discar ded. the rx filters include a perfect address filter and a hash filter. wake-on-lan power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the lan. wake-up fr ames are recognized by the receive filtering modules or by a magic frame detection technology. system wake-up occurs by triggering an interrupt. an interrupt logic block raises and masks interrupts and keeps track of the cause of interrupts. the interrupt block sends an inte rrupt request signal to the host system. interrupts can be enabled, cleared and set by software.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 206 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet support for ieee 802.3/clause 31 flow control is implemented in the flow control block. receive flow control frames are automatically handled by the mac. transmit flow control frames can be initiated by software. in half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded. the ethernet block has both a standard media independent interface (mii) bus and a reduced media independent interface (rmii) to connect to an external ethernet phy chip. mii or rmii mode can be selected by the rmii bit in the command register. the standard nibble-wide mii interface allows a low speed data connection to the phy chip: 2.5 mhz at 10 mbps or 25 mhz at 100 mbps. the rmii interface allows a low pin count double clock data connection to the phy. registers in the phy chip are accessed via the ahb interface through the serial management connection of the miim bus, typically operating at 2.5 mhz. 10.8.2 example phy devices some examples of compatible phy devices are shown in ta b l e 1 4 4 . table 144. example phy devices manufacturer part numbers broadcom bcm5221 ics ics1893 intel lxt971a lsi logic l80223, l80225, l80227 micrel ks8721 national dp83847, dp83846, dp83843 smsc lan83c185
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 207 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.9 pin description table 145 shows the signals used for connecting the media independent interface (mii), and table 146 shows the signals used for connecting the reduced media independent interface (rmii) to the external phy. table 147 shows the signals used for media independent interface management (miim) to the external phy. table 145. ethernet mii pin descriptions pin name type pin description enet_tx_en output transmit data enable, active low. enet_txd3:0 output transmit data, 4 bits. enet_tx_er output transmit error. enet_tx_clk input transmitter clock. enet_rx_dv input receive data valid. enet_rxd3:0 input receive data, 4 bits. enet_rx_er input receive error. enet_rx_clk input receive clock. enet_col input collision detect. enet_crs input carrier sense. table 146. ethernet rmii pin descriptions pin name type pin description enet_tx_en output transmit data enable, active low. enet_txd1:0 output transmit data, 2 bits enet_rxd1:0 input receive data, 2 bits. enet_rx_er input receive error. enet_crs input enet_crs_dv. carrier sense/data valid. enet_rx_clk input enet_ref_clk. reference clock. table 147. ethernet miim pin descriptions pin name type pin description enet_mdc output miim clock. enet_mdio input/output mi data input and output
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 208 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10 register description the software interface of the ethernet block c onsists of a register view and the format definitions for the transmit and receive descri ptors. these two aspects are addressed in the next two subsections. the total ahb address space required for the ethernet is 4 kilobytes. after a hard reset or a soft reset via the regreset bit of the command register all bits in all registers are reset to 0 unless stated othe rwise in the following register descriptions. some registers will have unused bi ts which will return a 0 on a read via the ahb interface. writing to unused register bits of an otherwise writable regist er will not have side effects. the register map consists of registers in t he ethernet mac and registers around the core for controlling dma transfers, flow control and filtering. reading from reserved addresses or reserved bits leads to unpredictable data. writing to reserved addresses or reserved bits has no effect. reading of write-only register s will return a read error on the ahb interface. writing of read-only registers will return a write error on the ahb interface. table 148. register overview: ethernet (base address 0x2008 4000) name access address offset description reset value table mac registers mac1 r/w 0x000 mac configuration register 1. 0x8000 149 mac2 r/w 0x004 mac configuration register 2. 0 150 ipgt r/w 0x008 back-to-back in ter-packet-gap register. 0 152 ipgr r/w 0x00c non back-to-back inter-packet-gap register. 0 153 clrt r/w 0x010 collision window / retry register. 0x370f 154 maxf r/w 0x014 maximum frame register. 0x0600 155 supp r/w 0x018 phy support register. 0 156 test r/w 0x01c test register. 0 157 mcfg r/w 0x020 mii mgmt configuration register. 0 158 mcmd r/w 0x024 mii mgmt command register. 0 160 madr r/w 0x028 mii mgmt address register. 0 161 mwtd wo 0x02c mii mgmt write data register. - 162 mrdd ro 0x030 mii mgmt read data register. 0 163 mind ro 0x034 mii mgmt indicators register. 0 164 sa0 r/w 0x040 station address 0 register. 0 165 sa1 r/w 0x044 station address 1 register. 0 166 sa2 r/w 0x048 station address 2 register. 0 167 control registers command r/w 0x100 command register. 0 168 status ro 0x104 status register. 0 169 rxdescriptor r/w 0x108 receive descriptor base address register. 0 170
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 209 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the third column in the table lists the accessibility of the re gister: read-only , write-only, read/write. all ahb register write transactions except for accesses to the interrupt registers are posted i.e. the ahb tran saction will complete be fore write data is act ually committed to the register. accesses to the inte rrupt registers will only be co mpleted by accepting the write data when the data has been committed to the register. rxstatus r/w 0x10c receive status base address register. 0 171 rxdescriptornumber r/w 0x110 receive number of descriptors register. 0 172 rxproduceindex ro 0x114 receive produce index register. 0 173 rxconsumeindex r/w 0x118 receive consume index register. 0 174 txdescriptor r/w 0x11c transmit descriptor base address register. 0 175 txstatus r/w 0x120 transmit status base address register. 0 176 txdescriptornumber r/w 0x124 transmit number of descriptors register. 0 177 txproduceindex r/w 0x128 transmi t produce index register. 0 178 txconsumeindex ro 0x12c transmit consume index register. 0 179 tsv0 ro 0x158 transmit status vector 0 register. 0 180 tsv1 ro 0x15c transmit status vector 1 register. 0 181 rsv ro 0x160 receive status vector register. 0 182 flowcontrolcounter r/w 0x170 flow control coun ter register. 0 183 flowcontrolstatus ro 0x174 flow control status register. 0 184 rx filter registers rxfilterctrl r/w 0x200 receive filter control register. 0 185 rxfilterwolstatus ro 0x204 receive filter wol status register. 0 186 rxfilterwolclear wo 0x208 receive filter wol clear register. - 187 hashfilterl r/w 0x210 hash filter table lsbs register. 0 188 hashfilterh r/w 0x214 hash filter table msbs register. 0 189 module control registers intstatus ro 0xfe0 interrupt status register. 0 190 intenable r/w 0xfe4 interrupt enable register. 0 191 intclear wo 0xfe8 interrupt clear register. - 192 intset wo 0xfec interrupt set register. - 193 powerdown r/w 0xff4 power-down register. 0 194 table 148. register overview: ethernet (base address 0x2008 4000) name access address offset description reset value table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 210 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1 ethernet mac register definitions this section defines the bits in the individual registers of the ethernet block register map. 10.10.1.1 mac configuration register 1 the mac configuration register 1 (mac1) has an address of 0x2008 4000. its bit definition is shown in table 149 . table 149. mac configuration register 1 (mac1 - address 0x2008 4000) bit description bit symbol function reset value 0 rxenable receive enable. set this to allow receive frames to be received. internally the mac synchronizes this control bit to the incoming receive stream. 0 1 parf pass all receive frames. when enabled (set to 1), t he mac will pass all frames regardless of type (normal vs. control). when disabled, the mac does not pass valid control frames. 0 2 rxflowctrl rx flow control. when enabled (set to 1), the mac acts upon received pause flow control frames. when disabled, received pause flow control frames are ignored. 0 3 txflowctrl tx flow control. when enabled (set to 1), pause flow control frames are allowed to be transmitted. when disabled, flow control frames are blocked. 0 4 loopback setting this bit will cause the mac transmit interface to be looped back to the mac receive interface. clearing this bit results in normal operation. 0 7:5 - unused 0 8 resettx setting this bit will put the transmit function logic in reset. 0 9 resetmcstx setting this bit resets the mac cont rol sublayer / transmit logic. the mcs logic implements flow control. 0 10 resetrx setting this bit will put t he ethernet receive logic in reset. 0 11 resetmcsrx setting this bit resets the mac cont rol sublayer / receive logic. the mcs logic implements flow control. 0 13:12 - reserved. read value is undefined, only zero should be written. 0 14 simreset simulation reset. settin g this bit will cause a reset to the random nu mber generator within the transmit function. 0 15 softreset soft reset. setting this bit will put all modules within the mac in reset except the host interface. 1 31:16 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 211 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.2 mac configuration register 2 table 150. mac configuration register 2 (mac2 - address 0x2008 4004) bit description bit symbol function reset value 0 fullduplex when enabled (set to 1), the mac operates in full-duplex mode. when disabled, the mac operates in half-duplex mode. 0 1 flc framelength checking. when enabled (set to 1), both transmit and receive frame lengths are compared to the length/type field. if the length/type field represents a length then the check is per formed. mismatches are reported in the statusinfo word for each received frame. 0 2 hfen huge frame enable. when enabled (set to 1), frames of any length are transmitted and received. 0 3 delayedcrc delayed crc. this bit determines the number of bytes, if any, of proprietary header information that exist on the front of ieee 802.3 frames. when 1, four bytes of header (ignored by the crc function) are added. when 0, there is no proprietary header. 0 4 crcen crc enable. set this bit to append a crc to every frame whether padding was required or not. must be set if pad/crc en able is set. clear this bit if frames presented to the mac contain a crc. 0 5 padcrcen pad crc enable. set this bit to have the mac pad all short frames. clear this bit if frames presented to the mac have a valid length. this bit is used in conjunction with auto pad enable and vlan pad enable. see table 152 - pad operation for details on the pad function. 0 6 vlanpaden vlan pad enable. set this bit to caus e the mac to pad all short frames to 64 bytes and append a valid crc. consult table 152 - pad operation for more information on the various padding features. note: this bit is ignored if pad / crc enable is cleared. 0 7 autodetpaden autodetectpad enable. set this bit to cause the mac to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (vlan protocol id) and pad accordingly. table 152 - pad operation provides a description of the pad f unction based on the configuration of this register. note: this bit is ignored if pad / crc enable is cleared. 0 8 ppenf pure preamble enforcement . when enabled (set to 1) , the mac will verify the content of the preamble to ensure it contains 0x55 and is error-free. a packet with an incorrect preamble is discarded. when disabled, no preamble checking is performed. 0 9 lpenf long preamble enforcement. when enabled (set to 1), the mac only allows receive packets which contain preamble fields less than 12 bytes in length. when disabled, the mac allows any length preamble as per the standard. 0 11:10 - reserved. read value is undefined, only zero should be written. 0 12 nobackoff when enabled (set to 1), the mac will immediately retransmit following a collision rather than using the binary exponential backoff algorithm as specified in the standard. 0 13 bp_nobackoff back pressure / no backoff. when enabled (set to 1), after the mac incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent. 0 14 excessdefer when enabled (set to 1) the mac will defer to carrier indefinitely as per the standard. when disabled, the mac will abort when the excessive deferral limit is reached. 0 31:15 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 212 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.3 back-to-back inter-packet-gap register 10.10.1.4 non back-to-back inter-packet-gap register table 151. pad operation type auto detect pad enable mac2 [7] vlan pad enable mac2 [6] pad/crc enable mac2 [5] action any x x 0 no pad or crc check any 0 0 1 pad to 60 bytes, append crc any x 1 1 pad to 64 bytes, append crc any 1 0 1 if untagged, pad to 60 bytes and append crc. if vlan tagged: pad to 64 bytes and append crc. table 152. back-to-back inter-packet-gap register (ipgt - address 0x2008 4008) bit description bit symbol function reset value 6:0 btobintegap back-to-back inter-packet-gap.this is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. in full-duplex mode, the register value should be the desired period in nibble times minus 3. in half-duplex mode, the register value should be the desired period in nibble times minus 6. in full-duplex the recommended setting is 0x15 (21d), which represents the minimum ip g of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). in half-duplex the recommended setting is 0x12 (18d), which also represents the minimum ipg of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). 0 31:7 - reserved. read value is undefined, only zero should be written. 0 table 153. non back-to-back inter-packet-gap register (ipgr - address 0x2008 400c) bit description bit symbol function reset value 6:0 nbtobintegap2 non-back-to-back inter-packet -gap part2. this is a programmable field representing the non-back-to-back inter-packet-gap. the recommended value is 0x12 (18d), which represents the minimum ipg of 960 ns (in 100 mbps mode) or 9.6 s (in 10 mbps mode). 0 7 - reserved. read value is undefined, only zero should be written. 0 14:8 nbtobintegap1 non-back-to-back inter-packet -gap part1. this is a programmable field representing the optional carriersense wind ow referenced in ieee 802.3/4. 2.3.2.1 'carrier deference'. if carrier is detected during the timing of ipgr1, the mac defers to carrier. if, however, carrier becomes active after ipgr1, the mac continues timing ipgr2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. its range of values is 0x0 to ipgr2. the recommended value is 0xc (12d) 0 31:15 - reserved. read value is undefined, only zero should be written. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 213 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.5 collision window / retry register 10.10.1.6 maximum frame register 10.10.1.7 phy support register the supp register provides additional control over the rmii interface. unused bits in the phy support register should be left as zeroes. table 154. collision window / retry register (clrt - address 0x2008 4010) bit description bit symbol function reset value 3:0 retransmax retransmission maximum.this is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. the standard specifies the attemptlimit to be 0xf (15d). see ieee 802.3/4.2.3.2.5. 0xf 7:4 - reserved. read value is undefined, only zero should be written. 0 13:8 collwin collision window. this is a progra mmable field representing the slot time or collision window during which collisions occur in properly configured networks. the default value of 0x37 (55d) represents a 56 byte window following the preamble and sfd. 0x37 31:14 - reserved. read value is undefined, only zero should be written. na table 155. maximum frame register (maxf - address 0x2008 4014) bit description bit symbol function reset value 15:0 maxflen maximum frame length. this field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. an untagged maximum size ethernet frame is 1518 octets. a tagged frame adds four octets for a total of 1522 octets. if a shorter maximum length restriction is desired, program this 16-bit field. 0x0600 31:16 - unused 0 table 156. phy support register (supp - address 0x2008 4018) bit description bit symbol function reset value 7:0 - unused 0 8 speed this bit configures the reduced mii logi c for the current operating speed. when set, 100 mbps mode is selected. when cleared, 10 mbps mode is selected. 0 31:9 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 214 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.8 test register 10.10.1.9 mii mgmt configuration register table 157. test register (test - address 0x2008 401c) bit description bit symbol function reset value 0 scpq shortcut pause quanta. this bit reduces the effective pause quanta from 64 byte-times to 1 byte-time. 0 1 testpause this bit causes the mac control sublayer to inhibit transmissions, just as if a pause receive control frame with a nonzero pause time parameter was received. 0 2 testbp test backpressure. setting this bit will c ause the mac to assert backpressure on the link. backpressure causes preamble to be transmitted, raising carrier sense. a transmit packet from the system will be sent during backpressure. 0 31:3 - unused 0 table 158. mii mgmt configuration register (mcfg - address 0x2008 4020) bit description bit symbol function reset value 0 scaninc scan increment. set this bit to c ause the mii management hardware to perform read cycles across a range of phys. when set, the mii management hardware will perform read cycles from address 1 through the value set in phy address[4:0]. clear this bit to allow continuous reads of the same phy. 0 1 supppreamble suppress preamble. set this bit to cause the mii manage ment hardware to perform read/write cycles with out the 32-bit preamble field. clear this bit to cause normal cycles to be performed. some phys support suppressed preamble. 0 5:2 clocksel clock select. this field is used by the clock divide logic in creating the mii management clock (mdc) which ieee 802.3u defines to be no faster than 2.5 mhz. some phys support clock rates up to 12 .5 mhz, however. the ahb bus clock (hclk) is divided by the specified amount. refer to table 159 below for the definition of values for this field. 0 14:6 - unused 0 15 resetmiimgmt reset mii mgmt. this bit resets the mii m anagement hardware. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 215 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet [1] the maximum ahb clock rate allowed is limited to the maximum cpu clock rate for the device. 10.10.1.10 mii mgmt command register 10.10.1.11 mii mgmt address register table 159. clock select encoding clock select bit 5 bit 4 bit 3 bit 2 maximum ahb clock supported host clock divided by 4 0 0 0 x 10 host clock divided by 6 0 0 1 0 15 host clock divided by 8 0 0 1 1 20 host clock divided by 10 0 1 0 0 25 host clock divided by 14 0 1 0 1 35 host clock divided by 20 0 1 1 0 50 host clock divided by 28 0 1 1 1 70 host clock divided by 36 1 0 0 0 80 [1] host clock divided by 40 1 0 0 1 90 [1] host clock divided by 44 1 0 1 0 100 [1] host clock divided by 48 1 0 1 1 120 [1] host clock divided by 52 1 1 0 0 130 [1] host clock divided by 56 1 1 0 1 140 [1] host clock divided by 60 1 1 1 0 150 [1] host clock divided by 64 1 1 1 1 160 [1] table 160. mii mgmt command register (mcmd - address 0x2008 4024) bit description bit symbol function reset value 0 read this bit causes the mii management hardware to perform a single read cycle. the read data is returned in register mrdd (mii mgmt read data). 0 1 scan this bit causes the mii ma nagement hardware to perform read cycles continuously. this is useful for monitoring link fail for example. 0 31:2 - unused 0 table 161. mii mgmt address register (madr - address 0x2008 4028) bit description bit symbol function reset value 4:0 regaddr register address. this field represents the 5-bit register address field of mgmt cycles. up to 32 registers can be accessed. 0 7:5 - unused 0 12:8 phyaddr phy address. this field represents the 5-bit phy address field of mgmt cycles. up to 31 phys can be addressed (0 is reserved). 0 31:13 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 216 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.12 mii mgmt write data register 10.10.1.13 mii mgmt read data register 10.10.1.14 mii mgmt indicators register here are two examples to access phy via the mii management controller. for phy write if scan is not used: 1. write 0 to mcmd 2. write phy address and register address to madr 3. write data to mwtd 4. wait for busy bit to be cleared in mind for phy read if scan is not used: 1. write 1 to mcmd 2. write phy address and register address to madr 3. wait for busy bit to be cleared in mind 4. write 0 to mcmd 5. read data from mrdd table 162. mii mgmt write data register (mwtd - address 0x2008 402c) bit description bit symbol function 15:0 writedata write data. when written, an mii mgmt write cycle is performed using the 16-bit data and the pre-configured phy and register addresses from the mii mgmt address register (madr). 31:16 - unused table 163. mii mgmt read data register (mrdd - address 0x2008 4030) bit description bit symbol function reset value 15:0 readdata read data. following an mii mgmt read cycle, the 16-bit data can be read from this location. 0 31:16 - unused 0 table 164. mii mgmt indicators register (mind - address 0x2008 4034) bit description bit symbol function reset value 0 busy when 1 is returned - indicates mii mgmt is currently performing an mii mgmt read or write cycle. 0 1 scanning when 1 is returned - indicates a scan operation (continuous mii mgmt read cycles) is in progress. 0 2 notvalid when 1 is returned - indicates mii mg mt read cycle ha s not completed and the read data is not yet valid. 0 3 miilinkfail when 1 is returned - indicates that an mii mgmt link fail has occurred. 0 31:4 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 217 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.1.15 station address 0 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . 10.10.1.16 station address 1 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . 10.10.1.17 station address 2 register the station address is used for perfect addr ess filtering and for sending pause control frames. for the ordering of the octets in the packet please refer to figure 23 . table 165. station address register (sa0 - address 0x2008 4040) bit description bit symbol function reset value 7:0 saddr2 station address, 2nd octet. this field hol ds the second octet of the station address. 0 15:8 saddr1 station address, 1st octet. this field holds the first octet of the station address. 0 31:16 - unused 0 table 166. station address register (sa1 - address 0x2008 4044) bit description bit symbol function reset value 7:0 saddr4 station address, 4th octet. this field holds the fourth octet of the station address. 0 15:8 saddr3 station address, 3rd octet. this field ho lds the third octet of the station address. 0 31:16 - unused 0 table 167. station address register (sa2 - address 0x2008 4048) bit description bit symbol function reset value 7:0 saddr6 station address, 6th octet. this field holds the sixth octet of the station address. 0 15:8 saddr5 station address, 5th octet. this field holds the fifth octet of the station address. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 218 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2 control re gister definitions 10.10.2.1 command register all bits can be written and read . the tx/rxreset bits are writ e-only, reading will return a 0. 10.10.2.2 status register the status register (status) is a read-only register. the values represent the status of the two ch annels/data paths. when the status is 1, the channel is active, meaning: ? it is enabled and the rx/txenable bit is se t in the command register or it just got disabled while still transmit ting or receiving a frame. ? also, for the transmit channel, the transmit queue is not empty i.e. produceindex != consumeindex. ? also, for the receive channel, the receive queue is not full i.e. produceindex != consumeindex - 1. table 168. command register (command - address 0x2008 4100) bit description bit symbol function reset value 0 rxenable enable receive. 0 1 txenable enable transmit. 0 2 - unused 0 3 regreset when a 1 is written, all datapaths and the host registers ar e reset. the mac needs to be reset separately. 0 4 txreset when a 1 is written, the transmit datapath is reset. - 5 rxreset when a 1 is written, the receive datapath is reset. - 6 passruntframe when set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a crc error. if 0 runt frames are filtered out. 0 7 passrxfilter when set to 1 , disables receive filtering i.e. all frames received are written to memory. 0 8 txflowcontrol enable ieee 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. 0 9 rmii when set to 1 , rmii mode is selected; if 0, mii mode is selected. 0 10 fullduplex when set to 1 , indicates full duplex operation. 0 31:11 - unused 0 table 169. status register (status - address 0x2008 4104) bit description bit symbol function reset value 0 rxstatus if 1, the receive channel is active. if 0, the receive channel is inactive. 0 1 txstatus if 1, the transmit channel is active. if 0, the transmit channel is inactive. 0 31:2 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 219 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the status transitions from active to inactive if the channel is disabled by a software reset of the rx/txenable bit in the command regist er and the channel has committed the status and data of the current frame to memory. the status also transitions to inactive if the transmit queue is empty or if the receive queue is full and status and data have been committed to memory. 10.10.2.3 receive descriptor base address register the receive descriptor base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. 10.10.2.4 receive status base address register the receive descriptor base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. the receive status base address is a byte ad dress aligned to a double word boundary i.e. lsb 2:0 are fixed to ?000?. 10.10.2.5 receive number of descriptors register the receive number of descriptors register defines the number of descriptors in the descriptor array for which rxdescriptor is the base address. the number of descriptors should match the number of statuses. the r egister uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.10.2.6 receive produce index register table 170. receive descriptor base address register (rxdescriptor - address 0x2008 4108) bit description bit symbol function reset value 1:0 - fixed to 00 - 31:2 rxdescriptor msbs of receive descriptor base address. 0 table 171. receive status base address register (rxstatus - address 0x2008 410c) bit description bit symbol function reset value 2:0 - fixed to 000 - 31:3 rxstatus msbs of receive status base address. 0 table 172. receive number of desc riptors register (rxdescriptornumber - address 0x2008 4110) bit description bit symbol function reset value 15:0 rxdescriptorn rxdescriptornumber. number of descriptors in the descriptor array for which rxdescriptor is the base address. the number of descriptors is minus one encoded. 0 31:16 - unused 0 table 173. receive produce index register (rxproduceindex - address 0x2008 4114) bit description bit symbol function reset value 15:0 rxproduceix index of the descriptor that is going to be filled next by the receive datapath. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 220 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the receive produ ce index regist er defines the descriptor that is going to be filled next by the hardware receive process. after a frame ha s been received, hardware increments the index. the value is wrapped to 0 once the value of rxdescriptornumber has been reached. if the rxproduceindex equals rxco nsumeindex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.10.2.7 receive consume index register the receive consume register defines the descr iptor that is going to be processed next by the software receive driver. the receive array is empty as long as rxproduceindex equals rxconsumeindex. as soon as the array is not empty, software can process the frame pointed to by rxconsumeindex. after a frame has been processed by software, software should increment the rxconsumeindex. the value must be wrapped to 0 once the value of rxdescriptornumber has been reache d. if the rxproduceindex equals rxconsumeindex - 1, t he array is full and any further frames being received will cause a buffer overrun error. 10.10.2.8 transmit descriptor base address register the transmit descriptor base address is a by te address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of descriptors. 10.10.2.9 transmit status base address register the transmit status base address is a byte address aligned to a word boundary i.e. lsb 1:0 are fixed to ?00?. the register contains the lowest address in the array of statuses. 10.10.2.10 transmit number of descriptors register table 174. receive consume index register (rxconsumeindex - address 0x2008 4118) bit description bit symbol function reset value 15:0 rxconsumeix index of the descriptor that is going to be processed next by the receive 31:16 - unused 0 table 175. transmit descriptor base address register (txdescriptor - address 0x2008 411c) bit description bit symbol function reset value 1:0 - fixed to ?00? - 31:2 txd txdescriptor. msbs of transmit descriptor base address. 0 table 176. transmit status base address register (txstatus - address 0x2008 4120) bit description bit symbol function reset value 1:0 - fixed to ?00? - 31:2 txstat txstatus. msbs of transmit status base address. 0 table 177. transmit number of descriptors register (txdescriptornumber - address 0x2008 4124) bit description bit symbol function reset value 15:0 txdn txdescriptornumber. number of descriptors in the descriptor array for which txdescriptor is the base address. the register is minus one encoded. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 221 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the transmit number of descriptors register defines the number of descriptors in the descriptor array for which txdescriptor is the base address. the number of descriptors should match the number of statuses. the r egister uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. 10.10.2.11 transmit produce index register the transmit produce index register defines the descriptor that is going to be filled next by the software transmit driver. the transmit descriptor array is empty as long as txproduceindex eq uals txconsumeindex. if th e transmit hardware is enabled, it will start transmitting frames as soon as the descriptor array is not empty. after a frame has been processed by software, it should increment the txproduceindex. the value must be wrapped to 0 once the value of txdescriptornumber has been reached. if the txproduceindex equals txconsumeindex - 1 the descriptor array is full and software should stop producing new descriptors unt il hardware has transmitted some frames and updated the txconsumeindex. 10.10.2.12 transmit consume index register the transmit consume index register defines the descriptor that is going to be transmitted next by the hardware transmi t process. after a frame ha s been transmitted hardware increments the index, wrapping the value to 0 once the value of txdescriptornumber has been reached. if the txconsumeindex equa ls txproduceindex the descriptor array is empty and the transmit channel will stop transmitting until so ftware produces new descriptors. 10.10.2.13 transmit status vector 0 register the transmit status vector registers store the most recent transmit status returned by the mac. since the status vector consists of more than 4 bytes, status is distributed over two registers tsv0 and tsv1. these registers ar e provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily through the frame descriptors. the status r egister contents are valid as long as the internal status of the mac is valid and shou ld typically only be read when the transmit and receive processes are halted. table 178. transmit produce index register (txproduceindex - address 0x2008 4128) bit description bit symbol function reset value 15:0 txpi txproduceindex. index of the descriptor that is going to be filled next by the transmit software driver. 0 31:16 - unused 0 table 179. transmit consume index register (txconsumeindex - address 0x2008 412c) bit description bit symbol function reset value 15:0 txci txconsumeindex. index of the descriptor that is going to be transmitted next by the transmit datapath. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 222 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet [1] the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are received, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error i ndication, but simply a statem ent by the chip regarding the status of the received frame. table 180. transmit status vector 0 register (tsv0 - address 0x2008 4158) bit description bit symbol function reset value 0 crcerr crc error. the attached crc in the packet did not match the internally generated crc. 0 1 lce length check error. indicates the frame length field does not match the actual number of data items and is not a type field. 0 2 lor length out of range. indicates that frame type/length field was larger than 1500 bytes. the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are receiv ed, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 0 3 done transmission of packet was completed. 0 4 multicast packet?s destination was a multicast address. 0 5 broadcast packet?s destination was a broadcast address. 0 6 packetdefer packet was deferred for at least one attempt, but less than an excessive defer. 0 7 exdf excessive defer. packet was deferred in excess of 6071 nibble times in 100 mbps or 24287 bit times in 10 mbps mode. 0 8 excol excessive collision. packet was aborted due to exceeding of maximum allowed number of collisions. 0 9 lcol late collision. collision occurred beyond collision window, 512 bit times. 0 10 giant byte count in frame was greater than ca n be represented in the transmit byte count field in tsv1. 0 11 underrun host side caused buffer underrun. 0 27:12 totalbytes the total number of bytes transferred including collided attempts. 0 28 controlframe the frame was a control frame. 0 29 pause the frame was a control frame with a valid pause opcode. 0 30 backpressure carrier-sense method backpressure was previously applied. 0 31 vlan frame?s length/type field contained 0x8100 which is the vlan protocol identifier. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 223 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.14 transmit status vector 1 register the transmit status vector 1 register (tsv1) is a read-only register. the transmit status vector registers store the most recent transm it status returned by the mac. since the status vector consists of more than 4 bytes, status is distributed over two registers tsv0 and tsv1. these registers are provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily through the frame descriptors. the status register contents are valid as long as the internal status of the mac is valid and should typically only be r ead when the transmit and receive processes are halted. table 181. transmit status vector 1 register (tsv1 - address 0x2008 415c) bit description bit symbol function reset value 15:0 tbc transmit byte count. the total number of by tes in the frame, not counting the collided bytes. 0 19:16 tcc transmit collision count. number of collisions the current packet incurred during transmission attempts. the maximum number of collisions (16) cannot be represented. 0 31:20 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 224 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.15 receive status vector register the receive status vector register (rsv) is a read-only register. the receive status vector register stores the most recent receive stat us returned by the mac. this register is provided for debug purposes, because the communication between driver software and the ethernet block takes place primarily throug h the frame descriptors. the status register contents are valid as long as the internal status of the mac is valid and should typically only be read when the transmit and receive processes are halted. table 182. receive status vector register (rsv - address 0x2008 4160) bit description bit symbol function reset value 15:0 rbc received byte count. indicates length of received frame. 0 16 ppi packet previously ignored. indicates that a packet was dropped. 0 17 rxdvseen rxdv event previously seen. indicates that the last receive event seen was not long enough to be a valid packet. 0 18 ceseen carrier event previously seen. indicates that at some time since the last receive statistics, a carrier event was detected. 0 19 rcv receive code violation. indicates that received phy data does not represent a valid receive code. 0 20 crcerr crc error. the attached crc in the packet did not match the internally generated crc. 0 21 lcerr length check error. indicates the frame length field does not match the actual number of data items and is not a type field. 0 22 lor length out of range. indicates that frame type/length field was larger than 1518 bytes. the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are receiv ed, it compares the frame type with the max length and gives the "length out of range" error. in fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame. 0 23 rok receive ok. the packet had valid crc and no symbol errors. 0 24 multicast the packet destination was a multicast address. 0 25 broadcast the packet destination was a broadcast address. 0 26 dribblenibble indicates that after the end of packet another 1-7 bits were received. a single nibble, called dribble nibble, is formed but not sent out. 0 27 controlframe the frame was a control frame. 0 28 pause the frame was a control frame with a valid pause opcode. 0 29 uo unsupported opcode. the current frame was recognized as a control frame but contains an unknown opcode. 0 30 vlan frame?s length/type field contained 0x8100 which is the vlan protocol identifier. 0 31 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 225 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.2.16 flow control counter register 10.10.2.17 flow control status register table 183. flow control counter register (flowcontrolcounter - address 0x2008 4170) bit description bit symbol function reset value 15:0 mc mirrorcounter. in full duplex mode the mirro rcounter specifies the nu mber of cycles before re-issuing the pause control frame. 0 31:16 pt pausetimer. in full-duplex mode the pausetimer specifies the value that is inserted into the pause timer field of a pause flow control frame. in half duplex mode the pausetimer specifies the number of backpressure cycles. 0 table 184. flow control status register (flowcontrolstatus - address 0x2008 4174) bit description bit symbol function reset value 15:0 mcc mirrorcountercurrent. in full duplex mode this register represents the current value of the datapath?s mirror counter which counts up to the value specified by the mirrorcounter field in the flowcontrolcounter register. in half duplex mode the register counts until it reaches the value of the pausetimer bits in the flowcontrolcounter register. 0 31:16 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 226 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.3 receive filter register definitions 10.10.3.1 receive filter control register 10.10.3.2 receive filter wol status register the receive filter wake-up on lan status re gister (rxfilterwolstatus) is a read-only register. the bits in this register record the cause for a wol. bits in rxfilterwolstatus can be cleared by writing the rxfilterwolclear register. table 185. receive filter control register (rxfilterctrl - address 0x2008 4200) bit description bit symbol function reset value 0 aue acceptunicasten. when set to 1, all unicast frames are accepted. 0 1 abe acceptbroadcasten. when set to 1, all broadcast frames are accepted. 0 2 ame acceptmulticasten. when set to 1, all multicast frames are accepted. 0 3 auhe acceptunicasthashen. when set to 1, unicast frames that pass the imperfect hash filter are accepted. 0 4 amhe acceptmulticasthashen. when set to 1, multicast frames that pass the imperfect hash filter are accepted. 0 5 ape acceptperfecten. when set to 1, the frames with a destination address identical to the station address are accepted. 0 11:6 - reserved. read value is undefined, only zero should be written. na 12 mpew magicpacketenwol. when set to 1, the result of the magic packet filter will generate a wol interrupt when there is a match. 0 13 rfew rxfilterenwol. when set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a wol interrupt when there is a match. 0 31:14 - unused 0 table 186. receive filter wol status register (rxfilterwolstatus - address 0x2008 4204) bit description bit symbol function reset value 0 auw acceptunicastwol. when the value is 1, a unicast frames caused wol. 0 1 abw acceptbroadcastwol. when the value is 1, a broadcast frame caused wol. 0 2 amw acceptmulticastwol. when the value is 1, a multicast frame caused wol. 0 3 auhw acceptunicasthashwol. when the value is 1, a unicast frame that passes the imperfect hash filter caused wol. 0 4 amhw acceptmulticasthashwol. when the value is 1, a multicast frame that passes the imperfect hash filter caused wol. 0 5 apw acceptperfectwol. when the value is 1, the perfect address matching filter caused wol. 0 6 - unused 0 7 rfw rxfilterwol. when the value is 1, the receive filter caused wol. 0 8 mpw magicpacketwol. when the value is 1, the magic packet filter caused wol. 0 31:9 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 227 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.3.3 receive filter wol clear register the receive filter wake-up on lan clear regi ster (rxfilterwolclear ) is a write-only register. the bits in this register are write-only; writing resets the corresponding bits in the rxfilterwolstatus register. 10.10.3.4 hash filter table lsbs register details of hash filter table use can be found in section 10.13.10 ? receive filtering ? on page 259 . 10.10.3.5 hash filter table msbs register details of hash filter table use can be found in section 10.13.10 ? receive filtering ? on page 259 . table 187. receive filter wol clear register (rxfilterwolclear - address 0x2008 4208) bit description bit symbol function 0 auwclr acceptunicastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 1 abwclr acceptbroadcastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 2 amwclr acceptmulticastwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 3 auhwclr acceptunicasthashwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 4 amhwclr acceptmulticasthashwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 5 apwclr acceptperfectwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 6 - unused 7 rfwclr rxfilterwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 8 mpwclr magicpacketwolclr. when a 1 is written, the corresponding status bit in the rxfilterwolstatus register is cleared. 31:9 - unused table 188. hash filter table lsbs register (hashfilterl - address 0x2008 4210) bit description bit symbol function reset value 31:0 hfl hashfilterl. bits 31:0 of the imperfect filter hash table for receive filtering. 0 table 189. hash filter msbs register (hashfilterh - address 0x2008 4214) bit description bit symbol function reset value 31:0 hfh bits 63:32 of the imperfect filter hash table for receive filtering. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 228 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4 module control register definitions 10.10.4.1 interrupt status register the interrupt status register (intstatus) is a read-only register.note that all bits are flip-flops with an asynchronous set in order to be able to generate interrupts if there are wake-up events while clocks are disabled. the interrupt status register is read-only. setting can be done via the intset register. reset can be accomplished via the intclear register. table 190. interrupt status register (intstatus - address 0x2008 4fe0) bit description bit symbol function reset value 0 rxoverrunint interrupt set on a fatal overrun error in the receive queue. the fatal interrupt should be resolved by a rx soft-reset. the bit is not set when there is a nonfatal overrun error. 0 1 rxerrorint interrupt trigger on receive errors: alignmenterror, rangeerror, lengtherror, symbolerror, crcerror or nodescriptor or overrun. 0 2 rxfinishedint interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 3 rxdoneint interrupt triggered when a receive descriptor has been processed while the interrupt bit in the control field of the descriptor was set. 0 4 txunderrunint interrupt set on a fatal underrun error in the transmit queue. the fatal interrupt should be resolved by a tx soft-reset. the bit is not set when there is a nonfatal underrun error. 0 5 txerrorint interrupt trigger on transmit erro rs: latecollision, excessivecollision and excessivedefer, nodesc riptor or underrun. 0 6 txfinishedint interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 7 txdoneint interrupt triggered when a descriptor has been transmitted while the interrupt bit in the control field of the descriptor was set. 0 11:8 - unused 0 12 softint interrupt triggered by software writing a 1 to the softintset bit in the intset register. 0 13 wakeupint interrupt triggered by a wake-u p event detected by the receive filter. 0 31:14 - unused 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 229 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4.2 interrupt enable register 10.10.4.3 interrupt clear register the interrupt clear register is write-only. writin g a 1 to a bit of the intclear register clears the corresponding bit in the stat us register. writing a 0 will not affect the interrupt status. table 191. interrupt enable register (int enable - address 0x2008 4f e4) bit description bit symbol function reset value 0 rxoverruninten enable for interrupt trigger on receive buffer overrun or descriptor underrun situations. 0 1 rxerrorinten enable for interrupt trigger on receive errors. 0 2 rxfinishedinten enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 3 rxdoneinten enable for interrupt triggered when a receive descriptor has been processed while the interrupt bit in the control field of the descriptor was set. 0 4 txunderruninten enable for interrupt trigger on transmit buffer or descriptor underrun situations. 0 5 txerrorinten enable for interrupt trigger on transmit errors. 0 6 txfinishedinten enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where produceindex == consumeindex. 0 7 txdoneinten enable for interrupt triggered when a descriptor has been transmitted while the interrupt bit in the control field of the descriptor was set. 0 11:8 - unused 0 12 softinten enable for interrupt triggered by the softint bit in the intstatus register, caused by software writing a 1 to the softintset bit in the intset register. 0 13 wakeupinten enable for interrupt triggered by a wake-up event detected by the receive filter. 0 31:14 - unused 0 table 192. interrupt clear register (intclear - address 0x2008 4fe8) bit description bit symbol function 0 rxoverrunintclr writing a 1 clears the corresponding stat us bit in interrupt status register intstatus. 1 rxerrorintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 2 rxfinishedintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 3 rxdoneintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 4 txunderrunintclr writing a 1 clears the corresponding status bit in inte rrupt status register intstatus. 5 txerrorintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 6 txfinishedintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 7 txdoneintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 11:8 - unused 12 softintclr writing a 1 clears the corresponding status bit in interrupt status register intstatus. 13 wakeupintclr writing a 1 clears the corresponding stat us bit in interrupt stat us register intstatus. 31:14 - unused
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 230 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.10.4.4 interrupt set register the interrupt set register is write-only. writing a 1 to a bit of the intset register sets the corresponding bit in the status register. writing a 0 will not affect the interrupt status. 10.10.4.5 power-down register the power-down register (powerdown) is used to block all ahb accesses except accesses to the power-down register. setting the bit will return an error on all re ad and write accesses on the macahb interface except for accesses to the power-down register. table 193. interrupt set register (intset - address 0x2008 4fec) bit description bit symbol function 0 rxoverrunintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 1 rxerrorintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 2 rxfinishedintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 3 rxdoneintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 4 txunderrunintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 5 txerrorintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 6 txfinishedintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 7 txdoneintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 11:8 - unused 12 softintset writing a 1 to one sets the corresponding status bit in interrupt status register intstatus. 13 wakeupintset writing a 1 to one sets the corresponding status bit in in terrupt status register intstatus. 31:14 - unused table 194. power-down register (powerdown - address 0x2008 4ff4) bit description bit symbol function reset value 30:0 - unused 0 31 pd powerdownmacahb. if true, all ahb accesses will return a read/write error, except accesses to the power-down register. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 231 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.11 descriptor an d status formats this section defines th e descriptor format for the transm it and receive scatter/gather dma engines. each ethernet frame can consist of one or more fragments. each fragment corresponds to a single descriptor. the dma managers in the ethernet block scatter (for receive) and gather (for transmit) multip le fragments for a single ethernet frame. 10.11.1 receive descri ptors and statuses figure 24 depicts the layout of the receive descriptors in memory. receive descriptors are stored in an array in memory. the base address of the array is stored in the rxdescriptor register, and shou ld be aligned on a 4 byte address boundary. the number of descriptors in the array is stor ed in the rxdescriptornumber register using a minus one encoding style e.g. if the array has 8 elements the register value should be 7. parallel to the descriptors there is an array of statuses. for each element of the descriptor array there is an associated status field in the status array. the base address of the status array is stored in the rxstatus register , and must be aligned on an 8 byte address boundary. during operation (when the receiv e data path is enabled) the rxdescriptor, rxstatus and rxdescriptornumber r egisters should not be modified. two registers, rxconsumeindex and rxprodu ceindex, define the descriptor locations that will be used next by hard ware and software. both register s act as counters starting at 0 and wrapping when they reach the value of rxdescriptornumber . the rxproduceindex contains the index of the descriptor that is going to be filled with the next frame being fig 24. receive descriptor memory layout 1 2 3 4 5 statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc statusinfo statushashcrc packet control packet control packet control packet control packet control packet control rxstatus rxdescriptornumber rxdescriptor data buffer data buffer data buffer data buffer data buffer data buffer
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 232 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet received. the rxconsumeindex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. when rxproduceindex == rxconsumeindex, the receive buffer is empty. when rxproduceindex == rxconsumeindex -1 (taking wraparound into ac count), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors. each receive descriptor takes two word loca tions (8 bytes) in memory. likewise each status field takes two words (8 bytes) in me mory. each receive descriptor consists of a pointer to the data buffer for storing receive data (packet) and a control word (control). the packet field has a zero address offset, the control field has a 4 byte address offset with respect to the descriptor address as defined in table 195 . the data buffer pointer (packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. the definiti on of the control word bits is listed in table 196 . table 197 lists the fields in the receive stat us elements from the status array. each receive status consists of two wo rds. the statushashcrc word contains a concatenation of the two 9-bit hash crcs ca lculated from the de stination and source addresses contained in the received frame. after detecting the destination and source addresses, statushashcrc is calculated once, then held for every fragment of the same frame. the concatenation of the two crcs is shown in table 198 : table 195. receive descriptor fields symbol address offset bytes description packet 0x0 4 base address of the data buffer for storing receive data. control 0x4 4 control information, see table 196 . table 196. receive descriptor control word bit symbol description 10:0 size size in bytes of the data buffer. this is the size of the buffer reserved by the device driver for a frame or frame fragment i.e. the byte size of the buffer pointed to by the packet field. the size is -1 encoded e.g. if the buffer is 8 bytes the size field should be equal to 7. 30:11 - unused 31 interrupt if true generate an rxdone interrupt when the dat a in this frame or frame fragment and the associated status information has been committed to memory. table 197. receive status fields symbol address offset bytes description statusinfo 0x0 4 receive status return flags, see table 199 . statushashcrc 0x4 4 the concatenation of the destination address hash crc and the source address hash crc.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 233 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the statusinfo word contains flags returned by the mac and flags generated by the receive data path reflecting the status of the reception. ta b l e 1 9 9 lists the bit definitions in the statusinfo word. [1] the emac doesn't distinguish the frame type and frame length, so, e.g. when the ip(0x8000) or arp(0x0806) packets are received, it compares the frame type with the max length and gives the "range" error. in fact, this bit is not an erro r indication, but simply a statement by the chip regarding the status of the received frame. table 198. receive status hashcrc word bit symbol description 8:0 sahashcrc hash crc calculated from the source address. 15:9 - unused 24:16 dahashcrc hash crc calculated from the destination address. 31:25 - unused table 199. receive status information word bit symbol description 10:0 rxsize the size in bytes of the actual data transferred into one fragment buffer. in other words, this is the size of the frame or fragment as actually writt en by the dma manager for one descriptor. this may be different from the size bits of the control field in the descriptor that indicate the size of the buffer allocated by the device driver. size is -1 encoded e. g. if the buffer has 8 bytes the rxsize value will be 7. 17:11 - unused 18 controlframe indicates this is a control frame for flow control, either a pause frame or a frame with an unsupported opcode. 19 vlan indicates a vlan frame. 20 failfilter indicates this frame has failed the rx filter. these frames will not normally pass to memory. but due to the limitation of the size of the buffer, part of this frame may already be passed to memory. once the frame is found to have failed the rx filter, the remainder of the frame will be discarded without being passed to the memory. however, if the passrxfilter bit in the command register is set, the whole frame will be passed to memory. 21 multicast set when a multicast frame is received. 22 broadcast set when a broadcast frame is received. 23 crcerror the received frame had a crc error. 24 symbolerror the phy reports a bit error over the phy interface during reception. 25 lengtherror the frame length field value in the frame specifies a valid length, but does not match the actual data length. 26 rangeerror [1] the received packet exceeds the maximum packet size. 27 alignmenterror an alignment error is flagged when dribble bits are detected and also a crc error is detected. this is in accordance with ieee std. 802.3/clause 4.3.2. 28 overrun receive overrun. the adapter can not accept the data stream. 29 nodescriptor no new rx descriptor is available and the frame is too long for the buffer size in the current receive descriptor. 30 lastflag when set to 1, indicates this descriptor is for the last fragment of a frame. if the frame consists of a single fragment, this bit is also set to 1. 31 error an error occurred during reception of this frame. this is a logical or of alignmenterror, rangeerror, lengtherror, symbolerror, crcerror, and overrun.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 234 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet for multi-fragment frames, the value of t he alignmenterror, rangeerror, lengtherror, symbolerror and crcerror bits in all but the la st fragment in the frame will be 0; likewise the value of the failfilter, multicast, broadcast, vlan and controlframe bits is undefined. the status of the last fragme nt in the frame will copy the value for these bits from the mac. all fragment statuses will have valid lastfrag, rxsize, error, overrun and nodescriptor bits. 10.11.2 transmit descriptors and statuses figure 25 depicts the layout of the transmit descriptors in memory. transmit descriptors are stored in an array in memory. the lowest address of the transmit descriptor array is stored in the txdescriptor register, and must be aligned on a 4 byte address boundary. the number of descriptors in the array is stored in the txdescriptornumber register using a minus on e encoding style i.e. if the array has 8 elements the register value should be 7. parallel to the descriptors there is an array of statuses. for each element of the descriptor arra y there is an associated status field in the status array. the base address of the status ar ray is stored in the txstatus register, and must be aligned on a 4 byte address boundary. during operation (when the transmit data path is enabled) the txdescr iptor, txstatus, and txdescri ptornumber registers should not be modified. two registers, txconsumeindex and txproducei ndex, define the descriptor locations that will be used next by hardware an d software. both register act as counters star ting at 0 and wrapping when they reach the value of txdescriptornumber. the txproduceindex fig 25. transmit descriptor memory layout 1 2 3 4 5 statusinfo statusinfo statusinfo statusinfo statusinfo statusinfo packet control packet control packet control packet control packet control packet control txstatus txdescriptornumber txdescriptor data buffer data buffer data buffer data buffer data buffer data buffer
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 235 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet contains the index of the next descriptor that is going to be filled by the software driver. the txconsumeindex contains the index of t he next descriptor going to be transmitted by the hardware. when txproduceindex == txcons umeindex, the transmit buffer is empty. when txproduceindex == txconsumeindex -1 (taking wraparound into account), the transmit buffer is full and the software dr iver cannot add new descriptors until the hardware has transmitted one or more frames to free up descriptors. each transmit descriptor takes two word locations (8 bytes) in memory. likewise each status field takes one word (4 bytes) in memory. each transmit descriptor consists of a pointer to the data buffer containing transmit data (packet) and a control word (control). the packet field has a zero address offset, whereas the control field has a 4 byte address offset, see table 200 . the data buffer pointer (packet) is a 32-bit, byte aligned address value containing the base address of the data buffer. the definiti on of the control word bits is listed in table 201 . table 202 shows the one field transmit status. the transmit status consists of one word whic h is the statusinfo word. it contains flags returned by the mac and flags generated by the transmit data path reflecting the status of the transmission. table 203 lists the bit definitions in the statusinfo word. table 200. transmit descriptor fields symbol address offset bytes description packet 0x0 4 base address of the data buffer containing transmit data. control 0x4 4 control information, see table 201 . table 201. transmit descriptor control word bit symbol description 10:0 size size in bytes of the data buffer. this is the size of the frame or fragment as it needs to be fetched by the dma manager. in most cases it will be equal to the byte size of the data buffer pointed to by the packet field of the descriptor. size is -1 encoded e.g. a buffer of 8 bytes is encoded as the size value 7. 25:11 - unused 26 override per frame override. if true, bits 30:27 will override the defaults from the mac inte rnal registers. if false, bits 30:27 will be ignored and the defau lt values from the mac will be used. 27 huge if true, enables huge frame, allowing unlimited frame sizes. when false, prevents transmission of more than the maximum frame length (maxf[15:0]). 28 pad if true, pad short frames to 64 bytes. 29 crc if true, append a hardware crc to the frame. 30 last if true, indicates that this is the descriptor for the last fragment in the transmit frame. if false, the fragment from the next descriptor should be appended. 31 interrupt if true, a txdone interrupt will be generated when the data in this frame or frame fragment has been sent and the associated status information has been committed to memory. table 202. transmit status fields symbol address offset bytes description statusinfo 0x0 4 transmit status return flags, see table 203 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 236 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet for multi-fragment frames, the value of the latecollis ion, excessivecollision, excessivedefer, defer and collissi oncount bits in all but the la st fragment in the frame will be 0. the status of the last fragment in the frame will copy th e value for these bits from the mac. all fragment statuses will have valid error, nodescriptor and underrun bits. table 203. transmit status information word bit symbol description 20:0 - unused 24:21 collisioncount the number of collisions this packet incurred, up to the retransmission maximum. 25 defer this packet incurred deferral, because the medium was occupied. this is not an error unless excessive deferral occurs. 26 excessivedefer this packet incurred deferral beyond the maximum deferral limit and was aborted. 27 excessivecollision indica tes this packet exceeded the maximum collision limit and was aborted. 28 latecollision an out of window collision was seen, causing packet abort. 29 underrun a tx underrun occurred due to the adapter not producing transmit data. 30 nodescriptor the transmit stream was interrupted because a descriptor was not available. 31 error an error occurred during transmission. this is a logical or of underrun, latecollision, excessivecollision, and excessivedefer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 237 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.12 ethernet block functional description this section defines the functions of the dma capable 10/100 ethernet mac. after introducing the dma concepts of the etherne t block, and a description of the basic transmit and receive functions, this section el aborates on advanced features such as flow control, receive filtering, etc. 10.12.1 overview the ethernet block can transmit and receive ethernet packets from an off-chip ethernet phy connected through the mii/rmii interface. mii or rmii mode is selected by software. typically during system start-up, the et hernet block will be in itialized. software initialization of the ethernet block should include initializ ation of the descriptor and status arrays as well as the receiver fragment buffers. remark: when initializing the ethernet block, it is important to first configure the phy and insure that reference clocks (enet_ref_clk signal in rmii mode, or both enet_rx_clk and enet_tx_clk signals in mii mode) are present at the external pins and connected to the emac m odule (selecting the appropriate pins using the iocon registers) prior to continuing with ethernet configuration. otherwise the cpu can become locked and no furthe r functionality will be possible. this w ill cause jtag lose communication with the target, if debug mode is being used. to transmit a packet the software driver has to set up the appropriate control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementin g the txproduceindex register. after transmission, hardware will increment txconsumeindex and opt ionally generate an interrupt. the hardware w ill receive packets from the phy and ap ply filtering as configured by the software driver. while receivin g a packet the hardware will read a descri ptor from memory to find the location of the associated receiver data buffer. receive data is written in the data buffer and receive status is returned in the receive descriptor status word. optionally an interrupt can be generated to notify software that a packet has been received. note that the dma manager will prefetch and buffer up to three descriptors. 10.12.2 ahb interface the registers of the ethernet block connect to an ahb slave interface to allow access to the registers from the cpu. the ahb interface has a 32-bit data path, which supports only word accesses and has an address aperture of 4 kb. ta b l e 1 4 8 lists the registers of the ethernet block. all ahb write accesses to registers are posted except for accesses to the intset, intclear and intenable registers. ahb write operations are executed in order. if the powerdown bit of the powerdown regist er is set, all ahb read and write accesses will return a read or write error except for accesses to the powerdown register. bus errors the ethernet block generates errors for several conditions:
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 238 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? the ahb interface will return a read error when there is an ah b read access to a write-only register; likewise a write error is returned when there is an ahb write access to the read-only regist er. an ahb read or write er ror will be returned on ahb read or write accesses to reserved register s. these errors are pr opagated back to the cpu. registers defined as read-only and write-only are identified in ta b l e 1 4 8 . ? if the powerdown bit is set all accesses to ahb registers will re sult in an error response except for accesses to the powerdown register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 239 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13 interrupts the ethernet block has a single interrupt r equest output to the cpu (via the nvic). the interrupt service routine must read the intstatus register to determine the origin of the interrupt. all interrupt statuses can be set by software writing to the intset register; statuses can be cleared by software writing to the intclear register. the transmit and receive data paths can only set interrupt statuses, they cannot clear statuses. the softint interrupt cannot be set by hardware and can be used by software for test purposes. 10.13.1 direct memory access (dma) descriptor arrays the ethernet block includes two dma managers . the dma managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. the dma managers work with arrays of frame de scriptors and statuses that are stored in memory. the descriptors and statuses act as an interface between the ethernet hardware and the device driver software. there is one descriptor array for receive frames and one descriptor array for transmit frames. using buffering for frame descriptors, the memory traffic and memory bandwid th utilization of descrip tors can be kept small. each frame descriptor contains two 32-bit fields: the first field is a pointer to a data buffer containing a frame or a fragment, whereas the second field is a control word related to that frame or fragment. the software driver must write the base addres ses of the descriptor and status arrays in the txdescriptor/rxdescriptor and txstat us/rxstatus registers. the number of descriptors/statuses in each array must be written in the txdescriptornumber/rxdescriptornumber regi sters. the number of descriptors in an array corresponds to the number of statuses in the associated status array. transmit descriptor arrays, receive descriptor arrays and transmit status arrays must be aligned on a 4 byte (32bit)address boundary, while the receive status array must be aligned on a 8 byte (64bit) address boundary. ownership of descriptors both device driver software and ethernet ha rdware can read and write the descriptor arrays at the same time in order to produce and consume descriptors. a descriptor is "owned" either by the device driver or by the ethernet hardware. only the owner of a descriptor reads or writes its value. typi cally, the sequence of use and ownership of descriptors and statuses is as follows: a de scriptor is owned and set up by the device driver; ownership of the descripto r/status is passed by the de vice driver to the ethernet block, which reads the descript or and writes information to the status field; the ethernet block passes ownership of the descriptor back to the device driver, which uses the status information and then recycles the descriptor to be used for another frame. software must pre-allocate the memory used to hold the descriptor arrays.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 240 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet software can hand over ownership of desc riptors and statuses to the hardware by incrementing (and wrapping if on the array boundary) the txproduceindex/rxconsumeindex registers. hardware hands over descriptors and status to software by updating the tx consumeindex/ rxprodu ceindex registers. after handing over a descriptor to the receive and transmit dma hardware, device driver software should not modify the descriptor or reclaim the descriptor by decrementing the txproduceindex/ rxconsumeindex registers because descriptors may have been prefetched by the hardwar e. in this case the de vice driver software will have to wait until the frame has been transmitted or the device driver has to soft-reset the transmit and/or receive data paths which will al so reset the descriptor arrays. sequential order with wrap-around when descriptors are read from and statuses are written to the arrays, this is done in sequential order with wrap-around. sequent ial order means that when the ethernet block has finished reading/writing a descriptor/status, the next descriptor/status it reads/writes is the one at the next higher, adjacent memory address. wrap around means that when the ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descri ptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. full and empty state of descriptor arrays the descriptor arrays can be empty, partially full or full. a descriptor array is empty when all descriptors are owned by the producer. a descriptor array is partially full if both producer and consumer own part of the desc riptors and both are busy processing those descriptors. a descriptor array is full when all descriptors (except one) are owned by the consumer, so that the producer has no more room to process frames. ownership of descriptors is indicated with the use of a consume index and a produce index. the produce index is the first element of the array owned by the producer. it is also the index of the array element that is next going to be used by the producer of frames (it may already be busy using it and subsequent elements). the consume index is the first element of the array that is owned by the co nsumer. it is also the number of the array element next to be consumed by the consumer of frames (it and subsequent elements may already be in the process of being cons umed). if the consume index and the produce index are equal, the descriptor array is empt y and all array elements are owned by the producer. if the consume index equals the prod uce index plus one, then the array is full and all array elements (except the one at the produce index) are owned by the consumer. with a full descriptor array, st ill one array element is kept empty, to be able to easily distinguish the full or empty state by look ing at the value of the produce index and consume index. an array must have at least 2 elements to be able to indicate a full descriptor array with a produce index of va lue 0 and a consume index of value 1. the wrap around of the arrays is taken into accoun t when determining if a descriptor array is full, so a produce index that indicates the last element in the array and a consume index that indicates the first element in the array, also means the descriptor array is full. when the produce index and the consume index are unequal and the consume index is not the produce index plus one (with wrap around taken in to account), then the descriptor array is partially full and both the consumer and producer own enough descriptors to be able to operate actively on the descriptor array. interrupt bit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 241 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the descriptors have an interrupt bit, which is programmed by software. when the ethernet block is processing a de scriptor and finds this bit set, it will allow triggering an interrupt (after committing status to memory ) by passing the rxdoneint or txdoneint bits in the intstatus register to the interrupt output pin. if the interrupt bit is not set in the descriptor, then the rxdoneint or txdoneint ar e not set and no interrupt is triggered (note that the corresponding bits in intenable must al so be set to trigger interrupts). this offers flexible ways of managing the descriptor arra ys. for instance, the device driver could add 10 frames to the tx descriptor array, and set the interrupt bit in descriptor number 5 in the descriptor array. this would invoke the in terrupt service routine before the transmit descriptor array is completely exhausted. th e device driver could add another batch of frames to the descriptor array, without interr upting continuous transmission of frames. frame fragments for maximum flexibility in fram e storage, frames can be split up into multiple frame fragments with fragments located in different places in memory. in this case one descriptor is used for each frame fragment. so, a descriptor can point to a single frame or to a fragment of a frame. by using fragment s, scatter/gather dma can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. by stringing together fragments it is possible to create large frames from small memory areas. another use of fragments is to be able to locate a frame header and frame payload in different places and to concatenate them wi thout copy operations in the device driver. for transmissions, the last bit in the descriptor control field indicates if the fragment is the last in a frame; for receive frames, the lastfr ag bit in the statusinfo field of the status words indicates if the fragment is the last in the frame. if the last(f rag) bit is 0 the next descriptor belongs to the same ethernet frame, if the last(frag) bit is 1 the next descriptor is a new ethernet frame. 10.13.2 initialization after reset, the ethernet software driver n eeds to initialize the ethernet block. during initialization the so ftware needs to: ? remove the soft reset condition from the mac. ? configure the phy via the miim interface of the mac. remark: it is important to configure the ph y and insure that reference clocks (enet_ref_clk signal in rmii mode, or both enet_rx_clk and enet_tx_clk signals in mii mode) are present at the external pins and connected to the emac module (selecting the appropriate pins using the iocon registers) prior to continuing with ethernet configuration. otherwise the cpu can become locked and no further functionality will be possible. this will cause jtag lose communication with the target, if debug mode is being used. ? select mii or rmii mode ? configure the transmit and receive dma e ngines, including the descriptor arrays. ? configure the host registers (mac1,mac2 etc.) in the mac. ? enable the receive and transmit data paths.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 242 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet depending on the phy, the software needs to initialize registers in the phy via the mii management interface. the software can read and write phy regist ers by programming the mcfg, mcmd, madr registers of the mac. write data should be written to the mwtd register; read data and status information can be read from the mrdd and mind registers. the ethernet block supports mii and rmii phys. du ring initialization software must select mii or rmii mode by programming the command register. before switching to rmii mode the default soft reset (mac1 register bit 15) has to be de-asserted. the clock(s) from the phy must be running and internally connected during this operation. transmit and receive dma engines should be in itialized by the device driver by allocating the descriptor and status arrays in memory. transmit and receive functions have their own dedicated descriptor and status arrays. the base addresses of these arrays need to be programmed in the txdescriptor/txstatus a nd rxdescriptor/rxstatus registers. the number of descriptors in an array matc hes the number of statuses in an array. please note that the transmit descriptors, re ceive descriptors and re ceive statuses are 8 bytes each while the transmit statuses are 4 b ytes each. all descriptor arrays and transmit statuses need to be aligned on 4 byte boun daries; receive status arrays need to be aligned on 8 byte boundaries. the number of de scriptors in the descriptor arrays needs to be written to the txdescriptornumber/rxdescr iptornumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the nu mber of descriptors register should be 3. after setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive data path. the packet field of the receive descriptors needs to be filled with the base address of the frame buffer of that descriptor. amongst others the control field in the receiv e descriptor needs to contain the size of the data buffer using -1 encoding. the receive data path has a configurable filter ing function for discardi ng/ignoring specific ethernet frames. the filtering function should also be configured during initialization. after an assertion of the hardwa re reset, the soft reset bit in the mac will be asserted. the soft reset condition must be removed before the ethernet block can be enabled. enabling of the receive function is located in two places. the receive dma manager needs to be enabled and the receive data path of the mac needs to be enabled. to prevent overflow in the receive dma engine the receive dma engine should be enabled by setting the rxenable bit in the command register before enabling the receive data path in the mac by setting the receive enable bit in the mac1 register. the transmit dma engine can be enabled at any time by setting the txenable bit in the command register. before enabling the data paths, several options can be programmed in the mac, such as automatic flow control, transmit to receiv e loop-back for verification, full/half duplex modes, etc. base addresses of descriptor arrays and descriptor array sizes cannot be modified without a (soft) reset of the receive and transmit data paths.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 243 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13.3 transmit process overview this section outlines the transmission process. device driver sets up descriptors and data if the descriptor array is full th e device driver should wait for the descriptor arrays to become not full before writing to a descriptor in the descriptor array. if the descriptor array is not full, the device driver should use t he descriptor numbered txproduceindex of the array pointed to by txdescriptor. the packet pointer in the descriptor is set to po int to a data frame or frame fragment to be transmitted. the size field in the command fi eld of the descriptor should be set to the number of bytes in the fragment buffer, -1 encoded. additional control information can be indicated in the control field in the descriptor (bits interrupt, last, crc, pad). after writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrappi ng) the txproduceindex register. if the transmit data path is disabled, the devi ce driver should not forget to enable the transmit data path by setting the tx enable bit in the command register. when there is a multi-fragment transmission for fragments other than the last, the last bit in the descriptor must be set to 0; for the last fragment the last bit must be set to 1. to trigger an interrupt when the frame has bee n transmitted and transmission status has been committed to memory, set the interrupt bit in the descriptor control field to 1. to have the hardware add a crc in the frame sequence control field of this ethernet frame, set the crc bit in the descriptor. this should be done if the crc has not already been added by software. to enable automatic padding of small frames to the minimum required frame size, set the pad bit in the control field of the descriptor to 1. in typical applications bits crc and pad are both set to 1. the device driver can set up interrupts using the intenable register to wait for a signal of completion from the hardware or can periodically inspect (poll) the progress of transmission. it can also add new frames at the end of the descriptor array, while hardware consumes descriptor s at the start of the array. the device driver can stop the transmit proc ess by resetting the txenable bit in the command register to 0. the transmission will not stop immediately; frames already being transmitted will be transmitte d completely and th e status will be committed to memory before deactivating the data path. the status of the transmit data path can be monitored by the device driver reading the tx status bit in the status register. as soon as the transmit data path is enabled and the corresponding txconsumeindex and txproduceindex are not equal i.e. th e hardware still needs to process frames from the descriptor array, the txstatus bit in th e status register will return to 1 (active). tx dma manager reads the tx descriptor array
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 244 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet when the txenable bit is set, the tx dma manager reads the descriptors from memory at the address determined by txdescriptor and txconsumeindex. the number of descriptors requested is determined by the total number of descriptors owned by the hardware: txproduceindex - txconsumeindex. block transferring descriptors minimizes memory loading. read data returned from memory is buffered and consumed as needed. tx dma manager transmits data after reading the descriptor the transmit dma engine reads the associated frame data from memory and transmits the frame. afte r transfer completion, the tx dma manager writes status information back to the status info and statushashcrc words of the status field. the value of the txcons umeindex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the tx dma manager continues to transmit frames until th e descriptor array is empty. if the transmit descriptor array is empty the txstatus bit in the status register will return to 0 (inactive). if the descriptor array is em pty the ethernet hardware will set the txfinishedint bit of th e intstatus register. the transmit data path will still be enabled. the tx dma manager inspects the last bit of the descriptor control field when loading the descriptor. if the last bit is 0, this indicates th at the frame consists of multiple fragments. the tx dma manager gathers all the fragments fr om the host memory, visiting a string of frame descriptors, and sends th em out as one ethernet frame on the ethernet connection. when the tx dma manager finds a descriptor with the last bit in the control field set to 1, this indicates the last fragment of the fr ame and thus the end of the frame is found. update consumeindex each time the tx dma manager commits a st atus word to memory it completes the transmission of a descriptor and it increm ents the txconsumeindex (taking wrap around into account) to hand the descriptor back to the device driver software. software can re-use the descriptor for new transmissi ons after hardware has handed it back. the device driver software can keep track of the progress of the dma manager by reading the txconsumeindex register to see how far along the transmit process is. when the tx descriptor array is emptied completely, the tx consumeindex register retains its last value. write transmission status after the frame has been transmitted over th e mii/rmii bus, the statusinfo word of the frame descriptor is updated by the dma manager. if the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame transmission, error flags (error, latecollision, excessivecollision, underrun, exce ssivedefer, defer) are set in the status. the collisioncount field is set to the number of collisio ns the frame incurred, up to the retransmissi on maximum programmed in the collis ion window/retry register of the mac. statuses for all but the last fragment in the frame will be writte n as soon as the data in the frame has been accepted by the tx dma manager . even if the descriptor is for a frame fragment other than the last fragment, the error flags are returned via the ahb interface. if the ethernet block detects a transmission error during transmission of a (multi-fragment) frame, all remaining fragments of the frame are still read via the ahb interfac e. after an error, the remaining transmit data is discarde d by the ethernet block. if there are errors
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 245 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet during transmission of a multi-fragment frame the error statuses will be repeated until the last fragment of the frame. st atuses for all bu t the last fragment in the frame will be written as soon as the data in the frame has been accepted by the tx dma manager. these may include error information if the error is detected early enough. the status for the last fragment in the frame will only be written after the transmission has completed on the ethernet connecti on. thus, the status for the last fragment w ill always refl ect any error that occurred anywhere in the frame. the status of the last frame transmission can also be inspected by reading the tsv0 and tsv1 registers. these registers do not report statuses on a fragment basis and do not store information of previously sent fram es. they are provided primarily for debug purposes, because the communication between driver software and the ethernet block takes place through the frame descriptors. the status registers are valid as long as the internal status of the mac is valid and shou ld typically only be read when the transmit and receive processes are halted. transmission error handling if an error occurs during the transmit process, the tx dma manager will report the error via the transmission statusinfo word written in the status array and the intstatus interrupt status register. the transmission can generate several types of errors: late collision, excessivecollision, excessivedefer, underrun, and nodescriptor. all have corresponding bits in the transmission statusinfo word. in addition to the separate bits in the statusinfo word, latecollision, excessivecollisio n, and excessiv edefer are ored together into the error bit of the status. errors are also propagated to the intstatus register; the txerror bit in the intstatus register is set in th e case of a latecollis ion, excessivecollisio n, excessivedefer, or nodescriptor error; underrun errors are re ported in the txunderrun bit of the intstatus register. underrun errors can have three causes: ? the next fragment in a multi-fragment transmissi on is not available. this is a nonfatal error. a nodescriptor status will be returned on the previous fragme nt and the txerror bit in intstatus will be set. ? the transmission fragment data is not available when the ethernet block has already started sending the frame. this is a nonfatal error. an u nderrun status will be returned on transfer and the txerror bit in intstatus will be set. ? the flow of transmission statuses stalls and a new status has to be written while a previous status still waits to be transferred across the memory interface. this is a fatal error which can only be resolved by a soft reset of the hardware. the first and second situations are nonfatal and the device driver has to re-send the frame or have upper software layers re-send the frame. in the third case the hardware is in an undefined state and needs to be soft reset by setting the txreset bit in the command register. after reporting a latecollision, e xcessivecollision, ex cessivedefer or u nderrun error, the transmission of the erroneous frame will be aborted, re maining transmission data and frame fragments will be discar ded and transmission will cont inue with the next frame in the descriptor array.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 246 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet device drivers should catch the transmission errors and take action. transmit triggers interrupts the transmit data path can generate four different interrupt types: ? if the interrupt bit in the de scriptor control field is se t, the tx dma will set the txdoneint bit in the intstatus register after sending the fragment and committing the associated transmission status to memory . even if a descriptor (fragment) is not the last in a multi-fragment frame the interrupt bit in the descriptor can be used to generate an interrupt. ? if the descriptor array is empty while the ethernet hardware is enabled the hardware will set the txfinish edint bit of the in tstatus register. ? if the ahb interface does not consume the tr ansmission statuses at a sufficiently high bandwidth the transmission ma y underrun in which case th e txunderrun bi t will be set in the intstatus register. this is a fatal error which requires a soft reset of the transmission queue. ? in the case of a transmission error (latecollision, exce ssivecollision, or excessivedefer) or a multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (nodescriptor) or in the case of a nonfatal overrun, the hardware will set the txer rorint bit of the intstatus register. all of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the intenable register. enabling or disabling does not affect the intstatus register contents, only the propagatio n of the interrupt status to the cpu (via the nvic). the interrupts, either of individual frames or of the whole list, are a good means of communication between the dma manager and the device driver, triggering the device driver to inspect the status words of descriptors that ha ve been processed. transmit example figure 26 illustrates the transmit pr ocess in an example transmi tting uses a frame header of 8 bytes and a frame payload of 12 bytes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 247 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after reset the values of the dma registers will be zero. du ring initialization the device driver will allocate the descriptor and status array in memory. in this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned on a 4 byte address boundary. the device driver writes the base address of the descriptor array (0x2008 10ec) to the txdescriptor register and the base address of the status array (0x2008 11f8) to the txstatus register. the device driver writes the number of descriptors and statuses minus 1(3) to the txdescri ptornumber register. the descriptors and statuses in the arrays need not be initialized, yet. at this point, the transmit data path may be enabled by setting the txenable bit in the command register. if the transmit data path is enabled while there are no further frames to send the txfinishedint interrupt flag will be set. to reduce the processor interrupt load only the desired interrupts can be enabled by setting the relevant bits in the intenable register. now suppose application software wants to tr ansmit a frame of 12 bytes using a tcp/ip protocol (in real applications frames will be larger than 12 bytes). the tcp/ ip stack will add a header to the frame. the frame header need not be immediately in front of the payload data in memory. the device driver c an program the tx dma to collect header and payload data. to do so, the devi ce driver will progra m the first descriptor to point at the fig 26. transmit example memory and registers statusinfo statusinfo statusinfo statusinfo packet 0x20081314 txstatus 0x200811f8 txdescriptor 0x200810ec 0x200810ec 0x200810f0 0x200810f4 0x200810f8 0x200810fc 0x20081100 0x20081104 0x20081108 0x200811f8 0x200811fc 0x20081200 0x20081204 packet 0x20081411 packet 0x20081419 packet 0x20081324 descriptor array descriptor 0 de s cr i p t o r 1 de scriptor 2 d escriptor 3 descriptor array fragment buffers txproduceindex txconsumeindex txdescriptornumber = 3 status 1 status 0 st atu s 3 st atu s 2 status array status array packet 1 header (8 bytes) packet 0 payload (12 bytes) packet 0 header (8 bytes) 00 7 control control 00 7 control control 11 3 control control 00 7 control control 0x20081314 0x2008131b 0x20081411 0x20081419 0x2008141c 0x20081324 0x2008132b
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 248 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet frame header; the last flag in the descriptor will be set to false/0 to indicate a multi-fragment tran smission. the device driver will progra m the next descriptor to point at the actual payload data. the maximum size of a payload buffer is 2 kb so a single descriptor suffices to describe the payload buffer. for the sake of the example though the payload is distributed across two descriptor s. after the first descriptor in the array describing the header, the second descriptor in the array describes the initial 8 bytes of the payload; the third descriptor in the array de scribes the remaining 4 bytes of the frame. in the third descriptor the last bit in the control word is set to true /1 to indicate it is the last descriptor in the frame. in this example the in terrupt bit in the descriptor control field is set in the last fragment of the frame in order to trigger an interrup t after the transmission completed. the size field in the descriptor?s c ontrol word is set to the number of bytes in the fragment buffer, -1 encoded. note that in real device driv ers, the payload will typically only be split across multiple descriptors if it is more than 2 kb. also note that transmission payload data is forwarded to the hardware without the device driver copying it (zero copy device driver). after setting up the descriptors for the trans action the device driver increments the txproduceindex register by 3 since three descriptors have been programmed. if the transmit data path was not enabled during in itialization the device driver needs to enable the data path now. if the transmit data path is enabled the ethernet block will start transmitting the frame as soon as it detects the txproduceindex is no t equal to txconsumeindex - both were zero after reset. the tx dma will start readin g the descriptors from memory. the memory system will return the descripto rs and the ethernet block w ill accept them one by one while reading the transmit data fragments. as soon as transmission read da ta is returned from memory, the ethernet block will try to start transmission on the ethernet co nnection via the mii/rmii interface. after transmitting each fragment of the fram e the tx dma will writ e the status of the fragment?s transmission. statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the tx dma manager. the status for the last fragment in the frame will only be written after the transmission has completed on the ethernet connection. since the interrupt bit in the descriptor of t he last fragment is set, after committing the status of the last fragment to memory the ethernet block will trigger a txdoneint interrupt, which triggers the device driver to inspect the status information. in this example the device driv er cannot add new descriptor s as long as the ethernet block has not incremented the txconsumeindex because the descriptor array is full (even though one descriptor is not programmed yet). only after the hardwar e commits the status for the first fragment to memory and the txconsumeindex is set to 1 by the dma manager can the device driver program the next (the fo urth) descriptor. the fo urth descriptor can already be programmed before completely transmitting the first frame. in this example the hardware adds the crc to the frame. if the device driver software adds the crc, the crc trailer can be consid ered another frame fragment which can be added by doing another gather dma.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 249 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet each data byte is transmitted across the mii interface as two 4-bit values or the rmii interface as four 2-bit values. the ether net block adds the preamble, frame delimiter leader, and the crc trailer if hardware crc is enabled. once transmission on the mii/rmii interface commences the transmission cannot be interrupted without generating an underrun error, which is why descriptors and data read commands are issued as soon as possible and pipelined. using an mii phy, the data communication between the ethernet block and the phy is done at a 25 mhz rate. with an rmii phy, the data communication between the ethernet block and the phy is at a 50 mhz rate. in 10 mbps mode data will only be transmitted once every 10 clock cycles. 10.13.4 receive process this section outlines the receive process incl uding the activities in the device driver software. device driver sets up descriptors after initializing the receive descriptor and status arrays to receive frames from the ethernet connection, the receive data path should be enabled in the mac1 register and the control register. during initialization, each packet pointer in the descriptors is set to point to a data fragment buffer. the size of the buffer is stor ed in the size bits of the control field of the descriptor. additionally, the control field in th e descriptor has an inte rrupt bit. the interrupt bit allows generation of an interrupt after a fr agment buffer has been filled and its status has been committed to memory. after the initialization and enabling of the receive data path, all descriptors are owned by the receive hardware and should not be modified by the software unless hardware hands over the descriptor by incrementing the rxproduceindex, indicating that a frame has been received. the device driver is allowed to modify the descriptors after a (soft) reset of the receive data path. rx dma manager reads rx descriptor arrays when the rxenable bit in the command register is set, the rx dma manager reads the descriptors from memory at the addr ess determined by rxdescriptor and rxproduceindex. the ethernet block will st art reading descriptors even before actual receive data arrives on the mii/rmii interface (descriptor prefetching). the block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: rxconsumeindex - rxproduceindex - 1. block transferring of descriptors minimizes memory load. read data returned from memory is buffered and consumed as needed. rx dma manager receives data after reading the descriptor, the receive dma engine waits for the mac to return receive data from the mii/rmii interface that passes the receive filter. receive frames that do not match the filtering criteria are not passed to memory. once a frame passes the receive filter, the data is written in the fragment buff er associated with the descriptor. the rx dma does not write beyond the size of the buffer. wh en a frame is received that is larger than a descriptor?s fragment buffer, the frame will be written to multiple fragment buffers of
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 250 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet consecutive descriptors. in the case of a multi- fragment reception, all but the last fragment in the frame will return a status where the la stfrag bit is set to 0. only on the last fragment of a frame the lastfrag bit in the status will be set to 1. if a fragment buffer is the last of a frame, the buffer ma y not be filled comple tely. the first receive data of the next frame will be written to the fragment buffer of the next descriptor. after receiving a fragment, the rx dma manager writes status information back to the statusinfo and statushashcrc words of the stat us. the ethernet block writes the size in bytes of a descriptor?s fragment buffer in the rxsize field of the status word. the value of the rxproduceindex is only updated after th e fragment data and the fragment status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the rx dma manager continues to receive frames until the descriptor array is full. if th e descriptor array is full, th e ethernet hardware will set the rxfinishedint bit of the intstatus register. the receive data path will still be enabled. if the receive descriptor array is full any new receiv e data will generate an overflow error and interrupt. update produceindex each time the rx dma manager commits a data fragment and the associated status word to memory, it completes the reception of a descriptor and increments the rxproduceindex (taking wrap around into account) in order to h and the descriptor back to the device driver software. software can re-use the descriptor for new receptions by handing it back to hardware when the receive data has been processed. the device driver software can keep track of the progress of the dma manager by reading the rxproduceindex register to see how far along the receive process is. when the rx descriptor array is emptied completely, t he rxproduceindex retains its last value. write reception status after the frame has been received from the mii/rmii bus, the statusinfo and statushashcrc words of the frame descrip tor are updated by the dma manager. if the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (error, nodescriptor, overrun, alignmenterror, rangeerror, lengtherror, symbolerror, or crcerror) are set in statusinfo . the rxsize field is set to the number of bytes actually written to the fragment buffer, -1 encoded. for fragments not being the last in the frame the rxsize will match the size of the buffer. the hash crcs of the destination and source addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every statushashcrc wo rd of the statuses associated with the corresponding fragments. if the reception reports an error, any remaining data in the receive frame is discarded and the lastfrag bit will be set in the receive status field, so the error flags in all bu t the last fragment of a frame will always be 0. the status of the last received frame can also be inspected by reading the rsv register. the register does not report statuses on a fragment basis and does not store information of previously received frames. rsv is provi ded primarily for debug purposes, because the communication between driver software and the ethernet block takes place through the frame descriptors. reception error handling
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 251 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet when an error occurs during th e receive process, the rx dma manager w ill report the error via the receive statusinfo written in the status array and the intstatus interrupt status register. the receive process can generate several ty pes of errors: alignmenterror, rangeerror, lengtherror, symbolerror, crcerror, overrun, and nodescriptor. all have corresponding bits in the receive statusinfo. in addition to the separate bits in the statusinfo, alignmenterror, rangeerror, lengtherror, sym bolerror, and crcerror are ored together into the error bit of the statusinfo. errors ar e also propagated to the intstatus register; the rxerror bit in the intstatus register is se t if there is an alignmenterror, rangeerror, lengtherror, symbolerror, crcer ror, or nodescriptor error; nonfatal overrun errors are reported in the rxerror bit of the intstatus re gister; fatal overrun errors are report in the rxoverrun bit of the intstatus register. on fata l overrun errors, the rx data path needs to be soft reset by setting the rxre set bit in the command register. overrun errors can have three causes: ? in the case of a multi-fragment reception, the next descriptor may be missing. in this case the nodescriptor field is set in the stat us word of the previ ous descriptor and the rxerror in the intstatus register is set. this error is nonfatal. ? the data flow on the receiver data interfac e stalls, corrupting the packet. in this case the overrun bit in the status word is set and the rxerror bit in the intstatus register is set. this error is nonfatal. ? the flow of reception statuses stalls an d a new status has to be written while a previous status still waits to be transferred across the memory inte rface. this error will corrupt the hardware state and requires the hardware to be soft reset. the error is detected and sets the overrun bit in the intstatus register. the first overrun situation will result in an incomplete fram e with a nodescriptor status and the rxerror bit in intstatus set. software should discard the partially received frame. in the second over run situation the frame data will be corrupt which results in the overrun status bit being set in the status word while the interror interrupt bit is set. in the third case receive errors cannot be reported in the receiver status arrays which corrupts the hardware state; the er rors will still be reported in the intsta tus register?s overrun bit. the rxreset bit in the command register should be used to soft reset the hardware. device drivers should catch the above receive errors and take action. receive triggers interrupts the receive data path can generate four different interrupt types: ? if the interrupt bit in the de scriptor control field is se t, the rx dma will set the rxdoneint bit in the intstatus register after receiving a fragment and committing the associated data and status to memory. even if a descriptor (fragment) is not the last in a multi-fragment frame, the interrupt bit in the descriptor can be used to generate an interrupt. ? if the descriptor array is full while the ethe rnet hardware is enabled, the hardware will set the rxfinishedint bit of the intstatus register. ? if the ahb interface does not consume receive statuses at a sufficiently high bandwidth, the receive status process may overrun, in which case the rxoverrun bit will be set in the intstatus register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 252 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? if there is a receive error (alignmenterror, rangeerror, lengtherror, symbolerror, or crcerror), or a multi-fragment frame where the device driver did provide descriptors for the initial fragments but did not prov ide the descriptors for the rest of the fragments, or if a nonfatal data overrun oc curred, the hardware w ill set the rxerrorint bit of the intstatus register. all of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the intenable register. enabling or disabling does not affect the intstatus register contents, only the propagatio n of the interrupt status to the cpu (via the nvic). the interrupts, either of individual frames or of the whole list, are a good means of communication between the dma manager and the device driver, triggering the device driver to inspect the status words of descriptors that ha ve been processed. device driver processes receive data as a response to status (e.g. rxdoneint) in terrupts or polling of th e rxproduceindex, the device driver can read the descriptors that ha ve been handed over to it by the hardware (rxproduceindex - rxconsumeindex). the device driver should inspect the status words in the status array to check for multi- fragment receptions and receive errors. the device driver can forwar d receive data and status to upper software layers. after processing of data and status, the descriptors, statuses and data buffers may be recycled and handed back to hardware by in crementing the rxconsumeindex. receive example figure 27 illustrates the receive pr ocess in an example rece iving a frame of 19 bytes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 253 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after reset, the values of the dma registers w ill be zero. during init ialization, the device driver will allocate the descriptor and status array in memory. in this example, an array of four descriptors is allocated; the array is 4x2x4 bytes and aligned on a 4 byte address boundary. since the number of descriptors ma tches the number of statuses, the status array consists of four elements; the array is 4x2x4 bytes and aligned on a 8 byte address boundary. the device driver writes the base address of the descriptor array (0x2008 10ec) in the rxdescriptor register, and the base address of the status array (0x2008 11f8) in the rxstatus register. the de vice driver writes th e number of descriptors and statuses minus 1 (3) in the rxdescri ptornumber register. the descriptors and statuses in the arrays need not be initialized yet. after allocating the descriptors, a fragment buffer needs to be allocated for each of the descriptors. each fragment buffer can be between 1 byte and 2 k bytes. the base address of the fragment buffer is stored in the packet field of the descriptors. the number of bytes in the fragment buffer is stored in the size field of the descriptor control word. the interrupt field in the control word of the descriptor can be set to generate an interrupt as soon as the descriptor ha s been filled by the receive pr ocess. in this example the fragment buffers are 8 bytes, so the value of the size field in the control word of the descriptor is set to 7. note that in this example, the fragment buffers are actually a fig 27. receive example memory and registers packet 0x20081409 rxstatus 0x200811f8 rxdescriptor 0x200810ec 0x200810ec 0x200810f0 0x200810f4 0x200810f8 0x200810fc 0x20081100 0x20081104 0x20081108 0x 2008 11f8 0x 2008 1200 0x 2008 1208 0x 2008 1210 packet 0x20081411 packet 0x20081419 packet 0x20081325 descriptor array de sc ript or 0 descriptor 1 descriptor 2 de scriptor 3 descriptor array fragment buffers rxproduceindex rxconsumeindex rxdescriptornumber = 3 status 1 status 0 status 3 status 2 status array status array fragment 1 buffer (8 bytes) fragment 0 buffer (8 bytes) fragment 2 buffer (3 bytes) fragment 3 buffer (8 bytes) 17 control 17 control 17 control 17 control statusinfo 7 statushashcrc statusinfo 7 statushashcrc statusinfo 7 statushashcrc statusinfo 2 statushashcrc 0x20081409 0x20081410 0x20081411 0x20081418 0x20081325 0x2008132c 0x20081419 0x2008141b
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 254 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet continuous memory space; even when a frame is distributed over mult iple fragments it will typically be in a linear, continuous memory sp ace; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space. the device driver should enable the receive pr ocess by writing a 1 to the rxenable bit of the command register, after which the mac needs to be enabled by writing a 1 to the ?receive enable? bit of the ma c1 configuration register. the ethernet block will now start receiving ethernet frames. to reduce the processor interrupt load, some interrupts can be disabled by setting the relevant bits in the intenable register. after the rx dma manager is enabled, it will start issuing descript or read commands. in this example the number of descriptors is 4. initially the rxproduceindex and rxconsumeindex are 0. since t he descriptor array is consid ered full if rxproduceindex == rxconsumeindex - 1, the rx dma manag er can only read (rxconsumeindex - rxproduceindex - 1 =) 3 de scriptors; note the wrapping. after enabling the receiv e function in the mac, data re ception will begin starting at the next frame i.e. if the receive function is en abled while the mii/rmii interface is halfway through receiving a frame, the frame will be di scarded and reception w ill start at the next frame. the ethernet block will strip the preamble and start of frame delimiter from the frame. if the frame passes the receive filterin g, the rx dma manager will start writing the frame to the first fragment buffer. suppose the frame is 19 bytes long. due to the buffer sizes specified in this example, the frame will be distributed over thr ee fragment buffers. after writ ing the initial 8 bytes in the first fragment buffer, the status for the first fragment buffer will be written and the rx dma will continue filling the second fragment buffer. since this is a multi-fragment receive, the status of the first fragment w ill have a 0 for the la stfrag bit in the statusinfo word; the rxsize field will be set to 7 (8, -1 encod ed). after writing the 8 bytes in the second fragment the rx dma will continue writing th e third fragment. the status of the second fragment will be like the status of the first frag ment: lastfrag = 0, rxsi ze = 7. after writing the three bytes in the third fragment buffer, the end of the frame has been reached and the status of the third fragment is written. the third fr agment?s status will have the lastfrag bit set to 1 and the rxsize equal to 2 (3, -1 encoded). the next frame received from the mii/rmii interface will be written to the fourth fragment buffer i.e. five bytes of the third buffer will be unused. the rx dma manager uses an internal tag protocol in the memory interface to check that the receive data and status have been committed to memory. after the status of the fragments are committed to memory, an rxdo neint interrupt will be triggered, which activates the device driver to inspect the status information. in this example, all descriptors have the inte rrupt bit set in the co ntrol word i.e. all de scriptors will generate an interrupt after committing data and status to memory. in this example the receive function cannot read new descriptors as long as the device driver does not increment the rxconsumeindex, because the de scriptor array is full (even though one descriptor is not programmed yet). only after the device driver has forwarded the receive data to application software, and after the device driver has updated the rxconsumeindex by incremen ting it, will the ethernet bl ock can continue reading descriptors and receive data. the device driver will probably increment the rxconsumeindex by 3, since the driver will forward the co mplete frame consisting of three fragments to the application, and hence free up three descriptors at the same time.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 255 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet each pair of nibbles transferred on the mii in terface (or four pairs of bits for rmii) are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and bu ffer modules. the ethernet block removes preamble, frame start delimiter, and crc from the data and checks the crc. to limit the buffer nodescriptor error proba bility, three descriptors are buffered. the value of the rxproduceindex is only updated after status information has been committed to memory, which is checked by an internal tag protocol in the memory interface. the software device driver will process the receive data, afte r which the device driver will update the rxconsumeindex. for an rmii phy the data between the ethernet block and the phy is communicated at half the data-width and twice the clock frequency (50 mhz). 10.13.5 transmission retry if a collision on the ethernet occurs, it usua lly takes place during the collision window spanning the first 64 bytes of a frame. if collision is detected , the ethernet block will retry the transmission. for this purpose, the first 64 bytes of a frame are buffered, so that this data can be used during the retry. a transmission retry within the first 64 bytes in a frame is fully transparent to the application and device driver software. when a collision occurs outside of the 64 byte collision wi ndow, a latecollision error is triggered, and the transmission is aborted. after a latecollision error, the remaining data in the transmit frame will be discarded. the ethernet block will set the error and latecollision bits in the frame?s status fields. the txerror bit in the intstatus register will be set. if the corresponding bit in the intena ble register is set, the txerror bit in the intstatus register will be propagated to the cpu (via the nvic). the device driver software should catch the interrupt and take appropriate actions. the ?retransmission maximum? field of the clrt register can be used to configure the maximum number of retries before aborting the transmission. 10.13.6 status hash crc calculations for each received frame, the ethernet block is able to detect the destination address and source address and from them calculate the corresponding hash crcs. to perform the computation, the ethernet block features two internal blocks: one is a controller synchronized with the beginning and the end of each frame, the second block is the crc calculator. when a new frame is detected, internal signaling notifies the controller.the controller starts counting the incoming bytes of the frame, which correspond to the destination address bytes. when the sixth (and last) by te is counted, the controller notifies the calculator to store the corresponding 32-bit crc into a first inner register. then the controller repeats counting the next incoming bytes, in order to get synchronized with the source address. when the last byte of the source address is encountered, the controller again notifies the crc calculator, which fr eezes until the next new frame. when the calculator receives this second notification, it stores the present 32-bit crc into a second inner register. then the crcs remain frozen in their own registers until new notifications arise.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 256 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the destination address an d source address hash crcs being written in the statushashcrc word are the nine most significant bits of the 32-bit crcs as calculated by the crc calculator. 10.13.7 duplex modes the ethernet block can operate in full duplex and half duplex mode. half or full duplex mode needs to be configured by the device driver software during initialization. for a full duplex connection the fullduplex bit of the command register needs to be set to 1 and the full-duplex bit of the mac2 configuration register needs to be set to 1; for half duplex the same bits need to be set to 0. 10.13.8 iee 802.3/clause 31 flow control overview for full duplex connections, the ethernet block supports ieee 8 02.3/clause 31 flow control using pause frames. this type of flow control may be used in full-duplex point-to-point connections. flow control allows a receiver to stall a transmitter e.g. when the receive buffers are (almost) full. for this purpose, th e receiving side sends a pause frame to the transmitting side. pause frames use units of 512 bit times corresponding to 128 rx_clk/tx_clk cycles. receive flow control in full-duplex mode, th e ethernet block will su spend its transmissions when the it receives a pause frame. rx flow control is initiated by the receiving side of the transmission. it is enabled by setting the ?rx flow control? bit in the mac1 configuration register. if the rx flow control? bit is zero, then the et hernet block ignores received pause control frames. when a pause frame is received on the rx side of the ethernet block, transmission on the tx side w ill be interrup ted after the currently transmitting frame has completed, for an amount of time as indicated in the received pause frame. the transmit data path will stop transmitting data for the nu mber of 512 bit slot times encoded in the pause-timer field of the received pause control frame. by default the received pause control frames are not forwarded to the device driver. to forward the receive flow control frames to the device driver, set the ?pass all receive frames? bit in the mac1 configuration register. transmit flow control if case device drivers need to stall the receive data e.g. because software buffers are full, the ethernet block can transmit pause control frames. transmit flow control needs to be initiated by the device driver software; there is no ieee 802.3/31 flow control initiated by hardware, such as the dma managers. with software flow control, the device driver can detect a situation in which the process of receiving frames needs to be interrupted by sending out tx pause frames. note that due to ethernet delays, a few frames can still be received be fore the flow control takes effect and the receive stream stops.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 257 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet transmit flow control is acti vated by writing 1 to the txfl owcontrol bit of the command register. when the ethernet bl ock operates in fu ll duplex mode, this will result in transmission of ieee 802.3/31 pause frames. the flow control continues until a 0 is written to txflowcontrol bit of the command register. if the mac is operating in full-duplex mode, then setting the txflowcontrol bit of the command register will start a pause frame tr ansmission. the value inserted into the pause-timer value field of transmitted pause frames is programmed via the pausetimer[15:0] bits in the flowcontrolcoun ter register. when the txflowcontrol bit is de-asserted, another pause frame having a p ause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission. when flow control be in force for an extend ed time, a sequence of pause frames must be transmitted. this is supported with a mirr or counter mechanism. to enable mirror counting, a nonzero value is written to the mirrorcounter[15:0] bits in the flowcontrolcounter register. when the txflo wcontrol bit is asserted, a pause frame is transmitted. after sending the pause frame, an in ternal mirror counter is initialized to zero. the internal mirror counter starts incrementing one every 512 bit-slot times. when the internal mirror counter re aches the mirrorcounter value, another pause frame is transmitted with pause-timer value equal to the pausetimer field from the flowcontrolcounter register, the internal mirr or counter is reset to zero and restarts counting. the register mirrorcounter[15:0] is usually set to a smaller value than register pausetimer[15:0] to ensure an early expiration of the mirror counter, allowing time to send a new pause frame before the transmission on the other side can resume. by continuing to send pause frames before the transmitting side finishes counting the pause timer, the pause can be extended as long as txflowco ntrol is asserted. this continues until txflowcontrol is de-asserted when a final pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow c ontrol and resume transmission. to disable the mirror counter mechanism, write the value 0 to mirrorcounter field in the flowcontrolcounter register. when using the mirror counter mechanism, account for time-of-flight delays, frame transmission time, queuing delays, crystal frequency tolerances, and response time delays by pr ogramming the mirrorcounter conservatively, typically about 80% of the pausetimer value. if the software device driver sets the mirrorcounter field of the flowcontrolcounter register to zero, the ethernet block will only send one paus e control frame. after sending the pause frame an internal pause counter is in itialized at zero; the internal pause counter is incremented by one every 512 bit-slot time s. once the internal pause counter reaches the value of the pausetimer re gister, the txflowcontrol bit in the command register will be reset. the software device driver can po ll the txflowcontrol bit to detect when the pause completes. the value of the internal counter in the flow control module can be read out via the flowcontrolstatus register. if the mirrorcounter is nonzero, the flowcontrolstatus register will return the value of the internal mirror counter; if the mirrorcounte r is zero the flowcontrolstatus register will return the value of the internal pause counter value. the device driver is allowed to dynamically modify the mirrorcounter register value and switch between zero mirrorcounter and nonzero mirrorcounter modes.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 258 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet transmit flow control is enabled via the ?tx flow control? bit in the mac1 configuration register. if the ?tx flow cont rol? bit is zero, then the mac will not transmit pause control frames, software must not initiate pause frame transmissions, and the txflowcontrol bit in the command register should be zero. transmit flow control example figure 28 illustrates the transmit flow control. in this example, a frame is received while transmitting another frame (full duplex.) the device driver detects that some buffer migh t overrun and enables the transmit flow control by programming the pausetimer and mirrorcounter fields of the flowcontrolcounter register, after which it enables the transmit flow control by setting the txflowcontrol bit in the command register. as a response to the enabling of the flow control a pause co ntrol frame will be sent after the currently transmitting frame has been transmitted. when the pause frame transmission completes the internal mirror counter will start counting bit slots; as soon as the counter reaches the value in the mirrorcounter field another pause frame is transmitted. while counting the transmit da ta path will continue normal transmissions. as soon as software disables transmit fl ow control a zero pause control frame is transmitted to resume the receive process. 10.13.9 half-duplex mode backpressure when in half-duplex mode, backpressure can be generated to stall receive packets by sending continuous preamble that basically ja ms any other transmissions on the ethernet medium. when the ethernet block operates in half duplex mode, asserting the txflowcontrol bit in the comman d register will result in applying cont inuous preamble on the ethernet wire, effectively blocking traffic from any other ethernet station on the same segment. fig 28. transmit flow control mirrorcounter (1/515 bit slots) 400 0 150 300 200 450 350 250 50 100 500 pausetimer mirrorcounter txflowctl clear txflowctl pause control frame transmission pause control frame transmission pause control frame transmission normal transimisson normal receive normal transmission normal receive rmii receive rmii transmit device driver register writes pause in effect
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 259 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet in half duplex mode, when the txflowcontrol bit goes high, continuous preamble is sent until txflowcontrol is de-asserted. if the me dium is idle, the ethernet block begins transmitting preamble, which rais es carrier sense causing all ot her stations to defer. in the event the transmitting of preamble causes a co llision, the backp ressure ?rides through? the collision. the colliding station ba cks off and then defers to the backpressure. if during backpressure, the user wishes to send a frame, the backpressure is interrupted, the frame sent and then the backpressure resumed. if txflowcontrol is asserted for longer than 3.3 ms in 10 mbps mode or 0.33 ms in 100 m bps mode, backpressure will cease sending preamble for several byte times to avoid the jabber limit. 10.13.10 receive filtering features of receive filtering the ethernet mac has several receive packet filtering functions that can be configured from the software driver: ? perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. ? hash table filter: allows imperfect filteri ng of packets based on the station address. ? unicast/multicast/broadcast filt ering: allows passing of a ll unicast, mult icast, and/or broadcast packets. ? magic packet filter: detection of magic packets to generate a wake-on-lan interrupt. the filtering functions can be logically comb ined to create complex filtering functions. furthermore, the ethernet block can pass or reject runt packets smaller than 64 bytes; a promiscuous mode allows all pack ets to be passed to software. overview the ethernet block has the capab ility to filter out receive fram es by analyzing the ethernet destination address in the frame. this capab ility greatly reduces t he load on the host system, because ethernet frames that are ad dressed to other stations would otherwise need to be inspected and rejected by the device driver software, using up bandwidth, memory space, and host cpu time. address filtering can be implemented using the perfect address filter or the (imperfect) hash filter. the latter produces a 6-bit hash code which can be used as an index into a 64 entry programmable hash table. figure 29 depicts a functional view of the receive filter. at the top of the diagram the ethernet receiv e frame enters the filters. each filter is controlled by signals from control registers; each filter produces a ?ready? output and a ?match? output. if ?ready? is 0 then the match value is ?don?t care?; if a filter finishes filtering then it will assert its ready ou tput; if the filter finds a ma tching frame it will assert the match output along with the ready output. the results of the filters are combined by logic functions into a single rxabor t output. if the rxabor t output is asserted, the frame does not need to be received. in order to reduce memory tr affic, the receive data path has a buffer of 68 bytes. the ethernet mac will only start writ ing a frame to memory after 68 byte delays. if the rxabort signal is asserted during the initial 68 bytes of the frame, the frame can be discarded and removed from the buffer and not stored to memory at all, not using up receive descriptors, etc. if the rxabort signal is asserted after the initial 68 bytes in a frame (probably due to reception of a magic packet), part of the frame is already written to memory and the
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 260 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ethernet mac will stop writing furt her data in the fram e to memory; the failfilter bit in the status word of the frame will be set to indicate that the soft ware device driver can discard the frame immediately. unicast, broadcast and multicast generic filtering based on the type of fr ame (unicast, multicast or broadcast) can be programmed using the acceptunic asten, acceptmulticasten, or acceptbroadcasten bits of the rxfilterctrl register. setting th e acceptunicast, acceptmulticast, and acceptbroadcast bits causes all frames of types unicast, multicast and broadcast, respectively, to be accepted, ignoring the ethernet destination address in the frame. to program promiscuous mode, i.e. to accept all frames, set all 3 bits to 1. perfect address match when a frame with a unicast destination addres s is received, a perfect filter compares the destination address with the 6 byte station address programmed in the station address registers sa0, sa1, sa2. if the acceptperfecten bi t in the rxfilterctrl register is set to 1, and the address matches, the frame is accepted. imperfect hash filtering fig 29. receive filter block diagram imperfect hash filter acceptunicasten acceptmulticasten acceptmulticasthashen acceptunicasthashen hashfilter perfect address filter packet crc ok? hfready hfmatch pare ady pamatch rxabort fready fmatch rxfilterenwol rxfilterwol stationaddress acceptperfecten
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 261 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet an imperfect filter is available, based on a hash mechanism. this filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. the advantage of th is type of filter is that a small table can cover any possible address. the disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded. ? hash function: ? the standard ethernet cyclic redundancy c heck (crc) function is calculated from the 6 byte destination address in the ethernet frame (this crc is calculated anyway as part of calculating the crc of the whole frame), then bits [28:23] out of the 32-bit crc result are taken to form the hash. the 6-bit hash is used to access the hash table: it is used as an index in t he 64-bit hashfilter register that has been programmed with accept values. if the selected accept value is 1, the frame is accepted. ? the device driver can initialize the hash filter table by writing to the registers hashfilterl and hashfilterh. hashfilterl contains bits 0 through 31 of the table and hashfilterh contains bit 32 through 63 of the table. so, hash value 0 corresponds to bit 0 of the hashfilterl register and hash value 63 corresponds to bit 31 of the hashfilterh register. ? multicast and unicast ? the imperfect hash filter can be applied to multicast addresse s, by setting the acceptmulticasthashen bit in the rxfilter register to 1. ? the same imperfect hash filter that is ava ilable for multicast addresses can also be used for unicast addresses. this is useful to be able to respond to a multitude of unicast addresses without enabling all unicast addresses. the hash filter can be applied to unicast addresses by settin g the acceptunicasth ashen bit in the rxfilter register to 1. enabling and disabling filtering the filters as defined in the sections above can be bypassed by setting the passrxfilter bit in the command register. wh en the passrxfilter bit is se t, all receive frames will be passed to memory. in this case the device driver software has to implement all filtering functionality in software. setting the passrxfilter bit does not affect the runt frame filtering as defined in the next section. runt frames a frame with less than 64 bytes (or 68 byte s for vlan frames) is shorter than the minimum ethernet frame size and therefore c onsidered erroneous; they might be collision fragments. the receive data path automatically filters and discards these runt frames without writing them to memory and using a receive descriptor. when a runt frame has a correct crc there is a po ssibility that it is intended to be useful. the device driver can receive the runt frames with correct crc by setting the passruntframe bit of the command register to 1. 10.13.11 power management the ethernet block supports power management by means of clock switching. all clocks in the ethernet core can be switched off. if wake-up on lan is needed, the rx_clk should not be switched off.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 262 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13.12 wake-up on lan overview the ethernet block supports power management with remote wake-up over lan. the host system can be powered down, even including part of the ethernet block itself, while the ethernet block continues to listen to packets on the lan. appropriately formed packets can be received and recognized by th e ethernet block and used to trigger the host system to wake up from its power-down state. wake-up of the system takes effect through an interrupt. when a wake-up event is detected, the wakeupint bit in th e intstatus register is set. th e interrupt stat us will trigger an interrupt if the corresponding wakeupinten bit in the intenable register is set. this interrupt should be used by system power management logic to wake up the system. while in a power-down state the packet that generates a wake-up on lan event is lost. there are two ways in which ethernet pack ets can trigger wake-up events: generic wake-up on lan and magic packet. magic packet filtering uses an additional filter for magic packet detection. in both cases a wa ke-up on lan event is only triggered if the triggering packet has a valid crc. figure 29 shows the generation of the wake-up signal. the rxfilterwolstatus register can be read by the software to inspect the reason for a wake-up event. before going to power-down the power management software should clear the register by writing the rxfilterwolclear register. note: when entering in power-down mode, a receive frame might be not entirely stored into the rx buffer. in this situation, afte r turning exiting power-down mode, the next receive frame is corrupted due to the data of the previous frame being added in front of the last received frame. software drivers have to reset the receive data path just after exiting power-down mode. the following subsections describe the two wake-up on lan mechanisms. filtering for wol the receive filter functionality can be used to generate wake-up on lan events. if the rxfilterenwol bit of the rxfilter ctrl register is set, the receiv e filter will set the wakeupint bit of the intstatus register if a frame is received that passes the f ilter. the interrupt will only be generated if the crc of the frame is correct. magic packet wol the ethernet block supports wake-up using magic packet technology (see ?magic packet technology?, advanced micro devices). a magic packet is a specially formed packet solely intended for wake-up purposes. this packet ca n be received, analyzed and recognized by the ethernet block and used to trigger a wake-up event. a magic packet is a packet that contains in it s data portion the station address repeated 16 times with no breaks or interruptions, preceded by 6 magic packet synchronization bytes with the value 0xff. other data may be surrounding the magic packet pattern in the data portion of the packet. the whole pa cket must be a well-formed ethernet frame.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 263 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the magic packet detection unit analyzes th e ethernet packets, extracts the packet address and checks the payload for the magic packet pattern. the address from the packet is used for matching the pattern (not the address in the sa0/1/2 registers.) a magic packet only sets the wake-up in terrupt status bit if the packet passes the receive filter as illustrated in figure 29 : the result of the receive filter is anded with the magic packet filter result to produce the result. magic packet filtering is enabled by setting the magicpac ketenwol bit of the rxfilterctrl register. note that when doing magic packet wol, the rxfilterenwol bit in the rxfilterctrl register should be 0. setting the rxfilterenwol bit to 1 would accept all packets for a matching address, not just the magic packets i.e. wol using magic packets is more strict. when a magic packet is detected, apart from the wakeupint bit in the intstatus register, the magicpacketwol bit is set in the rxfilter wolstatus register. software can reset the bit writing a 1 to the corresponding bit of the rxfilterwolclear register. example: an example of a magic packet with station address 0x11 0x22 0x33 0x44 0x55 0x66 is the following (misc indicates miscellaneous additional data bytes in the packet): ff ff ff ff ff ff 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 10.13.13 enabling and disabl ing receive and transmit enabling and disabling reception after reset, the receive function of the ethern et block is disabled. the receive function can be enabled by the device driver setting the rxenable bit in the command register and the ?receive enable? bit in the mac1 configuration register (in that order). the status of the receive data path can be monitored by the device driver by reading the rxstatus bit of the status register. figure 30 illustrates the state machine for the generation of the rxstatus bit.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 264 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after a reset, the state machine is in the inactive state. as soon as the rxenable bit is set in the command register, the state machine transitions to the active state. as soon as the rxenable bit is cleared, the state ma chine returns to the inactive state. if the receive data path is busy receiving a packet while the receive data path gets disabled, the packet will be received completely, stored to memory along with its status before returning to the inactive state. also if the receive descriptor array is full, the state machine will return to the inactive state. for the state machine in figure 30 , a soft reset is like a hardware reset assertion, i.e. after a soft reset the receive data path is in active until the data path is re-enabled. enabling and disabling transmission after reset, the transmit function of the ether net block is disabled. the tx transmit data path can be enabled by the device driver setting the txenable bit in the command register to 1. the status of the transmit data paths can be monitored by the device driver reading the txstatus bit of the status register. figure 31 illustrates the state machine for the generation of the txstatus bit. fig 30. receive active/inactive state machine active rxstatus = 1 inactive rxstatus = 0 rxenable = 1 rxenable = 0 and not busy receiving or rxproduceindex = rxconsumeindex - 1 reset
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 265 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet after reset, the state machine is in the inacti ve state. as soon as the txenable bit is set in the command register and the produce and consume indices are not equal, the state machine transitions to the active state. as so on as the txenable bit is cleared and the transmit data path has completed all pending transmissions, including committing the transmission status to memory, the state machine returns to the inactive state. the state machine will also return to the inactive state if th e produce and consume indices are equal again i.e. all frames have been transmitted. for the state machine in figure 31 , a soft reset is like a hardware reset assertion, i.e. after a soft reset the transmit data path is inactive until the data path is re-enabled. 10.13.14 transmission padding and crc in the case of a frame of less than 60 byte s (or 64 bytes for vlan frames), the ethernet block can pad the frame to 64 or 68 by tes including a 4 bytes crc frame check sequence (fcs). padding is affected by the value of the ?auto detect pad enable? (adpen), ?vlan pad enable? (vlpen) and ?pad/crc enable? (paden) bits of the mac2 configuration register, as well as th e override and pad bits from the transmit descriptor control word. crc generation is affected by the ?crc enable? (crce) and ?delayed crc? (dcrc) bits of the mac2 co nfiguration register, and the override and crc bits from the transmit descriptor control word. the effective pad enable (epaden) is equal to the ?pad/crc enable? bit from the mac2 register if the override bit in the descriptor is 0. if the override bit is 1, then epaden will be taken from the descriptor pad bit. likewise the effective crc enable (ecrce) equals crce if the override bit is 0, otherwise it equal the crc bit from the descriptor. if padding is required and enabled, a crc will always be appended to the padded frames. a crc will only be appended to the n on-padded frames if ecrce is set. if epaden is 0, the frame w ill not be padded and no crc will be added unless ecrce is set. fig 31. transmit active/inactive state machine active txstatus = 1 inactive txstatus = 0 txenable = 1 and txproduceindex <> txconsumeindex txenable = 0 and not busy transmitting or txproduceindex = txconsumeindex reset
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 266 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet if epaden is 1, then small fr ames will be padded and a crc will always be added to the padded frames. in this case if adpen and vlpen are both 0, then the frames will be padded to 60 bytes and a crc will be added creating 64 bytes frames; if vlpen is 1, the frames will be padded to 64 bytes and a crc will be added creating 68 bytes frames; if adpen is 1, while vlpen is 0 vlan fram es will be padded to 64 bytes, non vlan frames will be padded to 60 bytes, and a crc will be added to padde d frames, creating 64 or 68 bytes padded frames. if crc generation is enabled, crc generation ca n be delayed by four bytes by setting the delayed crc bit in the mac2 register, in order to skip proprietary header information. 10.13.15 huge frames and frame length checking the ?huge frame enable? bit in the mac2 configuration register can be set to 1 to enable transmission and reception of frames of any length. huge frame transmission can be enabled on a per frame basis by setting the override and huge bits in the transmit descriptor control word. when enabling huge frames, the ethernet block will not che ck frame length s and report frame length errors (rangeerror and lengtherror). if huge frames are enabled, the received byte count in the rsv register may be invalid because the frame may exceed the maximum size; the rxsize fields from the receive status arrays will be valid. frame lengths are checked by comparing the le ngth/type field of the frame to the actual number of bytes in the frame. a lengtherror is reported by setting the corresponding bit in the receive statusinfo word. the maxf register allows the device driver to specify the maximum number of bytes in a frame. the ethernet block w ill compare the actual receive frame to the maxf value and report a rangeerror in th e receive statusinfo word if the frame is larger. 10.13.16 statistics counters generally, ethernet applications maintain ma ny counters that track ethernet traffic statistics. there are a number of standards specifying such counters, such as ieee std 802.3 / clause 30. other standards are rfc 2665 and rfc 2233. the approach taken here is that by default a ll counters are implemented in software. with the help of the statusinfo field in frame stat uses, many of the important statistics events listed in the standards can be counted by software. 10.13.17 mac status vectors transmit and receive status information as det ected by the mac are available in registers tsv0, tsv1 and rsv so that software can poll them. these registers are normally of limited use because the communication between driver software and the ethernet block takes place primarily through frame descriptor s. statistical events can be counted by software in the device driver. however, for de bug purposes the transmit and receive status vectors are made visible. they are valid as long as the internal status of the mac is valid and should typically only be read when th e transmit and receive processes are halted.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 267 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.13.18 reset the ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bits in registers. all registers in the ethernet block have a valu e of 0 after a hard reset, unless otherwise specified. hard reset after a hard reset, all registers will be set to their default value. soft reset parts of the ethernet block can be soft reset by setting bits in the command register and the mac1 configuration register.the mac1 register has six different reset bits: ? soft reset: setting this bit will put all modu les in the mac in reset, except for the mac registers (at addresses 0x000 to 0x0fc). the value of the soft reset after a hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware reset. ? simulation reset: resets the random number generator in the transmit function. the value after a hardware reset assertion is 0. ? reset mcs/rx: setting this bit will reset the mac contro l sublayer (pause frame logic) and the receive function in the mac. the value after a hardware reset assertion is 0. ? reset rx: setting this bit will reset the rece ive function in the mac. the value after a hardware reset assertion is 0. ? reset mcs/tx: setting this bit will rese t the mac control sublayer (pause frame logic) and the transmit function in the mac. the value after a hardware reset assertion is 0. ? reset tx: setting this bit will reset the transmit function of the mac. the value after a hardware reset assertion is 0. the above reset bits must be cleared by software. the command register has three different reset bits: ? txreset: writing a ?1? to the txreset bit will reset the transm it data path, excluding the mac portions, including all (read-only) register s in the transmit data path, as well as the txproduceindex register in the host registers module. a soft reset of the transmit data path will abort all ahb tr ansactions of the transmit da ta path. the reset bit will be cleared autonomous ly by the ethernet block. a soft reset of the tx data path will clear the txstatus bit in the status register. ? rxreset: writing a ?1? to th e rxreset bit will reset the re ceive data path, excluding the mac portions, including all (read-only) regist ers in the receive data path, as well as the rxconsumeindex register in the host registers module. a soft reset of the receive data path will abort all ahb transactions of the receive data path. the reset bit will be cleared autonomously by the ethernet block. a soft re set of the rx data path will clear the rxstatus bit in the status register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 268 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? regreset: resets all of the data paths and registers in the host registers module, excluding the registers in the mac. a soft reset of the registers will also abort all ahb transactions of the transm it and receive data path. the re set bit will be cleared autonomously by the ethernet block. to do a full soft reset of the etherne t block, device driver software must: ? set the ?soft reset? bit in the mac1 register to 1. ? set the regreset bit in the command register, this bit clears automatically. ? re-initialize the mac registers (0x000 to 0x0fc). ? reset the ?soft reset? bit in the mac1 register to 0. to reset just the transmit data path , the device driver software has to: ? set the ?reset mcs/tx? bit in the mac1 register to 1. ? disable the tx dma managers by setting th e txenable bits in the command register to 0. ? set the txreset bit in the command register, this bit clears automatically. ? reset the ?reset mcs/tx? bit in the mac1 register to 0. to reset just the receive data path, the device driver software has to: ? disable the receive function by resetting the ?receive enable? bit in the mac1 configuration register and resetting of the rxenable bit of the command register. ? set the ?reset mcs/rx? bit in the mac1 register to 1. ? set the rxreset bit in the command register, this bit clears automatically. ? reset the ?reset mcs/rx? bit in the mac1 register to 0. 10.13.19 ethernet errors the ethernet block generates erro rs for the following conditions: ? a reception can cause an error: alignmenterror, rangeerror, lengtherror, symbolerror, crcerror, nodescriptor, or overrun. these are reported back in the receive statusinfo and in the inte rrupt status register (intstatus). ? a transmission ca n cause an error: latecollis ion, excessivecollision, excessivedefer, nodescriptor, or unde rrun. these are reported back in the transmission statusinfo and in the in terrupt status register (intstatus).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 269 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.14 ahb bandwidth the ethernet block is connected to an ahb bus which must carry all of the data and control information associated with all ethernet traffic in addition to the cpu accesses required to operate the ethernet block and deal with message contents. 10.14.1 dma access assumptions by making some assumptions, the bandwidt h needed for each type of ahb transfer can be calculated and added in order to find the overall bandwidth requirement. the flexibility of the descriptors used in the et hernet block allows the possibility of defining memory buffers in a range of sizes. in or der to analyze bus bandwidth requirements, some assumptions must be made about these bu ffers. the "worst case" is not addressed since that would involve all desc riptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and ve ry little data. it can easily be shown that the ahb cannot handle the huge amount of bus traffic that would be caused by such a degenerate (and illogical) case. for this analysis, an ethernet packet is assumed to consist of a 64 byte frame. continuous traffic is assumed on both the transmit and receive channels. this analysis does not reflect the flow of ethernet traffic over time, which would include inter-packet gaps in both the transmit an d receive channels that reduce the bandwidth requirements over a larger time frame. types of dma access and their bandwidth requirements the interface to an external ethernet ph y is via rmii. rmii operates at 50 mhz, transferring a byte in 4 clock cycles. the data transfer rate is 12.5 mbps. the interface to an external ethernet phy is via either mii or rmii. an interface mii operates at 25 mhz, tr ansferring a byte in 2 clock cycles . an rmii interface operates at 50 mhz, transferring a byte in 4 clock cycles. the data transfer rate is the same in both cases: 12.5 mbps. the ethernet block initiates dma accesses for the following cases: ? tx descriptor read: ? transmit descriptors occupy 2 words (8 by tes) of memory and are read once for each use of a descriptor. ? two word read happens once every 64 bytes (16 words) of transmitted data. ? this gives 1/8th of the data rate, which = 1.5625 mbps. ? rx descriptor read: ? receive descriptors occupy 2 words (8 byte s) of memory and are read once for each use of a descriptor. ? two word read happens once every 64 bytes (16 words) of received data. ? this gives 1/8th of the data rate, which = 1.5625 mbps. ? tx status write:
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 270 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet ? transmit status occupies 1 word (4 bytes) of memory and is written once for each use of a descriptor. ? one word write happens once every 64 bytes (16 words) of transmitted data. ? this gives 1/16th of the data rate, which = 0.7813 mbps. ? rx status write: ? receive status occupies 2 words (8 bytes) of memory and is written once for each use of a descriptor. ? two word write happens once every 64 bytes (16 words) of received data. ? this gives 1/8 of the data rate, which = 1.5625 mbps. ? tx data read: ? data transmitted in an ethernet frame, the size is variable. ? basic ethernet rate = 12.5 mbps. ? rx data write: ? data to be received in an ethernet frame, the size is variable. ? basic ethernet rate = 12.5 mbps. this gives a total rate of 30.5 mbps for the tr affic generated by the ethernet dma function. 10.14.2 types of cpu access ? accesses that mirror each of the dma access types: ? all or part of status values must be read , and all or part of descriptors need to be written after each use, transmitted data mu st be stored in the memory by the cpu, and eventually received data must be retrieved from the memory by the cpu. ? this gives roughly the same or slightly lower rate as the combined dma functions, which = 30.5 mbps. ? access to registers in the ethernet block: ? the cpu must read the rxproduceindex, txconsumeindex, and intstatus registers, and both read and write th e rxconsumeindex and txproduceindex registers. ? 7 word read/writes once every 64 bytes (16 words) of transmitted and received data. ? this gives 7/16 of the data rate, which = 5.4688 mbps. this gives a total rate of 36 mbps for the traffic generated by the ethernet dma function. 10.14.3 overall bandwidth overall traffic on the ahb is the sum of dma access rates and cpu access rates, which comes to approximately 66.5 mb/s. the peak bandwidth requirement can be somewhat higher due to the use of small memory buffers, in order to hold often used addresses (e.g. the station address) for example. driver software can determine how to build frames in an efficient manner that does not over utilize the ahb.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 271 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet the bandwidth available on the ahb bus de pends on the system clock frequency. as an example, assume that the system clock is se t at 60 mhz. all or nearly all of bus accesses related to the ethernet will be word transfers. th e raw ahb bandwidth can be approximated as 4 bytes per two system clocks, which equals 2 times the system clock rate. with a 60 mhz system clock, the bandwid th is 120 mb/s, giving about 55% utilization for ethernet traffic during simultaneous transmit and receive operations. this shows that it is not necessary to use the maximum cpu frequency for the ethernet to work with plenty of bandwidth headroom.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 272 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet 10.15 crc calculation the calculation is used for several purposes: ? generation the fcs at the end of the ethernet frame. ? generation of the hash table inde x for the hash table filtering. ? generation of the destination and source address hash crcs. the c pseudocode function below calculates the crc on a frame taking the frame (without fcs) and the number of bytes in th e frame as arguments. the function returns the crc as a 32-bit integer. int crc_calc(char frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // crc result int q0, q1, q2, q3; // temporary variables crc = 0xffffffff; for (i = 0; i < frame_len; i++) { byte = *frame_no_fcs++; for (j = 0; j < 2; j++) { if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) { q3 = 0x04c11db7; } else { q3 = 0x00000000; } if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) { q2 = 0x09823b6e; } else { q2 = 0x00000000; } if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) { q1 = 0x130476dc; } else { q1 = 0x00000000; } if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) { q0 = 0x2608edb8; } else { q0 = 0x00000000; } crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0; byte >>= 4; } } return crc; } for fcs calculation, this function is passed a pointer to the first byte of the frame and the length of the frame without the fcs.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 273 of 942 nxp semiconductors UM10562 chapter 10: lpc408x/407x ethernet for hash filtering, this function is passed a pointer to th e destination address part of the frame and the crc is only calculated on the 6 address bytes. the ha sh filter uses bits [28:23] for indexing the 64-bits { hashfilterh, hashfilterl } vector. if the corresponding bit is set the packet is passed, otherwise it is rejected by the hash filter. for obtaining the destination and source address hash crcs, this function calculates first both the 32-bit crcs, then the nine most significant bits from each 32-bit crc are extracted, concatenated, and written in ev ery statushashcrc word of every fragment status.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 274 of 942 11.1 how to read this chapter the lcd controller is available on some lpc408x/407x devices, see section 1.4 for details. 11.2 basic configuration the lcd controller is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pclcd. remark: the lcd is disabled on reset (pclcd = 0). also see section 11.6.12 for power-up procedure. 2. clock: see table 224 and ta b l e 3 4 . 3. pins: select lcd pins and pin modes through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 5. the lcd clock divider is configur ed in the system configuration block ( section 3.3.7.2 ) and the clksel bit in the lcd_pol register ( section 11.7.3 ). 11.3 introduction the lcd controller provides all of the necessary control signals to interface directly to a variety of color and monochrome lcd panels. UM10562 chapter 11: lpc408x/407x lcd controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 275 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.4 features ? ahb bus master interface to access frame buffer. ? setup and control via a separate ahb slave interface. ? dual 16-deep programmable 64-bit wide fifos for buffering incoming display data. ? supports single and dual-panel monochrome super twisted nematic (stn) displays with 4 or 8-bit interfaces. ? supports single and dual-panel color stn displays. ? supports thin film transistor (tft) color displays. ? programmable display resolution including, but not limited to: 320x200, 320x240, 640x200, 640x240, 640x480, 800x600, and 1024x768. ? hardware cursor support for single-panel displays. ? 15 gray-level monochrome, 3375 color stn, and 32k color palettized tft support. ? 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome stn. ? 1, 2, 4, or 8 bpp palettized color displays for color stn and tft. ? 16 bpp true-color non-palettized, for color stn and tft. ? 24 bpp true-color non-palettized, for color tft. ? programmable timing for different display panels. ? 256 entry, 16-bit palette ram, arranged as a 128x32-bit ram. ? frame, line, and pixel clock signals. ? ac bias signal for stn, data enable signal for tft panels. ? supports little and big-endian, and windows ce data formats. ? lcd panel clock may be generated from the peripheral clock, or from a clock input pin. 11.4.1 programmable parameters the following key display and controller parameters can be programmed: ? horizontal front and back porch ? horizontal synchronization pulse width ? number of pixels per line ? vertical front and back porch ? vertical synchroniz ation pulse width ? number of lines per panel ? number of pixel clocks per line ? hardware cursor control. ? signal polarity, active high or low ? ac panel bias ? panel clock frequency ? bits-per-pixel ? display type: stn monoch rome, stn color, or tft
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 276 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller ? stn 4 or 8-bit interface mode ? stn dual or single panel mode ? little-endian, big-endian, or windows ce mode ? interrupt generation event 11.4.2 hardware cursor support the hardware cursor feature reduces software overhead associated with maintaining a cursor image in the lcd frame buffer. without this feature, software needed to: ? save an image of the area un der the next cursor position. ? update the area with the cursor image. ? repair the last cursor position with a previously saved image. in addition, the lcd driver had to check w hether the graphics operation had overwritten the cursor, and correct it. with a cursor size of 64x64 and 24-b it color, each cursor move involved reading and writing approximately 75 kb of data. the hardware cursor removes the requirement for this management by providing a completely separate image buffer for the cursor, and superimposing the cursor image on the lcd output stream at the current cursor (x,y) coordinate. to move the hardware cursor, the software driver supplies a new cursor coordinate. the frame buffer requires no modification. this significantly reduces software overhead. the cursor image is held in the lcd controller in an internal 256x32-bit buffer memory. 11.4.3 types of lcd panels supported the lcd controller supports the following types of lcd panel: ? active matrix tft panels with up to 24-bit bus interface. ? single-panel monochrome stn panels (4-bit and 8-bit bus interface). ? dual-panel monochrome stn panels (4-bit and 8-bit bus interface per panel). ? single-panel color stn panels, 8-bit bus interface. ? dual-panel color stn panels, 8-bit bus interface per panel. 11.4.4 tft panels tft panels support one or more of the following color modes: ? 1 bpp, palettized, 2 colors selected from available colors. ? 2 bpp, palettized, 4 colors selected from available colors. ? 4 bpp, palettized, 16 colors selected from available colors. ? 8 bpp, palettized, 256 colors selected from available colors. ? 12 bpp, direct 4:4:4 rgb.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 277 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller ? 16 bpp, direct 5:5:5 rgb, wi th 1 bpp not normally used. th is pixel is st ill output, and can be used as a brightness bit to connect to the least significant bit (lsb) of rgb components of a 6:6:6 tft panel. ? 16 bpp, direct 5:6:5 rgb. ? 24 bpp, direct 8:8:8 rgb, pr oviding over 16 million colors. each 16-bit palette entry is composed of 5 bpp (rgb), plus a common intensity bit. this provides better memory utilizat ion and performance compared with a full 6 bpp structure. the total number of colors supported can be do ubled from 32k to 64k if the intensity bit is used and applied to all three color components simultaneously. alternatively, the 16 signals can be used to drive a 5:6:5 panel with the extra bit only applied to the green channel. 11.4.5 color stn panels color stn panels support one or more of the following color modes: ? 1 bpp, palettized, 2 colors selected from 3375. ? 2 bpp, palettized, 4 colors selected from 3375. ? 4 bpp, palettized, 16 colors selected from 3375. ? 8 bpp, palettized, 256 colors selected from 3375. ? 16 bpp, direct 4:4:4 rgb, with 4 bpp not being used. 11.4.6 monochrome stn panels monochrome stn panels support one or more of the following modes: ? 1 bpp, palettized, 2 gray scales selected from 15. ? 2 bpp, palettized, 4 gray scales selected from 15. ? 4 bpp, palettized, 16 gray scales selected from 15. more than 4 bpp for monochrome panels can be programmed, but using these modes has no benefit because the maximum number of gr ay scales supported on the display is 15.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 278 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.5 pin description the largest configuration for the lcd controlle r uses 31 pins. there are many variants using as few as 10 pins for a monochrome stn panel. pins are allocated in groups based on the selected configuration. all lcd function s are shared with other chip functions. in table 204 , only the lcd related portion of the pin name is shown. remark: to connect the lcd controller to necessary pins, see section 7.3 . 11.5.1 signal usage the signals that are used for various display types are identified in the following sections. 11.5.1.1 signals used for single panel stn displays the signals used for single panel stn displays are shown in table 205 . ud refers to upper panel data. 11.5.1.2 signals used for dual panel stn displays the signals used for dual panel stn displays are shown in table 206 . ud refers to upper panel data, and ld refers to lower panel data. table 204. lcd controller pins pin name type function lcd_pwr output lcd panel power enable. lcd_dclk output lcd panel clock. each level on this pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. lcd_enab_m output stn ac bias drive or tft data enable output. lcd_fp output frame pulse (stn). vertical synchronization pulse (tft) lcd_le output line end signal lcd_lp output line synchronization pulse (stn). horizontal synchronization pulse (tft) lcd_vd[23:0] output lcd panel data. bits used depend on the panel configuration. lcd_clkin input optional clock input. table 205. pins used for single panel stn displays pin name 4-bit monochrome (10 pins) 8-bit monochrome (14 pins) color (14 pins) lcd_pwr y y y lcd_dclk y y y lcd_enab_m y y y lcd_fp y y y lcd_le y y y lcd_lp y y y lcd_vd[3:0] ud[3:0] ud[3:0] ud[3:0] lcd_vd[7:4] - ud[7:4] ud[7:4] lcd_vd[23:8] - - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 279 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.5.1.3 signals used for tft displays the signals used for tft displays are shown in table 207 . table 206. pins used for dual panel stn displays pin name 4-bit monochrome (14 pins) 8-bit monochrome (22 pins) color (22 pins) lcd_pwr y y y lcd_dclk y y y lcd_enab_m y y y lcd_fp y y y lcd_le y y y lcd_lp y y y lcd_vd[3:0] ud[3:0] ud[3:0] ud[3:0] lcd_vd[7:4] - ud[7:4] ud[7:4] lcd_vd[11:8] ld[3:0] ld[3:0] ld[3:0] lcd_vd[15:12] - ld[7:4] ld[7:4] lcd_vd[23:16] - - - table 207. pins used for tft displays pin name 12-bit, 4:4:4 mode (18 pins) 16-bit, 5:6:5 mode (22 pins) 16-bit, 1:5:5:5 mode (24 pins) 24-bit (30 pins) lcd_pwr y y y y lcd_dclk y y y y lcd_enab_m y y y y l c d _ f p yyyy lcd_le y y y y lcd_lp y y y y lcd_vd[1:0] - - - red[1:0] lcd_vd[2] - - intensity red[2] lcd_vd[3] - red[0] red[0] red[3] lcd_vd[7:4] red[3:0] red[4:1] red[4:1] red[7:4] lcd_vd[9:8] - - - green[1:0] lcd_vd[10] - green[0] intensity green[2] lcd_vd[11] - green[1] green[0] green[3] lcd_vd[15:12] green[3:0] green [5:2] green[4:1] green[7:4] lcd_vd[17:16] - - - blue[1:0] lcd_vd[18] - - intensity blue[2] lcd_vd[19] - blue[0] blue[0] blue[3] lcd_vd[23:20] blue[3:0] blue[4:1] blue[4:1] blue[7:4]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 280 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6 lcd controller fu nctional description the lcd controller performs translation of pixel-coded data into the required formats and timings to drive a variety of single or dual panel monochrome and color lcds. packets of pixel coded data are fed using the ahb interface, to two independent, programmable, 32-bit wide, dma fifos that act as input data flow buffers. the buffered pixel coded data is th en unpacked using a pixel serializer. depending on the lcd type and mode, the unpacked data can represent: ? an actual true display gray or color value. ? an address to a 256x16 bit wide palette ram gray or color value. in the case of stn displays, either a value obtained from the addressed palette location, or the true value is passed to the gray sc aling generators. the hardware-coded gray scale algorithm logic sequences the activity of t he addressed pixels over a programmed number of frames to provide the effective display appearance. for tft displays, either an addressed palette value or true color value is passed directly to the output display drivers, bypass ing the gray scaling algorithmic logic. in addition to data formatting, the lcd controller provides a set of programmable display control signals, including: ? lcd panel power enable. ? pixel clock. ? horizontal and vertical synchronization pulses. ? display bias. the lcd controller generates individual interrupts for: ? upper or lower panel dma fifo underflow. ? base address update signification. ? vertical compare. ? bus error. there is also a single combined interrupt that is asserted when any of the individual interrupts become active. figure 32 shows a simplified block diagram of the lcd controller.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 281 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.1 ahb interfaces the lcd controller includes two separate ahb interfaces. the first, an ahb slave interface, is used primarily by the cpu to access control and data registers within the lcd controller. the second, an ahb master interfac e, is used by the lcd controller for dma access to display data stored in memory elsewhere in the system. the lcd dma controller can only access the peripheral srams and the external memory. 11.6.1.1 amba ahb slave interface the ahb slave interface connects the lcd co ntroller to the ahb bus and provides cpu accesses to the registers and palette ram. 11.6.1.2 amba ahb master interface the ahb master interface transfers display da ta from a selected slave (memory) to the lcd controller dma fifos. it can be configured to obtain data from the peripheral srams, various types of off-chip static memory, or off-chip sdram. fig 32. lcd controller block diagram ahb slave interface ahb master interface ahb bus panel clock generator timing controller lcd panel clock lcd control signals upper panel dma fifo pixel serializer lower panel formatter ram palette (128x32) input fifo control lower panel dma fifo upper panel output fifo lower panel output fifo upper panel formatter upper stn lower stn hardware cursor gray scaler stn/tft data select lcd panel data interrupt generation interrupt fifo underflow ahb error lcdclkin
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 282 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller in dual panel mode, the dma fi fos are filled up in an alte rnating fashion via a single dma request. in single panel mode, the dma fifos are filled up in a sequential fashion from a single dma request. the inherent ahb master interface state machine performs the following functions: ? loads the upper panel base address into the ahb address incrementer on recognition of a new frame. ? monitors both the upper and lower dma fifo levels and asserts a dma request to request display data from memory, filling th em to above the pr ogrammed watermark. the dma request is reasserted when there are at least four locations available in either fifo (dual panel mode). ? checks for 1 kb boundaries during fixed-length bursts, appropriately adjusting the address in such occurrences. ? generates the address sequences for fixed-length and undefined bursts. ? controls the handshaking between the me mory and dma fifos. it inserts busy cycles if the fifos have not completed their synchronization and updating sequence. ? fills up the dma fifos, in dual panel mode, in an alternating fashion from a single dma request. ? asserts the a bus error interrupt if an error occurs during an active burst. ? responds to retry commands by restarting the failed access. this introduces some busy cycles while it re-synchronizes. 11.6.2 dual dma fifos and associated control logic the pixel data accessed from memory is buffered by two dma fifos that can be independently controlled to cover single and dual-panel lcd types. each fifo is 16 words deep by 64 bits wide and can be cascaded to form an effective 32-dword deep fifo in single panel mode. synchronization logic transfers the pixel data from the ahb clock domain to the lcd controller clock domain. the wate r level marks in each fifo are set such that each fifo requests data when at least four locations become available. an interrupt signal is asserted if an attempt is made to read either of the two dma fifos when they are empty (an underflow condition has occurred). 11.6.3 pixel serializer this block reads the 32-bit wide lcd data from the output port of the dma fifo and extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. the lcd controller supports big-endian, little-endian, and windows ce data formats. depending on the mode of operation, the extracted data can be used to point to a color or gray scale value in the palette ram or can actually be a true color value that can be directly applied to an lcd panel input. table 208 through table 210 show the structure of the data in each dma fifo word corresponding to the endianness and bpp combinations. for each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 283 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller table 208. fifo bits for little-endian byte, little-endian pixel order fifo bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 0p 0 p0 p0 p0 p0 p0 1p 1 2p 2 p1 3p 3 4p 4 p2 p1 5p 5 6p 6 p3 7p 7 8p 8 p4 p2 p1 9p 9 10 p10 p5 11 p11 12 p12 p6 p3 13 p13 14 p14 p7 15 p15 16 p16 p8 p4 p2 p1 17 p17 18 p18 p9 19 p19 20 p20 p10 p5 21 p21 22 p22 p11 23 p23 24 p24 p12 p6 p3 25 p25 26 p26 p13 27 p27 28 p28 p14 p7 29 p29 30 p30 p15 31 p31
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 284 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller table 209. fifo bits for big-endian byte, big-endian pixel order fifo bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 0p 3 1 p15 p7 p3 p1 p0 1p 3 0 2p 2 9 p14 3p 2 8 4p 2 7 p13 p6 5p 2 6 6p 2 5 p12 7p 2 4 8p 2 3 p11 p5 p2 9p 2 2 10 p21 p10 11 p20 12 p19 p9 p4 13 p18 14 p17 p8 15 p16 16 p15 p7 p3 p1 p0 17 p14 18 p13 p6 19 p12 20 p11 p5 p2 21 p10 22 p9 p4 23 p8 24 p7 p3 p1 p0 25 p6 26 p5 p2 27 p4 28 p3 p1 p0 29 p2 30 p1 p0 31 p0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 285 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller ta b l e 2 11 shows the structure of the data in each dma fifo word in rgb mode. table 210. fifo bits for little-endian byte, big-endian pixel order fifo bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 0p 7 p3 p1 p0 p0 p0 1p 6 2p 5 p2 3p 4 4p 3 p1 p0 5p 2 6p 1 p0 7p 0 8p 1 5 p7 p3 p1 9p 1 4 10 p13 p6 11 p12 12 p11 p5 p2 13 p10 14 p9 p4 15 p8 16 p23 p11 p5 p2 p1 17 p22 18 p21 p10 19 p20 20 p19 p9 p4 21 p18 22 p17 p8 23 p16 24 p31 p15 p7 p3 25 p30 26 p29 p14 27 p28 28 p27 p13 p6 29 p26 30 p25 p12 31 p24
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 286 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.4 ram palette the ram-based palette is a 256 x 16 bit dual-port ram physically structured as 128 x 32 bits. two entries can be written into the palette from a single word write access. the least significant bit (lsb) of the serialized pixel da ta selects between upper and lower halves of the palette ram. the half that is selected depends on the byte ordering mode. in little-endian mode, setting the lsb selects the upper half, but in big-endian mode, the lower half of the pa lette is selected. table 211. rgb mode data formats fifo data 24-bit rgb 16-bit (1:5:5:5 rgb) 16-bit (5:6:5 rgb) 16-bit (4:4:4 rgb) 0 p0, red 0 p0, red 0 p0, red 0 p0, red 0 1 p0, red 1 p0, red 1 p0, red 1 p0, red 1 2 p0, red 2 p0, red 2 p0, red 2 p0, red 2 3 p0, red 3 p0, red 3 p0, red 3 p0, red 3 4 p0, red 4 p0, red 4 p0, red 4 p0, green 0 5 p0, red 5 p0, green 0 p0, green 0 p0, green 1 6 p0, red 6 p0, green 1 p0, green 1 p0, green 2 7 p0, red 7 p0, green 2 p0, green 2 p0, green 3 8 p0, green 0 p0, green 3 p0, green 3 p0, blue 0 9 p0, green 1 p0, green 4 p0, green 4 p0, blue 1 10 p0, green 2 p0, blue 0 p0, green 5 p0, blue 2 11 p0, green 3 p0, blue 1 p0, blue 0 p0, blue 3 12 p0, green 4 p0, blue 2 p0, blue 1 - 13 p0, green 5 p0, blue 3 p0, blue 2 - 14 p0, green 6 p0, blue 4 p0, blue 3 - 15 p0, green 7 p0 intensity bit p0, blue 4 - 16 p0, blue 0 p1, red 0 p1, red 0 p1, red 0 17 p0, blue 1 p1, red 1 p1, red 1 p1, red 1 18 p0, blue 2 p1, red 2 p1, red 2 p1, red 2 19 p0, blue 3 p1, red 3 p1, red 3 p1, red 3 20 p0, blue 4 p1, red 4 p1, red 4 p1, green 0 21 p0, blue 5 p1, green 0 p1, green 0 p1, green 1 22 p0, blue 6 p1, green 1 p1, green 1 p1, green 2 23 p0, blue 7 p1, green 2 p1, green 2 p1, green 3 24 - p1, green 3 p1, green 3 p1, blue 0 25 - p1, green 4 p1, green 4 p1, blue 1 26 - p1, blue 0 p1, green 5 p1, blue 2 27 - p1, blue 1 p1, blue 0 p1, blue 3 28 - p1, blue 2 p1, blue 1 - 29 - p1, blue 3 p1, blue 2 - 30 - p1, blue 4 p1, blue 3 - 31 - p1 intensity bit p1, blue 4 -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 287 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller pixel data values can be written and verified through the ahb slave interface. for information on the supported colors, refer to the section on the related panel type earlier in this chapter. the palette ram is a dual port ram with independent controls and addresses for each port. port1 is used as a read/write port and is connected to the ahb slave interface. the palette entries can be written and verified thro ugh this port. port2 is used as a read-only port and is connected to the unpacker and gray scaler. for color modes of less than 16 bpp, the palette enables each pixel value to be mapped to a 16-bit color: ? for tft displays, the 16-bit value is passed directly to the pixel serializer. ? for stn displays, the 16-bit value is first converted by the gray scaler. table 212 shows the bit representation of the palette data. the palette 16-bit output uses the tft 1:5:5:5 data format. in 16 and 24 b pp tft mode, the palette is bypassed and the output of the pixel serializer is used as the tft panel data. the red and blue pixel data can be swapped to support bgr data format using a control register bit 8 (bgr). see the lcd_ctrl r egister description for more information. table 213 shows the bit representation of the palette data for the stn color modes. table 212. palette data storage for tft modes. bit(s) name (rgb format) description (rgb format) name (bgr format) description (bgr format) 4:0 r[4:0] red palette data b[4:0] blue palette data 9:5 g[4:0] green palette data g[4:0] green palette data 14:10 b[4:0] blue palette data r[4:0] red palette data 15 i intensity / unused i intensity / unused 20:16 r[4:0] red palette data b[4:0] blue palette data 25:21 g[4:0] green palette data g[4:0] green palette data 30:26 b[4:0] blue palette data r[4:0] red palette data 31 i intensity / unused i intensity / unused table 213. palette data storage for stn color modes. bit(s) name (rgb format) description (rgb format) name (bgr format) description (bgr format) 0 r[0] unused b[0] unused 4:1 r[4:1] red palette data b[4:1] blue palette data 5 g[0] unused g[0] unused 9:6 g[4:1] green palette data g[4:1] green palette data 10 b[0] unused r[0] unused 14:11 b[4:1] blue palette data r[4:1] red palette data 15 i unused i unused 16 - unused - unused 20:17 r[3:0] red palette data b[3:0] blue palette data 21 - unused - unused 25:22 g[3:0] green palette data g[3:0] green palette data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 288 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller for monochrome stn mode, only the red palette field bits [4:1] are used. however, in stn color mode the green and blue [4:1] are also used. only 4 bits per color are used, because the gray scaler only suppo rts 16 different shades per color. table 214 shows the bit representation of th e palette data for the stn monochrome mode. 11.6.5 hardware cursor the hardware cursor is an integral part of the lcd controller. it uses the lcd timing module to provide an indication of the curr ent scan position coordinate, and intercepts the pixel stream between the palette logic and the gray scale/output multiplexer. all cursor programming registers are accessed through the lcd slave interface. this also provides a read/write port to the cursor image ram. 11.6.5.1 cursor operation the hardware cursor is contained in a dual port ram. it is programmed by software through the ahb slave interface. the ahb slav e interface also provides access to the hardware cursor control registers. these registers enable you to modify the cursor position and perform various other functions. when enabled, the hardware cursor uses the horizontal and vertical synchronization signals, along with a pixel clock enable and various display parameters to calculate the current scan coordinate. when the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. when the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image. this enables software controlled animations to be performed without flickering for frame synchronized cursors. 11.6.5.2 cursor sizes two cursor sizes are supported, as shown in table 215 . 26 - unused - unused 30:27 b[3:0] blue palette data r[3:0] red palette data 31 - unused - unused table 214. palette data storage for stn monochrome mode. bit(s) name description 0 - unused 4:1 y[3:0] intensity data 16:5 - unused 20:17 y[3:0] intensity data 31:21 - unused table 213. palette data storage for stn color modes. bit(s) name (rgb format) description (rgb format) name (bgr format) description (bgr format)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 289 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.5.3 cursor movement the following descriptions assume that both the screen and cursor origins are at the top left of the visible screen (the first visible pixel scanned each frame). figure 33 shows how each pixel coordinate is assumed to be the top left corner of the pixel. 11.6.5.4 cursor xy positioning the crsr_xy register controls the cursor position on the cursor overlay (see cursor xy position register). this provides separate fields for x and y ordinates. the crsr_cfg register (see cursor config uration register) provides a framesync bit controlling the visible be havior of the cursor. with framesync inactive, the cursor responds immediately to any change in the programmed crsr_xy value. some transient smearing effects may be visible if the cursor is moved across the lcd scan line. with framesync active, the cursor only updates its position after a vertical synchronization has occurred. this provides clean cursor movement, but the cursor position only updates once a frame. table 215. palette data storage for stn monochrome mode. x pixels y pixels bits per pixel words per line words in cursor image 32 32 2 2 64 64 64 2 4 256 fig 33. cursor movement crsr_xy(x) crsr_xy(y) (0,0)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 290 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.5.5 cursor clipping the crsr_xy register (see cursor xy posi tion register) is programmed with positive binary values that enable the cursor image to be located anywhere on the visible screen image. the cursor image is clipped automati cally at the screen limits when it extends beyond the screen image to the right or bottom (see x1,y1 in figure 34 ). the checked pattern shows the visible portion of the cursor. because the crsr_xy register values are posi tive integers, to emulate cursor clipping on the left and top of screen, a clip positi on register, crsr_clip, is provided. this controls which point of the cursor image is positioned at the crsr _clip coordinate. for clipping functions on the y axis, crsr_xy(x) is zero, and clip(x) is programmed to provide the offset into the cursor image (x2 and x3). the equivalent function is provided to clip on the x axis at the top of the display (y2). for cursors that are not clipped at the x=0 or y=0 lines, program the clip position register x and y fields with zero to display the cursor correctly. see clip(x4,y4) for the effect of incorrect programming. 11.6.5.6 cursor image format the lcd frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only lbbp. this is little-endian byte, big-endian pixel for windows ce mode. fig 34. cursor clipping clip(x2) clip(y2) clip(x3) cursor(y1) cursor(x1) cursor(x5) clip(x4) cursor(y5) clip(y4)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 291 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller the image ram start address is offset by 0x8 00 from the lcd base address, as shown in the register description in this chapter. the displayed cursor coordinate system is expressed in terms of (x,y). 64 x 64 is an extension of the 32 x 32 format shown in figure 35 . 32 by 32 pixel format four cursors are held in memory, each with the same pixel format. table 216 lists the base addresses for the four cursors. table 217 shows the buffer to pi xel mapping for cursor 0. fig 35. cursor image format table 216. addresses for 32 x 32 cursors address description 0x2008 8800 cursor 0 start address. 0x2008 8900 cursor 1 start address. 0x2008 8a00 cursor 2 start address. 0x2008 8b00 cursor 3 start address. (31, 0) (0, 0) (1, 0) (2, 0) (30, 0) (29, 0) (31, 1) (0, 1) (1, 1) (2, 1) (30, 1) (29, 1) (31, 2) (0, 2) (1, 2) (2, 2) (30, 2) (29, 2) right left (31, 29) (0, 29) (1, 29) (2, 29) (30, 29) (29, 29) (31, 30) (0, 30) (1, 30) (2, 30) (30, 30) (29, 30) (31, 31) (0, 31) (1, 31) (2, 31) (30, 31) (29, 31) top bottom
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 292 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 64 by 64 pixel format only one cursor fits in the memory space in 64 x 64 mode, as detailed in table 218 . table 217. buffer to pixel mapping for 32 x 32 pixel cursor format offset into cursor memory data bits 0 4 (8 * y) (8 * y) +4 f8 fc 1:0 (3, 0) (19, 0) (3, y) (19, y) (3, 31) (19, 31) 3:2 (2, 0) (18, 0) (2, y) (18, y) (2, 31) (18, 31) 5:4 (1, 0) (17, 0) (1, y) (17, y) (1, 31) (17, 31) 7:6 (0, 0) (16, 0) (0, y) (16, y) (0, 31) (16, 31) 9:8 (7, 0) (23, 0) (7, y) (23, y) (7, 31) (23, 31) 11:10 (6, 0) (22, 0) (6, y) (22, y) (6, 31) (22, 31) 13:12 (5, 0) (21, 0) (5, y) (21, y) (5, 31) (21, 31) 15:14 (4, 0) (20, 0) (4, y) (20, y) (4, 31) (20, 31) 17:16 (11, 0) (27, 0) (11, y) (27, y) (11, 31) (27, 31) 19:18 (10, 0) (26, 0) (10, y) (26, y) (10, 31) (26, 31) 21:20 (9, 0) (25, 0) (9, y) (25, y) (9, 31) (25, 31) 23:22 (8, 0) (24, 0) (8, y) (24, y) (8, 31) (24, 31) 25:24 (15, 0) (31, 0) (15, y) (31, y) (15, 31) (31, 31) 27:26 (14, 0) (30, 0) (14, y) (30, y) (14, 31) (30, 31) 29:28 (13, 0) (29, 0) (13, y) (29, y) (13, 31) (29, 31) 31:30 (12, 0) (28, 0) (12, y) (28, y) (12, 31) (28,31) table 218. buffer to pixel mapping for 64 x 64 pixel cursor format offset into cursor memory data bits 0 4 8 12 (16 * y) (16 * y) +4 (16 * y) + 8 (16 * y) + 12 fc 1:0 (3, 0) (19, 0) (35, 0) (51, 0) (3, y) (19, y) (35, y) (51, y) (51, 63) 3:2 (2, 0) (18, 0) (34, 0) (50, 0) (2, y) (18, y) (34, y) (50, y) (50, 63) 5:4 (1, 0) (17, 0) (33, 0) (49, 0) (1, y) (17, y) (33, y) (49, y) (49, 63) 7:6 (0, 0) (16, 0) (32, 0) (48, 0) (0, y) (16, y) (32, y) (48, y) (48, 63) 9:8 (7, 0) (23, 0) (39, 0) (55, 0) (7, y) (23, y) (39, y) (55, y) (55, 63) 11:10 (6, 0) (22, 0) (38, 0) (54, 0) (6, y) (22, y) (38, y) (54, y) (54, 63) 13:12 (5, 0) (21, 0) (37, 0) (53, 0) (5, y) (21, y) (37, y) (53, y) (53, 63) 15:14 (4, 0) (20, 0) (36, 0) (52, 0) (4, y) (20, y) (36, y) (52, y) (52, 63) 17:16 (11, 0) (27, 0) (43, 0) (59, 0) (11, y) (27, y) (43, y) (59, y) (59, 63) 19:18 (10, 0) (26, 0) (42, 0) (58, 0) (10, y) (26, y) (42, y) (58, y) (58, 63) 21:20 (9, 0) (25, 0) (41, 0) (57, 0) (9, y) (25, y) (41, y) (57, y) (57, 63) 23:22 (8, 0) (24, 0) (40, 0) (56, 0) (8, y) (24, y) (40, y) (56, y) (56, 63) 25:24 (15, 0) (31, 0) (47, 0) (63, 0) (15, y) (31, y) (47, y) (63, y) (63, 63) 27:26 (14, 0) (30, 0) (46, 0) (62, 0) (14, y) (30, y) (46, y) (62, y) (62, 63) 29:28 (13, 0) (29, 0) (45, 0) (61, 0) (13, y) (29, y) (45, y) (61, y) (61, 63) 31:30 (12, 0) (28, 0) (44, 0) (60, 0) (12, y) (28, y) (44, y) (60, y) (60, 63)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 293 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller cursor pixel encoding each pixel of the cursor requires two bits of information. these are interpreted as color0, color1, transparent, and transparent inverted. in the coding scheme, bit 1 selects between color and transparent (and mask) and bit 0 selects variant (xor mask). table 219 shows the pixel encoding bit assignments. 11.6.6 gray scaler a patented gray scale algorithm drives mono chrome and color stn pa nels. this provides 15 gray scales for monochrome displays. for stn color displa ys, the three color components (rgb) are gray scaled simultaneously. this results in 3375 (15x15x15) colors being available. the gray scaler transf orms each 4-bit gray value into a sequence of activity-per-pixel over several frames, relying to some degree on the display characteristics, to give the representation of gray scales and color. 11.6.7 upper and lower panel formatters formatters are used in stn mode to convert the gray scaler output to a parallel format as required by the display. for monochrome displays, this is either 4 or 8 bits wide, and for color displays, it is 8 bits wide. table 220 shows a color display driven with 2 2/3 pixels worth of data in a repeating sequence. each formatter consists of thre e 3-bit (rgb) shift left registers. rgb pixel data bit values from the gray scaler are concurrently shifted into the res pective registers. when enough data is available, a byte is constructed by mu ltiplexing the registered data to the correct bit position to satisfy the rgb data pattern of lcd panel. the byte is transferred to the 3-byte fifo, which has enough space to store eight color pixels. table 219. pixel encoding value description 00 color0. the cursor color is displayed according to the red-green-blue (rgb) value programmed into the crsr_pal0 register. 01 color1. the cursor color is displayed according to the rgb value programmed into the crsr_pal1 register. 10 transparent. the cursor pixel is transparent, so is displayed unchanged. this enables the visible cursor to assume shapes that are not square. 11 transparent inverted. the cursor pixel assumes the complementary color of the frame pixel that is displayed. this can be used to ensure that the cursor is visible regardless of the color of the frame buffer image. table 220. color display driven with 2 2/3 pixel data byte cld[7] cld[6] cld[5] cld[4] cld[3] cld[2] cld[1] cld[0] 0 p2[green] p2[red] p1[blue] p1[green] p1[red] p0[blue] p0[green] p0[red] 1 p5[red] p4q[blue] p4[green] p4[red] p3[blue] p3[green] p3[red] p2[blue] 2 p7[blue] p7[green] p7[red] p6[blue] p6[green] p6[red] p5[blue] p5[green]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 294 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.8 panel clock generator the output of the panel clock generator block is the panel clock, pin lcd_dclk. the panel clock can be based on either the peripheral clock for the lcd block or the external clock input for the lcd, pin lcd_clkin. whichever source is selected can be divided down in order to produce the internal lcd clock, lcdclk. the panel clock generator can be programmed to output the lcd panel clock in the range of lcdclk/2 to lcdclk/1025 to match the bpp data rate of the lcd panel being used. the clksel bit in the lcd_pol register det ermines whether the base clock used is cclk or the lcd_clkin pin. 11.6.9 timing controller the primary function of the timing controller block is to generate the horizontal and vertical timing panel signals. it also provides the panel bias and enable signals. these timings are all register-programmable. 11.6.10 stn and tft data select support is provided for passive super twis ted nematic (stn) and active thin film transistor (tft) lcd display types: 11.6.10.1 stn displays stn display panels require algorithmic pixe l pattern generation to provide pseudo gray scaling on monochrome displays, or color creation on color displays. 11.6.10.2 tft displays tft display panels require the digital color value of each pixel to be applied to the display data inputs. 11.6.11 interrupt generation four interrupts are generated by the lcd controller, and a single combined interrupt. the four interrupts are: ? master bus error interrupt. ? vertical compare interrupt. ? next base address update interrupt. ? fifo underflow interrupt. each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the lcd_int_msk register. thes e interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked. provision of individual outputs in addition to a combined interrupt output enables use of either a global interrupt service routine, or modular device drivers to handle interrupts. the status of the individual interrupt source s can be read from the lcd_intraw register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 295 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.6.11.1 master bus error interrupt the master bus error interrupt is asserted when an error response is received by the master interface during a transaction with a slave. when such an error is encountered, the master interface enters an error state and remain s in this state until clearance of the error has been signaled to it. when the respective interrupt service rout ine is complete, the master bus error interrupt may be cleared by writing a 1 to the beric bit in the lcd_intclr register. this action releases the master interface from its error state to the start of frame state, and enables fresh frame of data display to be initiated. 11.6.11.2 vertical compare interrupt the vertical compare interrupt asserts when one of four vertical display regions, selected using the lcd_ctrl register, is reached. the interrupt can be made to occur at the start of: ? vertical synchronization. ? back porch. ? active video. ? front porch. the interrupt may be cleared by writing a 1 to the vcompic bit in the lcd_intclr register. 11.6.11.2.1 next base address update interrupt the lcd next base address update interrupt asserts w hen either the lcdupbase or lcdlpbase values have been transferred to the lcdupcurr or lcdlpcurr incrementers respectively. this signals to the system that it is safe to update the lcdupbase or the lcdlpbase registers with new frame base addresses if required. the interrupt can be cleared by writing a 1 to the lnbuic bit in the lcd_intclr register 11.6.11.2.2 fifo underflow interrupt the fifo underflow interrupt asserts when in ternal data is requested from an empty dma fifo. internally, upper and lower panel dm a fifo underflow interrupt signals are generated. the interrupt can be cleared by writing a 1 to the fufic bit in the lcd_intclr register. 11.6.12 lcd power-up an d power-down sequence the lcd controller requires the following power-up sequence to be performed: 1. when power is applied, the following signals are held low: ? lcd_lp ? lcd_dclk ? lcd_fp ? lcd_enab_m ? lcd_vd[23:0] ? lcd_le
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 296 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 2. when lcd power is stabilized, a 1 is written to the lcden bit in t he lcd_ctrl register. this enables the following signals into their active states: ? lcd_lp ? lcd_dclk ? lcd_fp ? lcd_enab_m ? lcd_le the lcd_vd[23:0] signals remain in an inactive state. 3. when the signals in step 2 have stabilized, the contrast voltage (not controlled or supplied by the lcd controller) is applied to the lcd panel. 4. if required, a software or hardware timer can be used to provide the minimum display specific delay time between application of the control signals and power to the panel display. on completion of the time interval, power is applied to the panel by writing a 1 to the lcdpwr bit within the lcd_ctrl register that, in turn, sets the lcd_pwr signal high and enables the lcd_vd[23:0] signals into their active states. the lcd_pwr signal is intended to be used to gate the power to the lcd panel. the power-down sequence is the reverse of the above four steps and must be strictly followed, this time, writing the re spective register bits with 0. figure 36 shows the power-up and power-down sequences. fig 36. power-up and power-down sequences lcdlp, lcdcp, lcdfp, lcdac, lcdle lcd power contrast voltage lcdpwr, lcd[23:0] minimum 0 ms lcd on sequence lcd off sequence minimum 0 ms minimum 0 ms display specific delay display specific delay minimum 0 ms
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 297 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7 register description for lcd configuration and clocking control, see table 34 . [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 221. register overview: lcd controller (base address 0x2008 8000) name access address offset description reset value [1] table timh r/w 0x000 horizontal timing control register 0 222 timv r/w 0x004 vertical timing control register 0 223 pol r/w 0x008 clock and signal polarity control register 0 224 le r/w 0x00c line end control register 0 225 upbase r/w 0x010 upper panel frame base address register 0 226 lpbase r/w 0x014 lower panel fr ame base address register 0 227 ctrl r/w 0x018 lcd control register 0 228 intmsk r/w 0x01c interrupt mask register 0 229 intraw ro 0x020 raw interrupt status register 0 230 intstat ro 0x024 masked interrupt status register 0 231 intclr wo 0x028 interrupt clear register - 232 upcurr ro 0x02c upper panel current address value register 0 233 lpcurr ro 0x030 lower panel current address value register 0 234 pal0 r/w 0x200 256x16-bit color palette registers 0 235 ... to pal127 0x3fc 256x16-bit color palette registers 0 235 crsr_img0 r/w 0x800 cursor image registers 0 236 ... to crsr_img255 0xbfc cursor image registers 0 236 crsr_ctrl r/w 0xc00 cursor control register 0 237 crsr_cfg r/w 0xc04 cursor configuration register 0 238 crsr_pal0 r/w 0xc08 cursor palette register 0 0 239 crsr_pal1 r/w 0xc0c cursor palette register 1 0 240 crsr_xy r/w 0xc10 cursor xy position register 0 241 crsr_clip r/w 0xc14 cursor clip position register 0 242 crsr_intmsk r/w 0xc20 cursor interrupt mask register 0 243 crsr_intclr wo 0xc24 cursor interrupt clear register - 244 crsr_intraw ro 0xc28 cursor raw interrupt status register 0 245 crsr_intstat ro 0xc2c cursor masked interrupt status register 0 246
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 298 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.1 horizontal timing register the lcd_timh register controls the horizontal synchronization pulse width (hsw), the horizontal front porch (hfp) period, the ho rizontal back porch (hbp) period, and the pixels-per-line (ppl). 11.7.1.1 horizontal timing restrictions dma requests new data at the start of a horizontal display line. some time must be allowed for the dma transfer and for data to propagate down the fifo path in the lcd interface. the data path latency forces some restrictions on the usable minimum values for horizontal porch width in stn mode. the minimum values are hsw = 2 and hbp = 2. single panel mode: ? hsw = 3 pixel clock cycles ? hbp = 5 pixel clock cycles ? hfp = 5 pixel clock cycles ? panel clock divisor (pcd) = 1 (lcdclk / 3) dual panel mode: ? hsw = 3 pixel clock cycles ? hbp = 5 pixel clock cycles ? hfp = 5 pixel clock cycles ? pcd = 5 (lcdclk / 7) table 222. horizontal timing register (timh, address 0x2008 8000) bit description bits symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. - 7:2 ppl pixels-per-line. the ppl bit field specifies the number of pixels in each line or row of the screen. ppl is a 6-bit value that represents between 16 and 1024 pixels per line. ppl counts the number of pixel clocks that occur before the hfp is applied. program the value required divided by 16, minus 1. actual pixels-per-line = 16 * (ppl + 1). for example, to obtain 320 pixels per line, program ppl as (320/16) -1 = 19. 0 15:8 hsw horizontal synchronization pulse width. the 8-bit hsw field specifies the pulse width of the line clock in passive mode, or the horizontal synchr onization pulse in active mode. program with desired value minus 1. 0 23:16 hfp horizontal front porch. the 8-bit hfp field sets the number of pixel clock intervals at the end of each line or row of pixels, before the lcd line clock is pulsed. when a complete line of pixels is transmitted to the lcd driver, th e value in hfp counts the number of pixel clocks to wait before asserting the line clock. hfp ca n generate a period of 1-256 pixel clock cycles. program with desired value minus 1. 0 31:24 hbp horizontal back porch. the 8-bit hbp field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. after the line clock for the previous line has been deasserted, the value in hbp counts th e number of pixel clocks to wait before starting the next display line. hbp c an generate a delay of 1-256 pixel clock cycles. program with desired value minus 1. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 299 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller if enough time is given at the start of the line, for example, setting hsw = 6, hbp = 10, data does not corrupt for pcd = 4, the minimum value. 11.7.2 vertical timing register the lcd_timv register controls the vertic al synchronization pulse width (vsw), the vertical front porch (vfp) period, the vertical back porch (vbp) period, and the lines-per-panel (lpp). table 223. vertical timing register (timv, address 0x2008 8004) bit description bits symbol description reset value 9:0 lpp lines per panel. this is the number of acti ve lines per screen. the lpp field specifies the total number of lines or rows on the lcd panel being controlled. lpp is a 10-bit value allowing between 1 and 1024 lines. program the register with the number of lines per lcd panel, minus 1. for dual panel displays, program the register with the number of lines on each of the upper and lower panels. 0 15:10 vsw vertical synchronization pulse width. this is the number of horizontal synchronization lines. the 6-bit vsw field specifies the pulse width of the vertical synchronization pulse. program the register with the number of lines required, minus one. the number of horizontal synchronization lines must be small (for example, program to zero) for passive stn lcds. the higher the value the worse the contrast on stn lcds. 0 23:16 vfp vertical front porch. this is the number of in active lines at the end of a frame, before the vertical synchronization period. the 8-bit vf p field specifies the number of line clocks to insert at the end of each frame. when a complete frame of pixels is transmitted to the lcd display, the value in vfp is used to count the number of line clock periods to wait. after the count has elapsed, the vertical synchronization signal, lcd_fp, is asserted in active mode, or extra line clocks are inse rted as specified by the vsw bit-field in passive mode. vfp generates 0?255 line clock cycles. program to zero on passive displays for improved contrast. 0 31:24 vbp vertical back porch. this is the number of inactive lines at the start of a frame, after the vertical synchronization period. the 8-bit vbp field specifie s the number of line clocks inserted at the beginning of each frame. the vbp count starts immediately after the vertical synchronization signal for the previous frame ha s been negated for active mode, or the extra line clocks have been inserted as specified by the vsw bit field in passive mode. after this has occurred, the count value in vbp sets the number of line clock perio ds inserted before the ne xt frame. vbp generates 0 to 255 extra line clock cycles. program to zero on passive displays for improved contrast. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 300 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.3 clock and signal polarity register the lcd_pol register controls various details of clock timing and signal polarity. table 224. clock and signal polarity register (pol, address 0x2008 8008) bit description bits symbol description reset value 4:0 pcd_lo lower five bits of panel clock divisor. the ten-bit pcd field, comprising pcd_hi (bits 31:27 of this register) and pcd_lo, is used to derive the lcd panel clock frequency lcd_dclk from the input clock, lcd_dclk = lcdclk/(pcd+2). for monochrome stn displays with a 4 or 8-bit interface, the panel clock is a factor of four and eight down from the actual individual pixel clock rate. for color stn displays, 22/3 pixels are output per lcd_dclk cycle, so the panel clock is 0.375 times the pixel rate. for tft displays, the pixel clock divider can be by passed by setting the bcd bit in this register. note: data path latency forces some restrictions on the usable minimum values for the panel clock divider in stn modes: single panel color mode, pcd = 1 (lcd_dclk = lcdclk/3). dual panel color mode, pcd = 4 (lcd_dclk = lcdclk/6). single panel monochrome 4-bit interface mode, pcd = 2(lcd_dclk = lcdclk/4). dual panel monochrome 4-bit interface mode and single panel monochrome 8-bit interface mode, pcd = 6(lcd_dclk = lcdclk/8). dual panel monochrome 8-bit interface mode, pcd = 14(lcd_dclk = lcdclk/16). 0 5 clksel clock select. this bit controls the selection of the source for lcdclk. 0 = the clock source for the lcd block is cclk. 1 = the clock source for the lcd block is lcd_clkin (external clock input for the lcd). 0 10:6 acb ac bias pin frequency. the ac bias pin frequency is only applicable to stn displays. these require the pixel voltage polarity to periodically reverse to prevent damage caused by dc charge accumulation. program this field with the required value minus one to apply the number of line clocks between each toggle of the ac bias pin, lcd_enab_m. this field has no effect if the lcd is operating in tft mode, when the lcd_enab_m pin is used as a data enable signal. 0 11 ivs invert vertical synchronization. the ivs bit inverts the polarity of the lcd_fp signal. 0 = lcd_fp pin is active high and inactive low. 1 = lcd_fp pin is active low and inactive high. 0 12 ihs invert horizontal synchronization. the ihs bit inverts the polarity of the lcd_lp signal. 0 = lcd_lp pin is active high and inactive low. 1 = lcd_lp pin is active low and inactive high. 0 13 ipc invert panel clock. the ipc bit selects the edge of the panel clock on which pixel data is driven out onto the lcd data lines. 0 = data is driven on the lcd data lines on the rising edge of lcd_dclk. 1 = data is driven on the lcd data lines on the falling edge of lcd_dclk. 0 14 ioe invert output enable. this bit selects the active polarity of the output enable signal in tft mode. in this mode, the lcd_enab_m pin is used as an enable that indicates to the lcd panel when valid display data is available. in active display mode, data is driven onto the lcd data lines at the programmed edge of lcd_dclk when lcd_enab_m is in its active state. 0 = lcd_enab_m output pin is active high in tft mode. 1 = lcd_enab_m output pin is active low in tft mode. 0 15 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 301 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.4 line end control register the lcd_le register controls the enabling of line-end signal lcd_le. when enabled, a positive pulse, four lcdclk periods wide, is output on lcd_le after a programmable delay, led, from the last pixel of each displa y line. if the line-end signal is disabled it is held permanently low. 25:16 cpl clocks per line. this field specifies the num ber of actual l cd_dclk clocks to the lcd panel on each line. this is the number of ppl divided by either 1 (for tft), 4 or 8 (for monochrome passive), 2 2/3 (for color passive), minus one. th is must be correctly programmed in addition to the ppl bit in the lcd_timh register for the lcd display to work correctly. 0 26 bcd bypass pixel clock divider. setting this to 1 bypasses the pixel clock divider logic. this is mainly used for tft displays. 0 31:27 pcd_hi upper five bits of panel clock divisor. see description for pcd_lo, in bits [4:0] of this register. 0 table 224. clock and signal polarity register (pol, address 0x2008 8008) bit description bits symbol description reset value table 225. line end control register (le, address 0x2008 800c) bit description bits symbol description reset value 6:0 led line-end delay. controls line-end signal delay from the rising-edge of the last panel clock, lcd_dclk. program with the number of lcdclk clock periods minus 1. 0 15:7 - reserved. read value is undefined, only zero should be written. - 16 lee lcd line end enable. 0 = lcd_le disabled (held low). 1 = lcd_le signal active. 0 31:17 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 302 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.5 upper panel fram e base address register the lcd_upbase register is th e color lcd upper panel dma base address register, and is used to program the base address of the frame buffer for the upper panel. lcdupbase (and lcdlpbase for dual panels) must be initialized before enabling the lcd controller. the base address must be doubleword aligned. optionally, the value may be changed mid-frame to create double-buffered video displays. these registers are copied to the corresponding current registers at each lcd vertical synchronization. this event causes the lnbu bit and an optional interrupt to be generated. the interrupt can be used to reprogram the base address when generating double-buffered video. 11.7.6 lower panel fram e base address register the lcd_lpbase register is th e color lcd lower panel dma base address register, and is used to program the base address of the frame buffer for the lower panel. lcdlpbase must be initialized before enabling the lcd controller. the base address must be doubleword aligned. optionally, the value may be changed mid-frame to create double-buffered video displays. these registers are copied to the corresponding current registers at each lcd vertical synchronization. this event causes the lnbu bit and an optional interrupt to be generated. the interrupt can be used to reprogram the base address when generating double-buffered video. the contents of the lcd_lpb ase register are described in table 227 . table 226. upper panel frame base register (upbase, address 0x2008 8010) bit description bits symbol description reset value 2:0 - reserved. read value is undefined, only zero should be written. - 31:3 lcdupbase lcd upper panel base address. this is the start address of the upper panel frame data in memory and is doubleword aligned. 0 table 227. lower panel frame base register (lpbase, address 0x2008 8014) bit description bits symbol description reset value 2:0 - reserved. read value is undefined, only zero should be written. - 31:3 lcdlpbase lcd lower panel base address. this is th e start address of the lower panel frame data in memory and is doubleword aligned. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 303 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.7 lcd control register the lcd_ctrl register controls the lcd operating mode and the panel pixel parameters. the contents of the lcd_ctrl register are described in table 228 . table 228. lcd control register (ctrl, address 0x2008 8018) bit description bits symbol description reset value 0 lcden lcd enable control bit. 0 = lcd disabled. signals lcd_lp, lcd_dclk, lcd_fp, lcd_enab_m, and lcd_le are low. 1 = lcd enabled. signals lcd_lp, lcd_dclk, lcd_fp, lcd_enab_m, and lcd_le are high. see lcd power-up and power-down sequence for details on lcd power sequencing. 0 3:1 lcdbpp lcd bits per pixel. selects the number of bits per lcd pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (tft panel only). 110 = 16 bpp, 5:6:5 mode. 111 = 12 bpp, 4:4:4 mode. 0 4 lcdbw stn lcd monochrome/color selection. 0 = stn lcd is color. 1 = stn lcd is monochrome. this bit has no meaning in tft mode. 0 5 lcdtft lcd panel tft type selection. 0 = lcd is an stn display. use gray scaler. 1 = lcd is a tft display. do not use gray scaler. 0 6 lcdmono8 monochrome lcd interface width. contro ls whether a monochrome stn lcd uses a 4 or 8-bit parallel interface. it has no meaning in other modes and must be programmed to zero. 0 = monochrome lcd uses a 4-bit interface. 1 = monochrome lcd uses a 8-bit interface. 0 7 lcddual single or dual lcd panel selection. stn lcd interface is: 0 = single-panel. 1 = dual-panel. 0 8 bgr color format selection. 0 = rgb: normal output. 1 = bgr: red and blue swapped. 0 9 bebo big-endian byte order. cont rols byte ordering in memory: 0 = little-endian byte order. 1 = big-endian byte order. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 304 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 10 bepo big-endian pixel or dering. controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. the bepo bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats. see pixel serializer for more information on the data format. 0 11 lcdpwr lcd power enable. 0 = power not gated through to lcd panel and lcd_vd[23:0] signals disabled, (held low). 1 = power gated through to lcd panel and lcd_vd[23:0] signals enabled, (active). see lcd power-up and power-down sequence for details on lcd power sequencing. 0 13:12 lcdvcomp lcd vertical compare interrupt. generate vcomp interrupt at: 00 = start of vertical synchronization. 01 = start of back porch. 10 = start of active video. 11 = start of front porch. 0 15:14 - reserved. read value is undefined, only zero should be written. - 16 watermark lcd dma fifo watermark level. c ontrols when dma requests are generated: 0 = an lcd dma request is generated when either of the dma fifos have four or more empty locations. 1 = an lcd dma request is generated when either of the dma fifos have eight or more empty locations. 0 31:17 - reserved. read value is undefined, only zero should be written. - table 228. lcd control register (ctrl, address 0x2008 8018) bit description bits symbol description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 305 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.8 interrupt mask register the lcd_intmsk register controls whether va rious lcd interrupts occur.setting bits in this register enables the corresponding raw in terrupt lcd_intraw status bit values to be passed to the lcd_intstat register for processing as interrupts. the contents of the lcd_intmsk register are described in ta b l e 2 2 9 . table 229. interrupt mask register (intmsk, address 0x2008 801c) bit description bits symbol description reset value 0 - reserved. read value is undefined, only zero should be written. - 1 fufim fifo underflow interrupt enable. 0: the fifo underflow interrupt is disabled. 1: interrupt will be generated when the fifo underflows. 0 2 lnbuim lcd next base address update interrupt enable. 0: the base address update interrupt is disabled. 1: interrupt will be generated when the lcd base address registers have been updated from the next address registers. 0 3 vcompim vertical compare interrupt enable. 0: the vertical compare time interrupt is disabled. 1: interrupt will be generated when the vertical compare time (as defined by lcdvcomp field in the lcd_ctrl register) is reached. 0 4 berim ahb master error interrupt enable. 0: the ahb master error interrupt is disabled. 1: interrupt will be generated when an ahb master error occurs. 0 31:5 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 306 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.9 raw interrupt status register the lcd_intraw register contains status flags for various lcd controller events. these flags can generate an interrupts if enabled by mask bits in the lcd_intmsk register. 11.7.10 masked interrupt status register the lcd_intstat register is read-only, and contains a bit-by-bit logical and of the lcd_intraw register and the lcd_intmask register. a logical or of all interrupts is provided to the system interrupt controller. table 230. raw interrupt status register (intraw, address 0x2008 8020) bit description bits symbol description reset value 0 - reserved. read value is undefined, only zero should be written. - 1 fufris fifo underflow raw interrupt status. set when either the upper or lower dma fifos have been read accessed when empty causing an underflow condition to occur. generates an interrupt if the fufim bit in the lcd_intmsk register is set. 2 lnburis lcd next address base update raw interrupt status. mode dependent. set when the current base address registers have been successfully updated by the next address registers. signifies that a new next address can be loaded if double buffering is in use. generates an interrupt if the lnbuim bit in the lcd_intmsk register is set. 0 3 vcompris vertical compare raw interrupt status. set when one of the four vertical regions is reached, as selected by the lcdvcomp bits in the lcd_ctrl register. generates an interrupt if the vcompim bit in the lcd_intmsk register is set. 0 4 berraw ahb master bus error raw interrupt status. set when the ahb master interface receives a bus error response from a slave. generates an interrupt if the berim bit in the lcd_intmsk register is set. 0 31:5 - reserved. read value is undefined, only zero should be written. - table 231. masked interrupt status register (intstat, address 0x2008 8024) bit description bits symbol description reset value 0 - reserved. the value read from a reserved bit is not defined. - 1 fufmis fifo underflow masked interrupt status. set when the both the fufris bit in the lcd_intraw register and the fufim bit in the lcd_intmsk register are set. 0 2 lnbumis lcd next address base update masked interrupt status. set when the both the lnburis bit in the lcd_intraw register and the lnbuim bit in the lcd_intmsk register are set. 0 3 vcompmis vertical compare masked interrupt status . set when the both the vcompris bit in the lcd_intraw register and the vcompim bit in the lcd_intmsk register are set. 0 4 bermis ahb master bus error masked interrupt status. set when the both the berraw bit in the lcd_intraw register and the berim bit in the lcd_intmsk register are set. 0 31:5 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 307 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.11 interrupt clear register the lcd_intclr register is write-only. writing a logic 1 to the relevant bit clears the corresponding interrupt. 11.7.12 upper panel curre nt address register the lcd_upcurr register is read-only, and contains an approximate value of the upper panel data dma address when read. note: this register can change at any time an d therefore can only be used as a rough indication of display position. 11.7.13 lower panel cu rrent address register the lcd_lpcurr register is read-only, and co ntains an approximate value of the lower panel data dma address when read. note: this register can change at any time an d therefore can only be used as a rough indication of display position. table 232. interrupt clear register (intclr, address 0x2008 8028) bit description bits symbol description 0 - reserved. read value is undefined, only zero should be written. 1 fufic fifo underflow interrupt clear. writing a 1 to this bit clears the fifo underflow interrupt. 2 lnbuic lcd next address base update interrupt clear. writing a 1 to this bit clears the lcd next address base update interrupt. 3 vcompic vertical compare interrupt clear. writing a 1 to this bit clears the vertical compare interrupt. 4 beric ahb master error interrupt clear. writing a 1 to this bit clears the ahb master error interrupt. 31:5 - reserved. read value is undefined, only zero should be written. table 233. upper panel current address register (upcurr, address 0x2008 802c) bit description bits symbol description reset value 31:0 lcdupcurr lcd upper panel current address. co ntains the current lcd upper panel data dma address. 0 table 234. lower panel current address register (lpcurr, address 0x2008 8030) bit description bits symbol description reset value 31:0 lcdlpcurr lcd lower panel current address. contains the current lcd lower panel data dma address. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 308 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.14 color palette registers the lcd_pal register contain 256 palette entries organized as 128 locations of two entries per word. each word location contains two palette entri es. this means that 128 word locations are used for the palette. when configured for littl e-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. when configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry. note: only tft displays use all of the palette entry bits. 11.7.15 cursor image registers the crsr_img register area c ontains 256-word wide values which are used to define the image or images overlaid on the displa y by the hardware cursor mechanism. the image must always be stored in lbbp mode (lit tle-endian byte, big-endian pixel) mode, as described in section 11.6.5.6 . two bits are used to encode color and transparency for each pixel in the cursor. depending on the state of bit 0 in the cr sr_cfg register (see cursor configuration register description), the cursor image ram co ntains either four 32x32 cursor images, or a single 64x64 cursor image. the two colors defined for the cursor are mapped onto values from the crsr_pal0 and crsr_pal0 registers (see cursor palette register descriptions). table 235. color palette registers (pal[0:127], address 0x2008 8200 (pal0) to 0x2008 83fc (pal127)) bit description bits symbol description reset value 4:0 r04_0 red palette data. for stn displays, only the four msbs, bits [4:1], are used. for monochrome displays only the red palette data is used. all of the palette registers have the same bit fields. 0 9:5 g04_0 green palette data. 0 14:10 b04_0 blue palette data. 0 15 i0 intensity / unused bit. can be used as the lsb of the r, g, and b inputs to a 6:6:6 tft display, doubling the number of colors to 64k, where each color has two different intensities. 0 20:16 r14_0 red palette data. for stn displays, only the four msbs, bits [4:1], are used. for monochrome displays only the red palette data is used. all of the palette registers have the same bit fields. 0 25:21 g14_0 green palette data. 0 30:26 b14_0 blue palette data. 0 31 i1 intensity / unused bit. can be used as the lsb of the r, g, and b inputs to a 6:6:6 tft display, doubling the number of colors to 64k, where each color has two different intensities. 0 table 236. cursor image registers (crsr_img[0:255] , address 0x2008 8800 (crsr_img0) to 0x2008 8bfc (crsr_img255)) bit description bits symbol description reset value 31:0 crsr_img cursor image data. the 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 309 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.16 cursor control register the crsr_ctrl register provides access to frequently used cursor functions, such as the display on/off control for the cursor, and the cursor number. if a 32x32 cursor is selected, one of four 32x32 cursors can be enabled. the images each occupy one quarter of the image memory, wi th cursor0 from location 0, followed by cursor1 from address 0x100, cursor2 from 0x200 and cursor3 from 0x300. if a 64x64 cursor is selected only one cursor fits in the image buffer, and no selection is possible. similar frame synchronization rules apply to the cursor number as apply to the cursor coordinates. if crsrframesync is 1, the displayed cursor image is only changed during the vertical frame blanking period. if crsrframesyn c is 0, the cursor image index is changed immediately, even if the cursor is currently being scanned. 11.7.17 cursor configuration register the crsr_cfg register provi des overall configuration information for the hardware cursor. table 237. cursor control register (crsr_ctrl, address 0x2008 8c00) bit description bits symbol description reset value 0 crsron cursor enable. 0 = cursor is not displayed. 1 = cursor is displayed. 0 3:1 - reserved. read value is undefined, only zero should be written. 0 5:4 crsrnum1_0 cursor image number. if the selected cursor size is 6x64, this field has no effect. if the selected cursor size is 32x32: 00 = cursor0. 01 = cursor1. 10 = cursor2. 11 = cursor3. 0 31:6 - reserved. read value is undefined, only zero should be written. 0 table 238. cursor configuration register (crsr_cfg, address 0x2008 8c04) bit description bits symbol description reset value 0 crsrsize cursor size selection. 0 = 32x32 pixel cursor. allows for 4 defined cursors. 1 = 64x64 pixel cursor. 0 1 framesync cursor frame synchronization type. 0 = cursor coordinates are asynchronous. 1 = cursor coordinates are synchronized to the frame synchronization pulse. 0 31:2 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 310 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.18 cursor palette register 0 the cursor palette registers provide color palette information for the visible colors of the cursor. color0 maps through crsr_pal0. the register provides 24 -bit rgb values that are displayed according to the abilities of the lcd panel in the same way as the frame-buffers palette output is displayed. in monochrome stn mode, only the upper 4 bits of the red field are used. in stn color mode, the upper 4 bits of the red, blue, and green fields are used. in 24 bits per pixel mode, all 24 bits of the palette registers are significant. 11.7.19 cursor palette register 1 the cursor palette registers provide color palette information for the visible colors of the cursor. color1 maps through crsr_pal1. the register provides 24 -bit rgb values that are displayed according to the abilities of the lcd panel in the same way as the frame-buffers palette output is displayed. in monochrome stn mode, only the upper 4 bits of the red field are used. in stn color mode, the upper 4 bits of the red, blue, and green fields are used. in 24 bits per pixel mode, all 24 bits of the palette registers are significant. table 239. cursor palette register 0 (crsr_pal0, address 0x2008 8c08) bit description bits symbol description reset value 7:0 red red color component 0 15:8 green green color component 0 23:16 blue blue color component. 0 31:24 - reserved. read value is undefined, only zero should be written. - table 240. cursor palette register 1 (crsr_pal1, address 0x2008 8c0c) bit description bits symbol description reset value 7:0 red red color component 0 15:8 green green color component 0 23:16 blue blue color component. 0 31:24 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 311 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.20 cursor xy position register the crsr_xy register defines the distance of the top-left edge of the cursor from the top-left side of the cursor overlay. refer to th e section on cursor clipping for more details. if the framesync bit in the crsr_cfg register is 0, th e cursor position changes immediately, even if the cursor is currently being scanned. if framesync is 1, the cursor position is only changed during the next vertical frame blanking period. 11.7.21 cursor clip position register the crsr_clip register defines the distance fr om the top-left edge of the cursor image, to the first displayed pixel in the cursor image. different synchronization rules apply to the cursor clip registers than apply to the cursor coordinates. if the framesync bit in the crsr_cfg register is 0, the cursor clip point is changed immediately, even if the cursor is currently being scanned. if the framesync bit in the crsr_cfg register is 1, the displayed cursor image is only changed during the vertical frame blanking period, providing that the cursor position has been updated since the clip register was programmed. when programming, the clip register must be written before the position register (clcdcrsr xy) to ensure that in a given frame, the clip and position information is coherent. the contents of the crsr_clip register are described in table 242 . table 241. cursor xy position register (crsr_xy, address 0x2008 8c10) bit description bits symbol description reset value 9:0 crsrx x ordinate of the cursor origin measured in pixels. when 0, the left edge of the cursor is at the left of the display. 0 15:10 - reserved. read value is undefined, only zero should be written. - 25:16 crsry y ordinate of the cursor origin measured in pixels. when 0, the top edge of the cursor is at the top of the display. 0 31:26 - reserved. read value is undefined, only zero should be written. - table 242. cursor clip position register (crsr_clip, address 0x2008 8c14) bit description bits symbol description reset value 5:0 crsrclipx cursor clip position for x direction. distance from the left edge of the cursor image to the first displayed pixel in the cursor. when 0, the first pixel of the cursor line is displayed. 0 7:6 - reserved. read value is undefined, only zero should be written. - 13:8 crsrclipy cursor clip position for y direction. distance from the top of the cursor image to the first displayed pixel in the cursor. when 0, the first displayed pixel is from the top line of the cursor image. 0 31:14 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 312 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.22 cursor interrupt mask register the crsr_intmsk register is used to enable or disable the cursor from interrupting the processor. 11.7.23 cursor interrupt clear register the crsr_intclr register is used by software to clear the cursor interrupt status and the cursor interrupt signal to the processor. 11.7.24 cursor raw interr upt status register the crsr_intraw register is set to indicate a cursor interrupt. when enabled via the crsrim bit in the crsr_intmsk register, prov ides the interrupt to the system interrupt controller. table 243. cursor interrupt mask register (crsr_intmsk, rw - 0x2008 8c20) bits symbol description reset value 0 crsrim cursor interrupt mask. when clear, the curs or never interrupts the processor. when set, the cursor interrupts the processor immediately after reading of the last word of cursor image. 0 31:1 - reserved. read value is undefined, only zero should be written. - table 244. cursor interrupt clear register (crsr_intclr, address 0x2008 8c24) bit description bits symbol description 0 crsric cursor interrupt clear. writing a 0 to this bit has no effect. writing a 1 to this bit causes the cursor interrupt status to be cleared. 31:1 - reserved. read value is undefined, only zero should be written. table 245. cursor raw interrupt status register (crsr_intraw, address 0x2008 8c28) bit description bits symbol description reset value 0 crsrris cursor raw interrupt status. the cursor inte rrupt status is set immediately after the last data is read from the cursor image for the curre nt frame. this bit is cleared by writing to the crsric bit in the crsr_intclr register. 0 31:1 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 313 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.7.25 cursor masked interrupt status register the crsr_intstat register is set to indica te a cursor interrupt providing that the interrupt is not masked in the crsr_intmsk register. table 246. cursor masked interrupt status register (crsr_intstat, address 0x2008 8c2c) bit description bits symbol description reset value 0 crsrmis cursor masked interrupt status. the cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the crsr_intmsk register is set. the bit remains clear if the crsr_intmsk register is clear. this bit is cleared by writing to the crsr_intclr register. 0 31:1 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 314 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.8 lcd timing diagrams (1) the active data lines will vary with the type of stn panel (4-bit, 8-bit, colo r, mono) and with single or dual frames. (2) the lcd panel clock is selected and scaled by the lcd controller and used to produce lcdclk. (3) the duration of the lcd_lp signal is controlled by the hsw field in the lcd_timh register. (4) the polarity of the lcd_lp signal is deter mined by the ihs bit in the lcd_pol register. fig 37. horizontal timing for stn displays pixel clock (internal) lcd_timh (hsw) lcdlp (line synch pulse) suppressed during lcdlp lcd_timh (hbp) 16 ? lcd_timh(ppl) ? 1 lcd_timh (hfp) lcddclk (panel clock) horizontal back porch (defined in pixel clocks) horizontal front porch (defined in pixel clocks) one horizontal line of lcd data lcdvd[15:0] (panel data) one horizontal line
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 315 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller (1) signal polarities may va ry for some displays. fig 38. vertical timing for stn displays lcd_timv (vsw) lcddclk (panel clock) lcd_timv (vbp) lcd_timv(lpp) lcd_timv (vfp) lcdfp (vertical synch pulse) back porch (defined in line clocks) front porch (defined in line clocks) pixel data and horizontal controls for one frame one frame all horizontal lines for one frame see horizontal timing for stn displays panel data clock active (1) the active data lines will vary with the type of tft panel. (2) the lcd panel clock is selected and scaled by the lcd controller and used to produce lcdclk. (3) the duration of the lcd_lp is controlled by the hsw field in the lcd_timh register. (4) the polarity of the lcd_lp signal is determined by the ihs bit in the lcd_pol register. fig 39. horizontal timing for tft displays pixel clock (internal) lcd_timh (hsw) lcdlp (lhorizontal synch pulse) lcd_timh (hbp) lcd_timh(ppl) lcd_timh (hfp) lcddclk (panel clock) lcdenab horizontal back porch (defined in pixel clocks) horizontal front porch (defined in pixel clocks) one horizontal line of lcd data lcdvd[23:0] (panel data) one horizontal line
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 316 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller (1) polarities may vary for some displays. fig 40. vertical timing for tft displays lcd_timv (vsw) lcdena (data enable) lcd_timv (vbp) lcd_timv(lpp) lcd_timv (vfp) lcdfp (vertical synch pulse) back porch (defined in line clocks) front porch (defined in line clocks) pixel data and horizontal control signals for one frame one frame all horizontal lines for one frame see horizontal timing for tft displays data enable lcddclk (panel clock) panel data clock active
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 317 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller 11.9 lcd panel signal usage table 247. lcd panel connections for stn single panel mode external pin 4-bit mono stn single panel 8-bit mono stn single panel color stn single panel pin used lcd function pin used lcd function pin used lcd function lcd_vd[8] - lcd_vd[23] -- -- -- lcd_vd[7] - - p4[29] ud[7] p4[29] ud[7] lcd_vd[6] - - p4[28] ud[6] p4[28] ud[6] lcd_vd[5] - - p2[13] ud[5] p2[13] ud[5] lcd_vd[4] - - p2[12] ud[4] p2[12] ud[4] lcd_vd[3] p2[9] ud[3] p2[9] ud[3] p2[9] ud[3] lcd_vd[2] p2[8] ud[2] p2[8] ud[2] p2[8] ud[2] lcd_vd[1] p2[7] ud[1] p2[7] ud[1] p2[7] ud[1] lcd_vd[0] p2[6] ud[0] p2[6] ud[0] p2[6] ud[0] lcd_lp p2[5] lcd_lp p2[5] lcd_lp p2[5] lcd_lp lcd_enab_m p2[4] lcd_enab_m p2[ 4] lcd_enab_m p2[4] lcd_enab_m lcd_fp p2[3] lcd_fp p2[3] lcd_fp p2[3] lcd_fp lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk lcd_le p2[1] lcd_le p2[1] lcd_le p2[1] lcd_le lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin p2[0] lcd_pwr
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 318 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller table 248. lcd panel connections for stn dual panel mode external pin 4-bit mono stn dual panel 8-bit mono stn dual panel color stn dual panel pin used lcd function pin used lcd function pin used lcd function lcd_vd[16] - lcd_vd[23] -- -- -- lcd_vd[15] - - p1[29] ld[7] p1[29] ld[7] lcd_vd[14] - - p1[28] ld[6] p1[28] ld[6] lcd_vd[13] - - p1[27] ld[5] p1[27] ld[5] lcd_vd[12] - p1[26] ld[4] p1[26] ld[4] lcd_vd[11] p4[29] ld[3] p1[25] ld[3] p1[25] ld[3] lcd_vd[10] p4[28] ld[2] p1[24] ld[2] p1[24] ld[2] lcd_vd[9] p2[13] ld[1] p1[23] ld[1] p1[23] ld[1] lcd_vd[8] p2[12] ld[0] p1[22] ld[0] p1[22] ld[0] lcd_vd[7] - - p1[21] ud[7] p1[21] ud[7] lcd_vd[6] - - p1[20] ud[6] p1[20] ud[6] lcd_vd[5] - - p2[13] ud[5] p2[13] ud[5] lcd_vd[4] - - p2[12] ud[4] p2[12] ud[4] lcd_vd[3] p2[9] ud[3] p2[9] ud[3] p2[9] ud[3] lcd_vd[2] p2[8] ud[2] p2[8] ud[2] p2[8] ud[2] lcd_vd[1] p2[7] ud[1] p2[7] ud[1] p2[7] ud[1] lcd_vd[0] p2[6] ud[0] p2[6] ud[0] p2[6] ud[0] lcd_lp p2[5] lcd_lp p2[5] lcd_lp p2[5] lcd_lp lcd_enab_m p2[4] lcd_enab_m p2[ 4] lcd_enab_m p2[4] lcd_enab_m lcd_fp p2[3] lcd_fp p2[3] lcd_fp p2[3] lcd_fp lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk lcd_le p2[1] lcd_le p2[1] lcd_le p2[1] lcd_le lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr p2[0] lcd-pwr lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 319 of 942 nxp semiconductors UM10562 chapter 11: lpc408x/407x lcd controller table 249. lcd panel connections for tft panels external pin tft 12 bit (4:4:4 mode) tft 16 bit (5:6:5 mode) tft 16 bit (1:5:5:5 mode) tft 24 bit pin used lcd function pin used lcd function pin used lcd function pin used lcd function lcd_vd[23] p1[29] blue3 p1[29] blue4 p1[29] blue4 p1[29] blue7 lcd_vd[22] p1[28] blue2 p1[28] blue3 p1[28] blue3 p1[28] blue6 lcd_vd[21] p1[27] blue1 p1[27] blue2 p1[27] blue2 p1[27] blue5 lcd_vd[20] p1[26] blue0 p1[26] blue1 p1[26] blue1 p1[26] blue4 lcd_vd[19] - - p2[13] blue0 p2[13] blue0 p2[13] blue3 lcd_vd[18] - - - - p2[12] intensity p2[12] blue2 lcd_vd[17]-- -- -- p0[9]blue1 lcd_vd[16]-- -- -- p0[8]blue0 lcd_vd[15] p1[25] green3 p1[25] gr een5 p1[25] green4 p1[25] green7 lcd_vd[14] p1[24] green2 p1[24] gr een4 p1[24] green3 p1[24] green6 lcd_vd[13] p1[23] green1 p1[23] gr een3 p1[23] green2 p1[23] green5 lcd_vd[12] p1[22] green0 p1[22] gr een2 p1[22] green1 p1[22] green4 lcd_vd[11] - - p1[21] green1 p 1[21] green0 p1[21] green3 lcd_vd[10] - - p1[20] green0 p1[20] intensity p1[20] green2 lcd_vd[9] - - - - - - p0[7] green1 lcd_vd[8] - - - - - - p0[6] green0 lcd_vd[7] p2[9] red3 p2[9] red4 p2[9] red4 p2[9] red7 lcd_vd[6] p2[8] red2 p2[8] red3 p2[8] red3 p2[8] red6 lcd_vd[5] p2[7] red1 p2[7] red2 p2[7] red2 p2[7] red5 lcd_vd[4] p2[6] red0 p2[6] red1 p2[6] red1 p2[6] red4 lcd_vd[3] - - p2[12] red0 p4[29] red0 p4[29] red3 lcd_vd[2] - - - - p4[28] intensity p4[28] red2 lcd_vd[1] - - - - - - p0[5] red1 lcd_vd[0] - - - - - - p0[4] red0 lcd_lp p2[5] lcd_lp p2[5] lcd_lp p2[5] lcd_lp p2[5] lcd_lp lcd_ enab_m p2[4] lcd_ enab_m p2[4] lcd_ enab_m p2[4] lcd_ enab_m p2[4] lcd_ enab_m lcd_fp p2[3] lcd_fp p2[3] lcd_fp p2[3] lcd_fp p2[3] lcd_fp lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk p2[2] lcd_dclk lcd_le p2[1] lcd_le p2[1] lcd_le p2[1] lcd_le p2[1] lcd_le lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr p2[0] lcd_pwr lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin p2[11] lcd_clkin
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 320 of 942 12.1 how to read this chapter this chapter describes the usb device cont roller which is present on lpc408x/407x family devices. on some family devices, the usb controller can also be configured for host or otg operation (see section 1.4 for details). 12.2 basic configuration the usb controller is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcusb. remark: on reset, the usb block is disabled (pcusb = 0). 2. clock: the usb block can be used with either the main pll (pll0), or with the alternate pll (pll1) to obtain the usb clock. see section 3.10 . 3. pins: select the required usb pins and their modes in the relevant iocon registers ( section 7.4.1 ). 4. wake-up: activity on the usb bus port can wake up the microcontroller from power-down mode, see section 3.12.8 . 5. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. the usb global interrupt status is visible in the usbintstat register ( ta b l e 3 7 ). 7. initialization: see section 12.13 . 12.3 introduction the universal serial bus (usb) is a four-wir e bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a to ken-based protocol. the bus supports hot plugging and dynamic configuration of the devi ces. all transa ctions are initiated by the host controller. the host schedules transactions in 1 ms fram es. each frame contains a start-of-frame (sof) marker and transactions that transfer da ta to or from device endpoints. each device can have a maximum of 16 logical or 32 physical endpoints. there are four types of transfers defined for the endpoints. control tr ansfers are used to configure the device. interrupt transfers are used for periodic data transfer. bulk transfers are used when the rate of transfer is not crit ical. isochronous transfers have guaranteed delivery time but no error correction. for more information on the universal serial bus, see the usb implementers forum website. the usb device controller enables full-speed (12 mb/s) data exchange with a usb host controller. UM10562 chapter 12: lpc408x/407x usb device controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 321 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.4 features ? fully compliant with the usb 2.0 specification (full speed). ? supports 32 physical (16 logical) endpoints. ? supports control, bulk, interr upt and isochronous endpoints. ? scalable realization of endpoints at run time. ? endpoint maximum packet size selection (up to usb maximum specification) by software at run time. ? supports softconnect and goodlink features. ? supports dma transfers on all non-control endpoints. ? allows dynamic switching betwee n cpu controlled and dma modes. ? double buffer implementation for bulk and isochronous endpoints. 12.5 fixed endpoint configuration table 251 shows the supported endpoint config urations. endpoints are realized and configured at run time using the endpoint realization registers, documented in section 12.10.4 ? endpoint realization registers ? . table 250. usb related acronyms, abbreviations, and definitions used in this chapter acronym/abbreviation description ahb advanced high-performance bus atle auto transfer length extraction atx analog transceiver dd dma descriptor ddp dma description pointer dma direct memory access eop end-of-packet ep endpoint ep_ram endpoint ram fs full speed led light emitting diode ls low speed mps maximum packet size nak negative acknowledge pll phase locked loop ram random access memory sof start-of-frame sie serial interface engine sram synchronous ram udca usb device communication area usb universal serial bus
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 322 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller table 251. fixed endpoint configuration logical endpoint physical endpoint endpoint type direction packet size (bytes) double buffer 0 0 control out 8, 16, 32, 64 no 0 1 control in 8, 16, 32, 64 no 1 2 interrupt out 1 to 64 no 1 3 interrupt in 1 to 64 no 2 4 bulk out 8, 16, 32, 64 yes 2 5 bulk in 8, 16, 32, 64 yes 3 6 isochronous out 1 to 1023 yes 3 7 isochronous in 1 to 1023 yes 4 8 interrupt out 1 to 64 no 4 9 interrupt in 1 to 64 no 5 10 bulk out 8, 16, 32, 64 yes 5 11 bulk in 8, 16, 32, 64 yes 6 12 isochronous out 1 to 1023 yes 6 13 isochronous in 1 to 1023 yes 7 14 interrupt out 1 to 64 no 7 15 interrupt in 1 to 64 no 8 16 bulk out 8, 16, 32, 64 yes 8 17 bulk in 8, 16, 32, 64 yes 9 18 isochronous out 1 to 1023 yes 9 19 isochronous in 1 to 1023 yes 10 20 interrupt out 1 to 64 no 10 21 interrupt in 1 to 64 no 11 22 bulk out 8, 16, 32, 64 yes 11 23 bulk in 8, 16, 32, 64 yes 12 24 isochronous out 1 to 1023 yes 12 25 isochronous in 1 to 1023 yes 13 26 interrupt out 1 to 64 no 13 27 interrupt in 1 to 64 no 14 28 bulk out 8, 16, 32, 64 yes 14 29 bulk in 8, 16, 32, 64 yes 15 30 bulk out 8, 16, 32, 64 yes 15 31 bulk in 8, 16, 32, 64 yes
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 323 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.6 functional description the architecture of the usb devi ce controller is shown below in figure 41 . 12.6.1 analog transceiver the usb device controller has a built-in analog transceiver (atx). the usb atx sends/receives the bidirectional d+ and d- signals of the usb bus. 12.6.2 serial interface engine (sie) the sie implements the full usb protocol layer. it is completely hardwired for speed and needs no firmware intervention. it handles tran sfer of data between the endpoint buffers in ep_ram and the usb bus. the functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, crc checking/generation, pid verification/generation, address recogn ition, and handshake evaluation/generation. 12.6.3 endpoint ram (ep_ram) each endpoint buffer is implemented as an sram based fifo. the sram dedicated for this purpose is called the ep_ram. each rea lized endpoint has a reserved space in the ep_ram. the total ep_ram space required depends on the number of realized endpoints, the maximum packet size of the endpoint, and whether the endpoint supports double buffering. fig 41. usb device controller block diagram register interface (ahb slave) dma interface (ahb master) ep_ram (4k) ep_ram access control register interface serial interface engine dma engine usb device block usb atx bus master interface ahb bus v bus usb_connect1 usb_connect2 usb_d+1, usb_d+2 usb_d-1, usb_d-2 usb_up_led1, usb_up_led2
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 324 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.6.4 ep_ram access control the ep_ram access control logic handles trans fer of data from/to the ep_ram and the three sources that can access it: the cpu (via the register interfac e), the sie, and the dma engine. 12.6.5 dma engine and bus master interface when enabled for an endpoint, the dma engine transfers data between ram on the ahb bus and the endpoint?s buffer in ep_ram. a single dma channel is shared between all endpoints. when transferring data, the dma engine functions as a master on the ahb bus through the bus master interface. 12.6.6 register interface the register interface allows the cpu to control the operation of the usb device controller. it also provides a way to write tr ansmit data to the controller and read receive data from the controller. 12.6.7 softconnect the connection to the usb is accomplished by bringing d+ (for a fu ll-speed device) high through a 1.5 kohm pull-up resistor. the softconnect feature can be used to allow software to finish its initializ ation sequence before deciding to establish connection to the usb. re-initialization of the usb bus connecti on can also be performed without having to unplug the cable. to use the softconnect feature, the connect signal should control an external switch that connects the 1.5 kohm resistor between d+ and +3.3v. software can then control the connect signal by writing to the con bit using the sie set device status command. 12.6.8 goodlink good usb connection indication is provided through goodlink technology. when the device is successfully enume rated and configured, the led indicator will be permanently on. during suspend, the led will be off. this feature provides a user-friendly indicator on the status of the usb device. it is a useful field diagnostics tool to isolate faulty equipment. to use the goodlink feature the up_led signal should control an led. the up_led signal is controlled using the sie configure device command.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 325 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.7 operational overview transactions on the usb bus transfer data between device endpoints and the host. the direction of a transaction is defined with respect to the host. out transactions transfer data from the host to the device. in transactio ns transfer data from the device to the host. all transactions ar e initiated by the host controller. for an out transaction, the usb atx receives the bidirectional d+ and d- signals of the usb bus. the serial interface engine (sie) receives the serial data from the atx and converts it into a parallel data stream. the parallel data is written to the corresponding endpoint buffer in the ep_ram. for in transactions, the sie reads the parallel data from the endpoint buffer in ep_ram, converts it into serial data, and transmits it onto the usb bus using the usb atx. once data has been received or sent, the endpoint buffer can be read or written. how this is accomplished depends on the endpoint?s type and operating mode. the two operating modes for each endpoint are slave (c pu-controlled) mode, and dma mode. in slave mode, the cpu transfers data between ram and the endpoint buffer using the register interface. see section 12.14 ? slave mode operation ? for a detailed description of this mode. in dma mode, the dma transfers data between ram and the endpoint buffer. see section 12.15 ? dma operation ? for a detailed description of this mode. 12.8 pin description table 252. usb external interface name direction description v bus iv bus status input. when this input function is not enabled via the corresponding iocon register, it is driven high internally. usb_connect1, usb_connect2 o softconnect control signal. usb_up_led1, usb_up_led2 o goodlink led control signal. usb_d+1, usb_d+2 i/o positive differential data. usb_d-1, usb_d-2 i/o negative differential data.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 326 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.9 clocking an d power management this section describes the clocking and powe r management features of the usb device controller. 12.9.1 power requirements the usb protocol insists on power management by the device. this becomes very critical if the device draws power from the bus (bus -powered device). the following constraints should be met by a bus-powered device: 1. a device in the non-configured state should draw a maximum of 100 ma from the bus. 2. a configured device can draw only up to wh at is specified in the max power field of the configuration descriptor. the maximum value is 500 ma. 3. a suspended device can draw a maximum of 500 a. 12.9.2 clocks the usb device controller clocks are shown in table 253 12.9.3 power management support to help conserve power, the usb device controller automatically disables the ahb master clock and usbclk when not in use. when the usb device controller goes into the suspend state (bus is idle for 3 ms), the usbclk input to the device controller is autom atically disabled, helping to conserve power. however, if software wishes to access the device controlle r registers, usbclk must be active. to allow access to the device controller registers while in the suspend state, the usbclkctrl and usbclkst registers are provided. when software wishes to access the device controller registers, it should first ensure usbclk is enabled by setting dev_clk_en in the usbclkctrl register, and then poll the corresponding dev_ clk_on bit in usbclkst until set. once set, usbc lk will remain enabled until dev_clk_en is cleared by software. when a dma transfer occurs, the device controller automatically turns on the ahb master clock. once asserted, it remains active for a minimum of 2 ms (2 frames), to help ensure that dma throughput is not affected by turning off the ahb master clock. 2 ms after the last dma access, the ahb master clock is auto matically disabled to help conserve power. if desired, software also has th e capability of forcing this clo ck to remain enabled using the usbclkctrl register. table 253. usb device controller clock sources clock source description ahb master clock clock for the ah b master bus interface and dma ahb slave clock clock for the ahb slave interface usbclk 48 mhz clock from the dedicated alt pll (pll1) or the main pll (pll0), used to recover the 12 mhz clock from the usb bus
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 327 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller note that the ahb slave clock is always enab led as long as the pcusb bit of pconp is set. when the device controller is not in use, all of the device controller clocks may be disabled by clearing pcusb. the usb_need_clk signal is us ed to facilitate going into and waking up from chip power-down mode. usb_need_clk is asserted if any of the bits of the usbclkst register are asserted. after entering the suspend state with dev_clk_en and ahb_cl k_en cleared, the dev_clk_on and ahb_clk_on will be cleared when the corr esponding clock turns off. when both bits are zero, usb_need_clk will be low, indicating that the chip can be put into power-down mode by writing to the pc on register. the status of usb_need_clk can be read from the usbintst register. any bus activity in the su spend state will cause the u sb_need_clk signal to be asserted. when the chip is in power-down mode and the usb interrupt is enabled, the assertion of usb_need_clk causes the ch ip to wake up from power-down mode. 12.9.4 remote wake-up the usb device controller supports software initiated remote wake-up. remote wake-up involves resume signaling on the usb bus in itiated from the device. this is done by clearing the sus bit in the sie set device stat us register. before writing into the register, all the clocks to the device controller have to be enabled using the usbclkctrl register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 328 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10 register description table 254 shows the usb device controller register s directly accessible by the cpu. the serial interface engine (sie) has other register s that are indirectly accessible via the sie command registers. see section 12.12 ? serial interface engine command description ? for more info. the usb interrupt status is captured in th e usbintstat register in the syscon block. reading wo register will return an invalid value. table 254. register overview: usb device controller (base address 0x2008 c000) name access address offset description reset value [1] table port select register portsel r/w 0x110 usb port select. this register is also used for otg configuration. in device-only operations only bits 0 and 1 of this register are used to control the routing of usb pins to port 1 or port 2. 0 255 device interrupt registers devintst ro 0x200 usb device interrupt status 0x10 256 devinten r/w 0x204 usb device interrupt enable 0 257 devintclr wo 0x208 usb device interrupt clear - 258 devintset wo 0x20c usb device interrupt set - 259 devintpri wo 0x22c usb device interrupt priority 0 260 endpoint interrupt registers epintst ro 0x230 usb endpoint interrupt status 0 262 epinten r/w 0x234 usb endpoint interrupt enable 0 263 epintclr wo 0x238 usb endpoint interrupt clear - 264 epintset wo 0x23c usb endpoint interrupt set - 265 epintpri wo 0x240 usb endpoint priority 0 266 endpoint realization registers reep r/w 0x244 usb realize endpoint 0x3 267 epin wo 0x248 usb endpoint index 0 268 maxpsize r/w 0x24c usb maxpacketsize 0x8 269 usb transfer registers rxdata ro 0x218 usb receive data 0 270 rxplen ro 0220 usb receive packet length 0 271 txdata wo 0x21c usb transmit data - 272 txplen wo 0x224 usb tran smit packet length 0 273 ctrl r/w 0x228 usb control 0 274 sie command registers cmdcode wo 0x210 usb command code 0 275 cmddata ro 0x214 usb command data 0 276 dma registers dmarst ro 0x250 usb dma request status 0 277
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 329 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. dmarclr wo 0x254 usb dma request clear - 278 dmarset wo 0x258 usb dma request set - 279 udcah r/w 0x280 usb udca head 0 280 epdmast ro 0x284 usb endpoint dma status 0 281 epdmaen wo 0x288 usb endpoint dma enable - 282 epdmadis wo 0x28c usb endpoint dma disable - 283 dmaintst ro 0x290 usb dma interrupt status 0 284 dmainten r/w 0x294 usb dma interrupt enable 0 285 eotintst ro 0x2a0 usb end of transfer interrupt status 0 286 eotintclr wo 0x2a4 usb end of transfer interrupt clear - 287 eotintset wo 0x2a8 usb end of transfer interrupt set - 288 nddrintst ro 0x2ac usb new dd request interrupt status 0 289 nddrintclr wo 0x2b0 usb new dd request interrupt clear - 290 nddrintset wo 0x2b4 usb new dd request interrupt set - 291 syserrintst ro 0x2b8 usb system error interrupt status 0 292 syserrintclr wo 0x2bc usb system error interrupt clear - 293 syserrintset wo 0x2c0 usb system error interrupt set - 294 clock control registers clkctrl r/w 0xff4 usb clock control 0 295 clkst ro 0xff8 usb clock status 0 296 table 254. register overview: usb device controller (base address 0x2008 c000) name access address offset description reset value [1] table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 330 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.1 port select register 12.10.1.1 usb port select register this register selects the usb port pins that the usb device signals are routed to. usbportsel is a read/write register. 12.10.2 device inte rrupt registers 12.10.2.1 usb device interrupt status register the usbdevintst register holds the status of each interrupt. a 0 indicates no interrupt and 1 indicates the presence of the interrup t. usbdevintst is a read-only register. table 255. usb port select register (portsel - address 0x2008 c110) bit description bit symbol value description reset value 1:0 portsel selects which usb port the device controller signals are mapped to. other values are reserved. 0 0x0 the usb device controller signals are mapped to the u1 port: usb_connect1, usb_up_led 1, usb_d+1, usb_d-1. 0x3 the usb device controller signals are mapped to the u2 port: usb_connect2, usb_up_led 2, usb_d+2, usb_d-2. 31:2 - reserved. read value is undefined, only zero should be written. na table 256. usb device interrupt status register (devintst - address 0x2008 c200) bit description bit symbol description reset value 0 frame the frame interrupt occurs every 1 ms. this is used in isochronous packet transfers. 0 1 ep_fast fast endpoint interrupt. if an endpoint interrupt priority regi ster (usbepintpri) bit is set, the corresponding endpoint interrupt will be routed to this bit. 0 2 ep_slow slow endpoints interrupt. if an endpoint interrupt priority register (usbepintpri) bit is not set, the corresponding endpoint interrupt will be routed to this bit. 0 3 dev_stat set when usb bus reset, usb suspend change or connect change event occurs. refer to section 12.12.6 ? set device status (command: 0xfe, data: write 1 byte) ? on page 360 . 0 4 ccempty the command code register (usbcmdcode ) is empty (new command can be written). 1 5 cdfull command data register (usbcmddata) is full (data can be read now). 0 6 rxendpkt the current packet in the endpoint buffer is transferred to the cpu. 0 7 txendpkt the number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the txpacket length register (usbtxplen). 0 8 ep_rlzed endpoints realized. set when realize endpoint register (usbreep) or maxpacketsize register (usbmaxpsize) is updated and the corresponding operation is completed. 0 9 err_int error interrupt. any bus error in terrupt from the usb device. refer to section 12.12.9 ? read error status (command: 0xfb, data: read 1 byte) ? on page 362 0 31:10 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 331 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.2.2 usb device interrupt enable register writing a one to a bit in this register enables the corresponding bit in usbdevintst to generate an interrupt on one of the interrup t lines when set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_ hp interrupt line by changing the value of usbdevintpri. usbdevinten is a read/write register. table 257. usb device interrupt enable register (devinten - address 0x2008 c204) bit description bit symbol description reset value 0 frameen 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 1 ep_fasten 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 2 ep_slowen 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 3 dev_staten 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 4 ccemptyen 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 5 cdfullen 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 6 rxendpkten 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 7 txendpkten 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 332 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.2.3 usb device interrupt clear register writing one to a bit in this register clears th e corresponding bit in usbdevintst. writing a zero has no effect. usbdevintc lr is a write-only register. remark: before clearing the ep_slow or ep_fast interrupt bits, the corresponding endpoint interrupts in usbepintst should be cleared. 8 ep_rlzeden 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 )) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 9 err_inten 0 = no interrupt is generated. 1 = an interrupt will be generated when the corresponding bit in the device interrupt status (devintst) register ( table 256 ) is set. by default, the interrupt is routed to the usb_int_req_lp interrupt line. optionally, either the ep_fast or frame interrupt may be routed to the usb_int_req_hp interrupt line by changing the value of usbdevintpri. 0 31:10 - reserved - table 257. usb device interrupt enable register (devinten - address 0x2008 c204) bit description bit symbol description reset value table 258. usb device interrupt clear register (devintclr - address 0x2008 c208) bit description bit symbol description 0 frameclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 1 ep_fastclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 2 ep_slowclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 3 dev_statclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 4 ccemptyclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 5 cdfullclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 6 rxendpktclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 7 txendpktclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 8 ep_rlzedclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 9 err_intclr 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is cleared. 31:10 - reserved
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 333 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.2.4 usb device interrupt set register writing one to a bit in this register sets the corresponding bit in the usbdevintst . writing a zero has no effect. usbdevints et is a write-only register. table 259. usb device interrupt set register (devintset - address 0x2008 c20c) bit description bit symbol description 0 frameset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 1 ep_fastset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 2 ep_slowset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 3 dev_statset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 4 ccemptyset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 5 cdfullset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 6 rxendpktset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 7 txendpktset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 8 ep_rlzedset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 9 err_intset 0 = no effect. 1 = the corresponding bit in usbdevintst ( section 12.10.2.1 ) is set. 31:10 - reserved
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 334 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.2.5 usb device interrupt priority register writing one to a bit in this register causes the corresponding interrupt to be routed to the usb_int_req_hp interrupt line. writing zero causes the interrupt to be routed to the usb_int_req_lp interrupt line. either the ep_ fast or frame interrupt can be routed to usb_int_req_hp, but not both. if the software attempts to set both bits to one, no interrupt will be routed to us b_int_req_hp. usbdevintpri is a write-only register. table 260. usb device interrupt priority register (devintpri - address 0x2008 c22c) bit description bit symbol value description reset value 0 frame frame interrupt routing 0 0 frame interrupt is routed to usb_int_req_lp. 1 frame interrupt is routed to usb_int_req_hp. 1 ep_fast fast endpoint interrupt routing 0 0 ep_fast interrupt is routed to usb_int_req_lp. 1 ep_fast interrupt is routed to usb_int_req_hp. 31:2 - reserved. read value is undefined, only zero should be written. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 335 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.3 endpoint in terrupt registers the registers in this group facilitate handling of endpoint interr upts. endpoint interrupts are used in slave mode operation. 12.10.3.1 usb endpoint interrupt status register each physical non-isochronous endpoint is repres ented by a bit in this register to indicate that it has generated an interrupt. all non-isochronous out endpoints generate an interrupt when they receive a packet without an error. all non-isoc hronous in endpoints generate an interrupt when a packet is successfully transmitted, or when a nak handshake is sent on the bus and the interrupt on nak feature is enabled (see section 12.12.3 ? set mode (command: 0xf3, data: write 1 byte) ? on page 358 ). a bit set to one in this register causes either the ep_fast or ep_slow bit of usbdevintst to be set depending on the value of the corresponding bit of usbepdevintpri. usbepintst is a read-only register. note that for isochronous endpoints, handlin g of packet data is done when the frame interrupt occurs. table 261. usb endpoint registers bit allocation bit 31 30 29 28 27 26 25 24 symbol epx31 = ep15tx epx30 = ep15rx epx29 = ep14tx epx28 = ep14rx epx27 = ep13tx epx26 = ep13rx epx25 = ep12tx epx24 = ep12rx bit 23 22 21 20 19 18 17 16 symbol epx23 = ep11tx epx22 = ep11rx epx21 = ep10tx epx20 = ep10rx epx19 = ep9tx epx18 = ep9rx epx17 = ep8tx epx16 = ep8rx bit 15 14 13 12 11 10 9 8 symbol epx15 = ep7tx epx14 = ep7rx epx13 = ep6tx epx12 = ep6rx epx11 = ep5tx epx10 = ep5rx epx9 = ep4tx epx8 = ep4rx bit 7 6 5 4 3 2 1 0 symbol epx7 = ep3tx epx6 = ep3rx epx5 = ep2tx epx4 = ep2rx epx3 = ep1tx epx2 = ep1rx epx1 = ep0tx epx0 = ep0rx table 262. usb endpoint interrupt status register (epintst - address 0x2008 c230) bit description bit symbol description reset value 31:0 epst 1 = endpoint data received (bits 0, 2, 4, ..., 30) or transmitted (b its 1, 3, 5, ..., 31) interrupt received. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 336 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.3.2 usb endpoint interrupt enable register setting a bit to 1 in this register causes the corresponding bit in usbepintst to be set when an interrupt occurs for the associated endpoint. setting a bit to 0 causes the corresponding bit in usbdmarst to be set when an interrupt occurs for the associated endpoint. usbepinten is a read/write register. 12.10.3.3 usb endpoint interrupt clear register writing a one to this a bit in this register causes the sie select endpoint/clear interrupt command to be executed ( table 304 ) for the corresponding physical endpoint. writing zero has no effect. before executing the select endpoint/clear interrupt command, the cdfull bit in usbdevintst is cleared by ha rdware. on completion of the command, the cdfull bit is set, usbcmddata contains the status of the endpoint, and the corresponding bit in u sbepintst is cleared. notes: ? when clearing interrupts using usbepintclr , software should wait for cdfull to be set to ensure the corresponding interr upt has been cleared before proceeding. ? while setting multiple bits in usbepintcl r simultaneously is possible, it is not recommended; only the status of the endpoin t corresponding to the least significant interrupt bit cleared w ill be available at the e nd of the operation. ? alternatively, the sie select endpoint/c lear interrupt command can be directly invoked using the sie command registers, but using usbepintclr is recommended because of its ease of use. each physical endpoint has its own reserved bit in this register. the bit field definition is the same as that of epintst shown in table 262 . epintclr is a wr ite-only register. table 263. usb endpoint interrupt enable register (epinten - address 0x2008 c234) bit description bit symbol description reset value 31:0 epen 0= the corresponding bit in usbdmarst is set when an interrupt o ccurs for this endpoint. 1 = the corresponding bit in usbepintst is se t when an interrupt occurs for this endpoint. implies slave mode for this endpoint. 0 table 264. usb endpoint interrupt clear register (epintclr - address 0x2008 c238) bit description bit symbol description 31:0 epclr 0 = no effect. 1 = clears the corresponding bit in usbepintst, by executing the sie select endpoint/clear interrupt command for this endpoint.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 337 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.3.4 usb endpoint interrupt set register writing a one to a bit in this register sets the corresponding bit in usbepintst. writing zero has no effect. each endpoint has its own bit in this register. usbepintset is a write-only register. 12.10.3.5 usb endpoint interrupt priority register this register determines whether an endpoi nt interrupt is routed to the ep_fast or ep_slow bits of usbdevintst. if a bit in this register is set to one, the interrupt is routed to ep_fast, if zero it is routed to ep_slow . routing of multiple endpoints to ep_fast or ep_slow is possible. note that the usbdevintpri r egister determines whether the ep_fast interrupt is routed to the usb_int_req_hp or usb_int_req_lp interrupt line. usbepintpri is a write-only register. table 265. usb endpoint interrupt set register (epintset - address 0x2008 c23c) bit description bit symbol description 31:0 epset 0 = no effect. 1 = sets the correspondi ng bit in usbepintst. table 266. usb endpoint interrupt priority register (epintpri - address 0x2008 c240) bit description bit symbol description reset value 31:0 eppri 0 = the corresponding interrupt is routed to the ep_slow bit of usbdevintst 1 = the corresponding interrupt is routed to the ep_fast bit of usbdevintst 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 338 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.4 endpoint real ization registers the registers in this group allow realization and configuration of endpoints at run time. 12.10.4.1 ep ram requirements the usb device controller uses a ram based fifo for each endpoint buffer. the ram dedicated for this purpose is called the en dpoint ram (ep_ram). each endpoint has space reserved in the ep_ram. the ep_ram space required for an endpoint depends on its maxpacketsize and whether it is doubl e buffered. 32 words of ep_ram are used by the device for storing the endpoint buffer pointers. the ep_ram is word aligned but the maxpacketsize is defined in bytes hence th e ram depth has to be adjusted to the next word boundary. also, each buffer has one word header showing the size of the packet length received. the ep_ ram space (in words) required for the physical endpoint can be expressed as where dbstatus = 1 for a single buffered endpoint and 2 for double a buffered endpoint. since all the realized endpoints occupy ep_ ram space, the total ep_ram requirement is where n is the number of realized endpoints. total ep_ram space should not exceed 4096 bytes (4 kb, 1 kwords). epramspace maxpacketsize 3 + 4 ------------------------------------------------- - 1 + ?? ?? dbstatus ? = totalepramspace 32 epramspace n ?? n0 = n ? +=
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 339 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.4.2 usb realize endpoint register writing one to a bit in this register causes the corresponding endpoint to be realized. writing zeros causes it to be unrealized. this register returns to its reset state when a bus reset occurs. usbreep is a read/write register. on reset, only the control endpoints are realiz ed. other endpoints, if required, are realized by programming the corresponding bits in usbreep. to calculate the required ep_ram space for the realized endpoints, see section 12.10.4.1 . realization of endpoints is a multi-cycle operation. pseudo code for endpoint realization is shown below. clear ep_rlzed bit in usbdevintst; for every endpoint to be realized, { /* or with the existing value of the realize endpoint register */ usbreep |= (uint32) ((0x1 << endpt)); /* load endpoint index reg with physical endpoint no.*/ usbepin = (uint32) endpointnumber; /* load the max packet size register */ usbepmaxpsize = mps; /* check whether the ep_rlzed bit in the device interrupt status register is set */ while (!(usbdevintst & ep_rlzed)) { /* wait until endpoint realization is complete */ } /* clear the ep_rlzed bit */ clear ep_rlzed bit in usbdevintst; } the device will not re spond to any transac tions to unrealized endpoints. the sie configure device command will only cause realized and enabled endpoints to respond to transactions. for details see table 299 . table 267. usb realize endpoint register (reep - address 0x2008 c244) bit description bit symbol description reset value 31:0 epr 0 = endpoint epxx is not realized. 1 = endpoint epxx is realized. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 340 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.4.3 usb endpoint index register each endpoint has a register carrying the maxpacketsize value for that endpoint. this is in fact a register array. hence before writ ing, this register is addressed through the usbepin register. the usbepin register will hold the physical endpoint numb er. writing to usbmaxpsize will set the array element pointed to by usbepin. usbepin is a write-only register. 12.10.4.4 usb maxpacketsize register on reset, the control endpoint is assigned the maximum packet size of 8 bytes. other endpoints are assigned 0. modifying usbmaxpsize will ca use the endpoint buffer addresses within the ep_ram to be recalculated. this is a multi-cycle process. at the end, the ep_rlzed bit will be set in usbdevintst ( table 256 ). usbmaxpsize array indexing is shown in figure 42 . usbmaxpsize is a read/write register. [1] reset value for ep0 and ep1. all other endpoints have a reset value of 0x0. table 268. usb endpoint index register (epin - address 0x2008 c248) bit description bit symbol description reset value 4:0 phy_ep physical endpoint number (0-31) 0 31:5 - reserved. read value is undefined, only zero should be written. na table 269. usb maxpacketsize register (maxpsize - address 0x2008 c24c) bit description bit symbol description reset value 9:0 mps the maximum packet size value. 0x008 [1] 31:10 - reserved. read value is undefined, only zero should be written. na the endpoint index is set via the usbepin regi ster. mps_ep0 to mps_ep31 are accessed via the usbmaxpsize register. fig 42. usb maxpacketsize register array indexing endpoint index mps_ep0 mps_ep31
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 341 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.5 usb transfer registers the registers in this group are used for transferring data between endpoint buffers and ram in slave mode operation. see section 12.14 ? slave mode operation ? . 12.10.5.1 usb receive data register for an out transaction, the cpu reads the endpo int buffer data from this register. before reading this register, the rd_en bit and lo g_endpoint field of the usbctrl register should be set appropriately. on reading this register, data from the selected endpoint buffer is fetched. the data is in little endian format: the first byte received from the usb bus will be available in the le ast significant byte of usbrxd ata. usbrxdata is a read-only register. 12.10.5.2 usb receive packet length register this register contains the number of bytes remaining in the endpoint buffer for the current packet being read via the usbrxdata register, and a bit indicating whether the packet is valid or not. before reading this register , the rd_en bit and log_endpoint field of the usbctrl register should be set appropriately. th is register is updated on each read of the usbrxdata register. usbrxpl en is a read-only register. table 270. usb receive data register (rxdata - address 0x2008 c218) bit description bit symbol description reset value 31:0 rx_data data received. 0 table 271. usb receive packet length register (rxplen - address 0x2008 c220) bit description bit symbol value description reset value 9:0 pkt_lngth - the remaining number of bytes to be read from the currently selected endpoint?s buffer. when this field decrements to 0, the rxendpkt bit will be set in usbdevintst. 0 10 dv data valid. this bit is useful fo r isochronous endpoints. non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. but invalid data packet can be produced with a bus reset. for isochronous endpoints, data transfer will happen even if an erroneous packet is received. in this case dv bit will not be set for the packet. 0 0 data is invalid. 1 data is valid. 11 pkt_rdy the pkt_lngth field is valid and the packet is ready for reading. 0 31:12 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 342 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.5.3 usb transmit data register for an in transaction, the cpu wr ites the endpoint data into this register. before writing to this register, the wr_en bit and log_endpoint field of the usbctrl register should be set appropriately, and the packet length shoul d be written to the usbtxplen register. on writing this register, the data is written to the selected endpoint buffer. the data is in little endian format: the firs t byte sent on the usb bus will be the least significant byte of usbtxdata. usbtxdata is a write-only register. 12.10.5.4 usb transmit packet length register this register contains the number of byte s transferred from the cpu to the selected endpoint buffer. before writing data to usbt xdata, software should first write the packet length ( ?? maxpacketsize) to this register. afte r each write to usbtxdata, hardware decrements usbtxplen by 4. the wr_en bit and log_endpoint field of the usbctrl register should be set to select the desired en dpoint buffer before starting this process. for data buffers larger than the endpoint?s maxpacketsize, software should submit data in packets of maxpacketsize, and send the remaining extra bytes in the last packet. for example, if the maxpacketsize is 64 bytes and the data buffer to be transferred is of length 130 bytes, then the software sends two 64-byte packets and the remaining 2 bytes in the last packet. so, a total of 3 packet s are sent on usb. usbt xplen is a write-only register. table 272. usb transmit data register (txdata - address 0x2008 c21c) bit description bit symbol description 31:0 tx_data transmit data. table 273. usb transmit packet length register (txplen - address 0x2008 c224) bit description bit symbol description reset value 9:0 pkt_lngth the remaining number of bytes to be written to the selected endpoint buffer. this field is decremented by 4 by hardware after each write to usbtxdata. when this field decrements to 0, the txendpkt bit will be set in usbdevintst. 0 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 343 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.5.5 usb control register this register controls the data transfer operation of the usb device. it selects the endpoint buffer that is accessed by the usbrxdata and usbtxdata registers, and enables reading and writing them. usbctrl is a read/write register. table 274. usb control register (ctrl - address 0x2008 c228) bit description bit symbol value description reset value 0 rd_en read mode control. enables reading data from the out endpoint buffer for the endpoint specified in the log_endpoint field using the usbrxdata register. this bit is cleared by hardware when the last word of the current packet is read from usbrxdata. 0 0 disabled. 1 enabled. 1 wr_en write mode control. enables writing data to the in endpoint buffer for the endpoint specified in the log_endpoint field using the usbtxdata register. this bit is cleared by hardware when the number of bytes in usbtxlen have been sent. 0 0 disabled. 1 enabled. 5:2 log_endpoint logical endpoint number. 0 31:6 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 344 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.6 sie command code registers the sie command code registers are used for communicating with the serial interface engine. see section 12.12 ? serial interface engine command description ? for more information. 12.10.6.1 usb command code register this register is used for sending the comm and and write data to the sie. the commands written here are propagated to the sie and executed there. after executing the command, the register is empty, and the ccempty bi t of usbdevintst register is set. see section 12.12 for details. usbcmdcode is a write-only register. 12.10.6.2 usb command data register this register contains the data retrieved af ter executing a sie command. when the data is ready to be read, the cd_full bit of the usbdevintst register is set. see table 256 for details. usbcmddata is a read-only register. table 275. usb command code register (cmdcode - address 0x2008 c210) bit description bit symbol value description 7:0 - reserved. read value is undefined, only zero should be written. 15:8 cmd_phase the command phase: 0x02 read 0x01 write 0x05 command 23:16 cmd_code_wdata this is a multi-purpose field. when cmd_phase is command or read, this field contains the code for the command (cmd_code). when cmd_phase is write, this field contains the command write data (cmd_wdata). 31:24 - reserved. read value is undefined, only zero should be written. table 276. usb command data register (cmddata - address 0x2008 c214) bit description bit symbol description reset value 7:0 cmd_rdata command read data. 0 31:8 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 345 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7 dma registers the registers in this group are used for the dma mode of operation (see section 12.15 ? dma operation ? ) 12.10.7.1 usb dma request status register a bit in this register associated with a non-isochronous endpoint is set by hardware when an endpoint interrupt occurs (see the description of usbepin tst) and the corresponding bit in usbepinten is 0. a bit associated wi th an isochronous endpoint is set when the corresponding bit in usbepinten is 0 and a frame interrupt occurs. a set bit serves as a flag for the dma engine to start the data transfer if the dma is enabled for the corresponding endpoint in the usbepdmast regist er. the dma cannot be enabled for control endpoints (ep0 and ep1). usbdmarst is a read-only register. [1] dma can not be enabled for this endpoint and the corresponding bit in the usbdmarst must be 0. table 277. usb dma request status register (dmarst - address 0x2008 c250) bit description bit symbol description reset value 0 eprst0 control endpoint out (dma cannot be enabled for this endpoint and ep0 bit must be 0). 0 1 eprst1 control endpoint in (dma cannot be enabled for this endpoint and ep1 bit must be 0). 0 31:2 eprst endpoint xx (2 ? ? xx ? ? 31) dma request. 0 = dma not requested by endpoint xx. 1 = dma requested by endpoint xx. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 346 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.2 usb dma request clear register writing one to a bit in this register will clear the correspond ing bit in the usbdmarst register. writing zero has no effect. this register is intended for initialization prior to enabling the dma for an endpoint. when the dma is enabled for an endpoint, hardw are clears the corresponding bit in usbdmarst on completion of a packet transfer. therefore, software should not clear the bit using this register while the endpoint is enabled for dma operation. usbdmarclr is a write-only register. the usbdmarclr bit allocation is ident ical to the usbdmarst register ( table 277 ). 12.10.7.3 usb dma request set register writing one to a bit in this register sets the corresponding bit in the usbdmarst register. writing zero has no effect. this register allows software to raise a dma request. this can be useful when switching from slave to dma mode of operation for an endpoint: if a packet to be processed in dma mode arrives before the corr esponding bit of usbepinten is cleared, the dma request is not raised by hardware. softwa re can then use this register to manually start the dma transfer. software can also use this re gister to initiate a dma tran sfer to proactively fill an in endpoint buffer before an in token packet is received from the host. usbdmarset is a write-only register. the usbdmarset bit allocation is id entical to the usbdmarst register ( table 277 ). table 278. usb dma request clear register (dmarclr - address 0x2008 c254) bit description bit symbol description 0 eprclr0 control endpoint out (dma cannot be enabled for this endpoint and the ep0 bit must be 0). 1 eprclr1 control endpoint in (dma cannot be enabled for this endpoint and the ep1 bit must be 0). 31:2 eprclr clear the endpoint xx (2 ? ? xx ? ? 31) dma request. 0 = no effect 1 = clear the corresponding bit in usbdmarst. table 279. usb dma request set register (dmarset - address 0x2008 c258) bit description bit symbol description 0 eprset0 control endpoint out (dma cannot be enabled for this endpoint and the ep0 bit must be 0). 1 eprset1 control endpoint in (dma cannot be enabled for this endpoint and the ep1 bit must be 0). 31:2 eprset set the endpoint xx (2 ? ? xx ? ? 31) dma request. 0 = no effect 1 = set the corresponding bit in dmarst.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 347 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.4 usb udca head register the udca (usb device communication area) head register maintains the address where the udca is located in the ram. refer to section 12.15.2 ? usb device communication area ? and section 12.15.4 ? the dma descriptor ? for more details on the udca and dma descriptors. udcah is a read/write register. 12.10.7.5 usb ep dma status register bits in this register indicate whether dm a operation is enabled for the corresponding endpoint. a dma transfer for an endpoint can start only if the corresponding bit is set in this register. epdmast is a read-only register. 12.10.7.6 usb ep dma enable register writing one to a bit to this register will en able the dma operation for the corresponding endpoint. writing zero has no effect.the dma cannot be enabled for control endpoints ep0 and ep1. epdmaen is a write-only register. table 280. usb udca head re gister (udcah - address 0x2008 c280) bit description bit symbol description reset value 6:0 - reserved. read value is undefined, only zero should be written. the udca is aligned to 128-byte boundaries. 0 31:7 udca_addr start address of the udca. 0 table 281. usb ep dma status register (epdmast - address 0x2008 c284) bit description bit symbol description reset value 0 ep_dma_st0 control endpoint out (dma cannot be enabled for this endpoint and the ep0_dma_enable bit must be 0). 0 1 ep_dma_st1 control endpoint in (dma cannot be enabled for this endpoint and the ep1_dma_enable bit must be 0). 0 31:2 ep_dma_st endpoint xx (2 ? ? xx ? ? 31) dma enabled bit. 0 = the dma for endpoint epxx is disabled. 1 = the dma for endpoint epxx is enabled. 0 table 282. usb ep dma enable register (epdmaen - address 0x2008 c288) bit description bit symbol description 0 ep_dma_en0 control endpoint out (dma cannot be enabled for this endpoint and the ep0_dma_enable bit value must be 0). 1 ep_dma_en1 control endpoint in (dma cannot be enabled for this endpoint and the ep1_dma_enable bit must be 0). 31:2 ep_dma_en endpoint xx(2 ? ? xx ? ? 31) dma enable control bit. 0 = no effect. 1 = enable the dma operation for endpoint epxx.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 348 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.7 usb ep dma disable register writing a one to a bit in this register clears the corresponding bit in epdmast. writing zero has no effect on the corresponding bit of epdmast. any write to this register clears the internal dma_proceed flag. refer to section 12.15.5.4 ? optimizing descriptor fetch ? for more information on the dma_proceed flag. if a dma transfer is in progress for an endpoint when its corresponding bit is cleared, the transfer is completed before the dma is disabled. when an error condition is dete cted during a dma transfer, the corresponding bit is cleared by hardware. epdm adis is a write-only register. 12.10.7.8 usb dma interrupt status register each bit of this register reflects whether any of the 32 bits in the corresponding interrupt status register are set. dmaintst is a read-only register. table 283. usb ep dma disable register (epdmadis - address 0x2008 c28c) bit description bit symbol description 0 ep_dma_dis0 control endpoint out (dma cannot be enabled for this endpoint and the ep0_dma_disable bit value must be 0). 1 ep_dma_dis1 control endpoint in (dma cannot be enabled for this endpoint and the ep1_dma_disable bit value must be 0). 31:2 ep_dma_dis endpoint xx (2 ? ? xx ? ? 31) dma disable control bit. 0 = no effect. 1 = disable the dma operation for endpoint epxx. table 284. usb dma interrupt status register (dmaintst - address 0x2008 c290) bit description bit symbol value description reset value 0 eot end of transfer interrupt bit. 0 0 all bits in the eotintst register are 0. 1 at least one bit in the eotintst is set. 1 nddr new dd request interrupt bit. 0 0 all bits in the nddrintst register are 0. 1 at least one bit in the nddrintst is set. 2 err system error interrupt bit. 0 0 all bits in the syserrintst register are 0. 1 at least one bit in the syserrintst is set. 31:3 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 349 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.9 usb dma interrupt enable register writing a one to a bit in this register enables the corresponding bit in dmaintst to generate an interrupt on the u sb_int_req_dma interrupt line when set. dmainten is a read/write register. 12.10.7.10 usb end of transfer interrupt status register when the dma transfer completes for the current dma descriptor, either normally (descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in this register. the cause of the interrupt is reco rded in the dd_status field of the descriptor. eotintst is a read-only register. 12.10.7.11 usb end of transfer interrupt clear register writing one to a bit in this register clears th e corresponding bit in the eotintst register. writing zero has no effect. eotintclr is a write-only register. table 285. usb dma interrupt enable register (dmainten - address 0x2008 c294) bit description bit symbol value description reset value 0 eot end of transfer interrupt enable bit. 0 0 disabled. 1 enabled. 1 nddr new dd request interrupt enable bit. 0 0 disabled. 1 enabled. 2 err system error interrupt enable bit. 0 0 disabled. 1 enabled. 31:3 - reserved. read value is undefined, only zero should be written. na table 286. usb end of transfer interrupt status register (eotintst - address 0x2008 c2a0) bit description bit symbol description reset value 31:0 eptxintst endpoint xx (2 ? ? xx ? ? 31) end of transfer interrupt request. 0 = there is no end of transfer interrupt request for endpoint xx. 1 = there is an end of transfer interrupt request for endpoint xx. 0 table 287. usb end of transfer interrupt clear register (eotintclr - address 0x2008 c2a4) bit description bit symbol description 31:0 eptxintclr clear endpoint xx (2 ? ? xx ? ? 31) end of transfer interrupt request. 0 = no effect. 1 = clear the epxx end of transfer interrupt request in the eotintst register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 350 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.12 usb end of transfer interrupt set register writing one to a bit in this register sets th e corresponding bit in the eotintst register. writing zero has no effect. eoti ntset is a write-only register. 12.10.7.13 usb new dd request interrupt status register a bit in this register is set when a transfer is requested from the usb device and no valid dd is detected for the corresponding endpoint. nddrintst is a read-only register. 12.10.7.14 usb new dd request interrupt clear register writing one to a bit in this register clears th e corresponding bit in the nddrintst register. writing zero has no effect. nddrintclr is a write-only register. 12.10.7.15 usb new dd request interrupt set register writing one to a bit in this register sets the corresponding bit in the nddrintst register. writing zero has no effect. nddrintset is a write-only register table 288. usb end of transfer interrupt set register (eotintset - address 0x2008 c2a8) bit description bit symbol description 31:0 eptxintset set endpoint xx (2 ? ? xx ? ? 31) end of transfer interrupt request. 0 = no effect. 1 = set the epxx end of transfer interrupt request in the eotintst register. table 289. usb new dd request interrupt status register (nddrintst - address 0x2008 c2ac) bit description bit symbol description reset value 31:0 epnddintst endpoint xx (2 ? ? xx ? ? 31) new dd interrupt request. 0 = there is no new dd interrupt request for endpoint xx. 1 = there is a new dd interrupt request for endpoint xx. 0 table 290. usb new dd request interrupt clear register (nddrintclr - address 0x2008 c2b0) bit description bit symbol description 31:0 epnddintclr clear endpoint xx (2 ? ? xx ? ? 31) new dd interrupt request. 0 = no effect. 1 = clear the epxx new dd interrupt request in the nddrintst register. table 291. usb new dd request interrupt set register (nddrintset - address 0x2008 c2b4) bit description bit symbol description 31:0 epnddintset set endpoint xx (2 ? ? xx ? ? 31) new dd interrupt request. 0 = no effect. 1 = set the epxx new dd interrupt request in the nddrintst register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 351 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.7.16 usb system error interrupt status register if a system error (ahb bus error) occurs when transferring the data or when fetching or updating the dd the corresponding bit is set in this register. syserrintst is a read-only register. 12.10.7.17 usb system error interrupt clear register writing one to a bit in this register clears th e corresponding bit in the syserrintst register. writing zero has no effect. syserr intclr is a write-only register. 12.10.7.18 usb system error interrupt set register writing one to a bit in this register sets th e corresponding bit in the syserrintst register. writing zero has no effect. syserrintset is a write-only register. table 292. usb system error interrupt status regist er (syserrintst - address 0x2008 c2b8) bit description bit symbol description reset value 31:0 eperrintst endpoint xx (2 ? ? xx ? ? 31) system error interrupt request. 0 = there is no system error interrupt request for endpoint xx. 1 = there is a system error interrupt request for endpoint xx. 0 table 293. usb system error interru pt clear register (syserrintclr - address 0x2008 c2bc) bit description bit symbol description 31:0 eperrintclr clear endpoint xx (2 ? ? xx ? ? 31) system error interrupt request. 0 = no effect. 1 = clear the epxx system error interrupt request in the syserrintst register. table 294. usb system error interrupt set register (syserrintset - address 0 x2008 c2c0) bi t description bit symbol description 31:0 eperrintset set endpoint xx (2 ? ? xx ? ? 31) system error interrupt request. 0 = no effect. 1 = set the epxx system e rror interrupt request in the syserrintst register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 352 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.10.8 clock control registers 12.10.8.1 usb clock control register this register controls the clocking of t he usb device controller. whenever software wants to access the device controller regi sters, both dev_clk_ en and ahb_clk_en must be set. the portsel_clk_en bit need only be set when accessing the portsel register. the software does not have to repeat this exer cise for every register access, provided that the corresponding clkctrl bits are already set. note that this register is functional only when the pcusb bit of pconp is set; when pcusb is cleared, all clocks to the device controller are disabled irrespective of the contents of this register. clkctrl is a read/write register. 12.10.8.2 usb clock status register this register holds the clock av ailability status. the bits of th is register are ored together to form the usb_need_clk signal. when enab ling a clock via clkctrl, software should poll the corresponding bit in clkst. if it is set, then software can go ahead with the register access. software does not have to repeat this exercise for every access, provided that the clkctrl bits are not disturbed. clkst is a read-only register. table 295. clkctrl register (clkctrl - address 0x2008 cff4) bit description bit symbol description reset value 0 - reserved. read value is undefined, only zero should be written. na 1 dev_clk_en device clock enable. enables the usbclk input to the device controller 0 2 - reserved. read value is undefined, only zero should be written. na 3 portsel_clk_en port select register clock enable. na 4 ahb_clk_en ahb clock enable 0 31:5 - reserved. read value is undefined, only zero should be written. na table 296. usb clock status register (clkst - address 0x2008 cff8) bit description bit symbol description reset value 0 - reserved. read value is undefined, only zero should be written. na 1 dev_clk_on device clock on. the usbclk inpu t to the device controller is active. 0 2 - reserved. read value is undefined, only zero should be written. na 3 portsel_clk_on port select register clock on. na 4 ahb_clk_on ahb clock on. 0 31:5 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 353 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.11 interrupt handling this section describes how an interrupt event on any of the endpoints is routed to the nested vectored interrupt controller (nvic) . for a diagram showing interrupt event handling, see figure 43 . all non-isochronous out endpoints (control, bulk, and interrupt endpoints) generate an interrupt when they receive a packet without an error. all non-isoc hronous in endpoints generate an interrupt when a packet has been successfully transmitted or when a nak signal is sent and interrupts on nak are enabled by the sie set mode command, see section 12.12.3 . for isochronous endpoints, a frame interrupt is generated every 1 ms. the interrupt handling is different for slave and dma mode. slave mode if an interrupt event occurs on an endpoint and the endpoint interrupt is enabled in the epinten register, the corresponding status bit in the epintst is set. for non-isochronous endpoints, all endpoint interrupt events are divided into two types by the corresponding epintpri[n] registers: fast endpoint interrupt events and slow endpoint interrupt events. all fast endpoint interrupt events are ored and routed to bit ep_fast in the devintst register. all slow endpoint interrupt events are ored and routed to the ep_slow bit in devintst. for isochronous endpoints, the frame bit in devintst is set every 1 ms. the devintst register holds the status of all endpoint interrupt events as well as the status of various other interrupts (see section 12.10.2.1 ). by default, all interrupts (if enabled in devinten) are routed to the usb_int_req_lp bit in the intst register to request low priority interrupt handling. however, the devi ntpri register can route either the frame or the ep_fast bit to the usb_int_req_hp bit in the intst register. only one of the ep_fast and frame interrupt events can be routed to the usb_int_req_hp bit. if routing both bits to usb_int_req_hp is attempted, both interrupt events are rout ed to usb_int_req_lp. slow endpoint interrupt events are always rout ed directly to the usb_int_req_lp bit for low priority interrupt handling by software. the final interrupt signal to the nvic is gated by the en_usb_in ts bit in the intst register. the usb interrupts are routed to the nvic only if en_usb_ints is set. dma mode if an interrupt event occurs on a non-control endpoint and the endpoint interrupt is not enabled in the epinten register, the correspo nding status bit in the dmarst is set by hardware. this serves as a flag for the dma engine to transfer data if dma transfer is enabled for the corresponding endpoint in the epdmast register. three types of interrupts can occur for each endpoint for data transfers in dma mode: end of transfer interrupt, new dd request interrupt, and system erro r interrupt. th ese interrupt events set a bit for each endpoint in the re spective registers eotintst, nddrintst, and syserrintst. the end of transfe r interrupts from all endpoints are then ored and routed to
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 354 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller the eot bit in dmaintst. likewise, all ne w dd request interrupts and system error interrupt events are routed to the nddr an d err bits respectively in the dmastint register. the eot, nddr, and err bits (if enabled in dmainten) are ored to set the usb_int_req_dma bit in the intst register. if the en_usb_ints bit is set in intst, the interrupt is routed to the nvic.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 355 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller for simplicity, devinten and dmainten are not shown. fig 43. interrupt event handling usb_int_req_hp usb_int_req_lp usb_int_req_dma en_usb_ints to nvic . . . . . . . . . . . . . . . . . . . . . . . . frame ep_fast ep_slow usbdevintpri[0] usbdevintpri[1] usbepintpri[n] usbepintst usbdmarst to dma engine interrupt event on epn n n . . . . 0 31 . . . . 0 31 . . . . 0 31 usbeotintst usbnddrintst usbsyserrintst eot nddr err usbdevintst usbintst usbepinten[n] from other endpoints usbdmaintst slave mode dma mode err_int
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 356 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12 serial interface engine command description the functions and registers of the serial interface engine (sie) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). the cmdcode ( table 275 ) and cmddata ( table 276 ) registers are used for these accesses. a complete access consists of two phases: 1. command phase: the cmdcode register is writte n with the cmd_phase field set to the value 0x05 (command), and the cmd_code field set to the desired command code. on completion of the command, th e ccempty bit of devintst is set. 2. data phase (optional): for writes, the cmdcode regi ster is written with the cmd_phase field set to the value 0x01 (w rite), and the cmd_wdata field set with the desired write data. on completion of t he write, the ccempty bit of devintst is set. for reads, cmdcode register is writ ten with the cmd_phase field set to the value 0x02 (read), and the cmd_code field set with command code the read corresponds to. on co mpletion of the read, the cdfu ll bit of devinst will be set, indicating the data is available for reading in the cmddata register. in the case of multi-byte registers, the least si gnificant byte is accessed first. an overview of the available commands is given in table 297 . here is an example of the read current frame number command (reading 2 bytes): devintclr = 0x30; // clear both ccempty & cdfull cmdcode = 0x00f50500; // cmd_code=0xf5, cmd_phase=0x05(command) while (!(devintst & 0x10)); // wait for ccempty. devintclr = 0x10; // clear ccempty interrupt bit. cmdcode = 0x00f50200; // cmd_code=0xf5, cmd_phase=0x02(read) while (!(devintst & 0x20)); // wait for cdfull. devintclr = 0x20; // clear cdfull. curframenum = cmddata; // read frame number lsb byte. cmdcode = 0x00f50200; // cmd_code=0xf5, cmd_phase=0x02(read) while (!(devintst & 0x20)); // wait for cdfull. temp = cmddata; // read frame number msb byte devintclr = 0x20; // clear cdfull interrupt bit. curframenum = curframenum | (temp << 8); here is an example of the set address command (writing 1 byte): devintclr = 0x10; // clear ccempty. cmdcode = 0x00d00500; // cmd_code=0xd0, cmd_phase=0x05(command) while (!(devintst & 0x10)); // wait for ccempty. devintclr = 0x10; // clear ccempty. cmdcode = 0x008a0100; // cmd_wdata=0x8a(dev_en=1, dev_addr=0xa), // cmd_phase=0x01(write) while (!(devintst & 0x10)); // wait for ccempty. devintclr = 0x10; // clear ccempty.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 357 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.1 set address (command: 0xd0, data: write 1 byte) the set address command is used to set the usb assigned address and enable the (embedded) function. the address set in the device will take ef fect after the status stage of the control transaction. after a bus rese t, dev_addr is set to 0x00, and dev_en is set to 1. the device will resp ond to packets for function add ress 0x00, endpoint 0 (default endpoint). table 297. sie command code table command name recipient code (hex) data phase device commands set address device d0 write 1 byte configure device device d8 write 1 byte set mode device f3 write 1 byte read current frame number device f5 read 1 or 2 bytes read test register device fd read 2 bytes set device status device fe write 1 byte get device status device fe read 1 byte get error code device ff read 1 byte read error status device fb read 1 byte endpoint commands select endpoint endpoint 0 00 read 1 byte (optional) endpoint 1 01 read 1 byte (optional) endpoint xx xx read 1 byte (optional) select endpoint/clear interrupt endpoint 0 40 read 1 byte endpoint 1 41 read 1 byte endpoint xx xx ? 40 read 1 byte set endpoint status endpoint 0 40 write 1 byte endpoint 1 41 write 1 byte endpoint xx xx ? 40 write 1 byte clear buffer selected endpoint f2 read 1 byte (optional) validate buffer selected endpoint fa none table 298. set address command bit description bit symbol description reset value 6:0 dev_addr device address set by the software. after a bus reset this field is set to 0x00. 0 7 dev_en device enable. after a bus reset this bit is set to 1. 0: device will not respond to any packets. 1: device will respond to packets for function address dev_addr. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 358 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.2 configure device (command: 0xd8, data: write 1 byte) a value of 1 written to the register indicate s that the device is configured and all the enabled non-contro l endpoints will respond. control endpoints are always enabled and respond even if the device is no t configured, in the default state. 12.12.3 set mode (command: 0xf3, data: write 1 byte) [1] this bit should be reset to 0 if the dma is enabled for any of the interrupt out endpoints. [2] this bit should be reset to 0 if the dma is enabled for any of the bulk out endpoints. table 299. configure device command bit description bit symbol description reset value 0 conf_device device is configured. all enabled non- control endpoints will respond. this bit is cleared by hardware when a bus reset occurs. when set, the up_led signal is driven low if the device is not in the suspended state (sus=0). 0 7:1 - reserved. read value is undefined, only zero should be written. na table 300. set mode command bit description bit symbol value description reset value 0 ap_clk always pll clock. 0 0 usb_need_clk is functional; the 48 mhz clock can be stopped when the device enters suspend state. 1 usb_need_clk is fixed to 1; the 48 mhz clock cannot be stopped when the device enters suspend state. 1 inak_ci interrupt on nak for control in endpoint. 0 0 only successful transactions generate an interrupt. 1 both successful and naked in transactions generate interrupts. 2 inak_co interrupt on nak for control out endpoint. 0 0 only successful transactions generate an interrupt. 1 both successful and naked out transactions generate interrupts. 3 inak_ii interrupt on nak for interrupt in endpoint. 0 0 only successful transactions generate an interrupt. 1 both successful and naked in transactions generate interrupts. 4 inak_io [1] interrupt on nak for interrupt out endpoints. 0 0 only successful transactions generate an interrupt. 1 both successful and naked out transactions generate interrupts. 5 inak_bi interrupt on nak for bulk in endpoints. 0 0 only successful transactions generate an interrupt. 1 both successful and naked in transactions generate interrupts. 6 inak_bo [2] interrupt on nak for bulk out endpoints. 0 0 only successful transactions generate an interrupt. 1 both successful and naked out transactions generate interrupts. 7 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 359 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.4 read current frame number (c ommand: 0xf5, data: read 1 or 2 bytes) returns the frame number of the last successfully received sof. the frame number is eleven bits wide. the frame number returns least significant byte first. in case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read. ? in case no sof was received by the device at the beginning of a frame, the frame number returned is that of the last successfully received sof. ? in case the sof frame number contained a crc error, the frame number returned will be the corrupted frame number as received by the device. 12.12.5 read test register (co mmand: 0xfd, data: read 2 bytes) the test register is 16 bits wide. it returns the value of 0xa50f if the usb clocks (usbclk and ahb slave clock) are running.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 360 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.6 set device status (comma nd: 0xfe, data: write 1 byte) the set device status command sets bits in the device status register. table 301. set device status command bit description bit symbol value description reset value 0 con the connect bit indicates the current connect status of the device. it controls the connect output pin, used for softconnect. reading the connect bit returns the current connect status. this bit is cleared by hardware when the v bus status input is low for more than 3 ms. the 3 ms delay filters out temporary dips in the v bus voltage. 0 0 writing a 0 will make the connect pin go high. 1 writing a 1 will make the connect pin go low. 1 con_ch connect change. 0 0 this bit is cleared when read. 1 this bit is set when the device?s pull-up resistor is disconnected because v bus disappeared. the dev_stat interrupt is generated when this bit is 1. 2 sus suspend: the suspend bit represents the current suspend state. when the device is susp ended (sus = 1) and the cpu writes a 0 into it, the device will generate a remote wake-up. this will only happen when the device is connected (con = 1). when the device is not connected or not suspended, writing a 0 has no effect. writing a 1 to this bit has no effect. 0 0 this bit is reset to 0 on any activity. 1 this bit is set to 1 when the device hasn?t seen any activity on its upstream port for more than 3 ms. 3 sus_ch suspend (sus) bit change indicator. the sus bit can toggle because: ? the device goes into the suspended state. ? the device is disconnected. ? the device receives resume si gnalling on its upstream port. this bit is cleared when read. 0 0 sus bit not changed. 1 sus bit changed. at the same time a dev_stat interrupt is generated. 4 rst bus reset bit. on a bus reset, the device will automatically go to the default state. in the default state: ? device is unconfigured. ? will respond to address 0. ? control endpoint will be in the stalled state. ? all endpoints are unrealized except control endpoints ep0 and ep1. ? data toggling is reset for all endpoints. ? all buffers are cleared. ? there is no change to the endpoint interrupt status. ? dev_stat interrupt is generated. note: bus resets are ignored when the device is not connected (con=0). 0 0 this bit is cleared when read. 1 this bit is set when the device receives a bus reset. a dev_stat interrupt is generated. 7:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 361 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.7 get device status (comma nd: 0xfe, data: read 1 byte) the get device status command returns the de vice status register. reading the device status returns 1 byte of data. the bit field de finition is same as the set device status register as shown in table 301 . remark: to ensure correct operation, the dev_st at bit of devintst must be cleared before executing the get device status command. 12.12.8 get error code (comma nd: 0xff, data: read 1 byte) different error conditions can arise inside the sie. the get error code command returns the last error code that occurred. the 4 le ast significant bits form the error code. table 302. get error code command bit description bit symbol value description reset value 3:0 ec error code. 0 0000 no error. 0001 pid encoding error. 0010 unknown pid. 0011 unexpected packet - any packet sequence violation from the specification. 0100 error in token crc. 0101 error in data crc. 0110 time out error. 0111 babble. 1000 error in end of packet. 1001 sent/received nak. 1010 sent stall. 1011 buffer overrun error. 1100 sent empty packet (iso endpoints only). 1101 bitstuff error. 1110 error in sync. 1111 wrong toggle bit in data pid, ignored data. 4 ea - the error active bit will be reset once this register is read. 7:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 362 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.9 read error status (comma nd: 0xfb, data: read 1 byte) this command reads the 8-bit error register from the usb device. this register records which error events have recently occurred in the sie. if any of these bits are set, the err_int bit of devintst is set. the error bi ts are cleared after reading this register. table 303. read error status command bit description bit symbol description reset value 0 pid_err pid encoding error or unknown pid or token crc. 0 1 uepkt unexpected packet - any packet sequenc e violation from the specification. 0 2 dcrc data crc error. 0 3 timeout time out error. 0 4 eop end of packet error. 0 5 b_ovrn buffer overrun. 0 6 btstf bit stuff error. 0 7 tgl_err wrong toggle bit in data pid, ignored data. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 363 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.10 select endpoint (command: 0x00 - 0x1f, data: read 1 byte (optional)) the select endpoint command initializes an internal pointer to the start of the selected buffer in ep_ram. optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s). the command code of the select endpoint command is equal to the physical endpoint number. in the case of a single buffered endpoint the b_2_full bit is not valid. table 304. select endpoint command bit description bit symbol value description reset value 0 fe full/empty. this bit indicates the full or empty status of the endpoint buffer(s). for in endpoints, the fe bit gives the anded result of the b_1_full and b_2_full bits. for out endpoints, the fe bit gives ored result of the b_1_full and b_2_full bits. for single buffered endpoints, this bit simply reflects the status of b_1_full. 0 0 for an in endpoint, at least one write endpoint buffer is empty. 1 for an out endpoint, at least one endpoint read buffer is full. 1 st stalled endpoint indicator. 0 0 the selected endpoint is not stalled. 1 the selected endpoint is stalled. 2 stp setup bit: the value of this bit is updated after each successfully received packet (i.e. an acked package on that particular physical endpoint). 0 0 the stp bit is cleared by doing a select endpoint/clear interrupt on this endpoint. 1 the last received packet for the se lected endpoint was a setup packet. 3 po packet over-written bit. 0 0 the po bit is cleared by the ?select endpoint/clear interrupt? command. 1 the previously received packet was over-written by a setup packet. 4 epn ep naked bit indicates sending of a nak. if the host sends an out packet to a filled out buffer, the device returns nak. if the host sends an in token packet to an empty in buffer, the device returns nak. 0 0 the epn bit is reset after the device has sent an ack after an out packet or when the device has seen an ack after sending an in packet. 1 the epn bit is set when a nak is sent and the interrupt on nak feature is enabled. 5 b_1_full the buffer 1 status. 0 0 buffer 1 is empty. 1 buffer 1 is full. 6 b_2_full the buffer 2 status. 0 0 buffer 2 is empty. 1 buffer 2 is full. 7 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 364 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.11 select endpoint/clear interrupt (command: 0x40 - 0x5f, data: read 1 byte) commands 0x40 to 0x5f are identical to their select endpoint equivalents, with the following differences: ? they clear the bit corresponding to the endpoint in the epintst register. ? in case of a control out endpoint, they clear the stp and po bits in the corresponding select endpoint register. ? reading one byte is obligatory. remark: this command may be invoked by usin g the cmdcode and cmddata registers, or by setting the corresponding bit in epintclr. for ease of use, using the epintclr register is recommended. 12.12.12 set endpoint status (comma nd: 0x40 - 0x55, data: write 1 byte (optional)) the set endpoint status command sets status bits 7:5 and 0 of the endpoint. the command code of set endpoint status is equal to the sum of 0x40 and the physical endpoint number in hex. not all bits can be set for all types of endpoints. table 305. set endpoint status command bit description bit symbol value description reset value 0 st stalled endpoint bit. a stalled control endpoint is automatically unstalled when it receives a setup token, regardless of the content of the packet. if the endpoint should stay in its stalled state, the cpu can stall it again by setting this bit. when a stalled endpoint is unstalled - either by the set endpoint status command or by receiving a setup token - it is also re-initialized. this flushes the buffer: in case of an out buffer it waits for a data 0 pid; in case of an in buffer it writes a data 0 pid. there is no change of the interrupt status of the endpoint. when already unstalled, writing a zero to this bit in itializes the endpoint. when an endpoint is stalled by the set endpoint status command, it is also re-initialized. 0 0 the endpoint is unstalled. 1 the endpoint is stalled. 4:1 - reserved. read value is undefined, only zero should be written. na 5 da disabled endpoint bit. 0 0 the endpoint is enabled. 1 the endpoint is disabled. 6 rf_mo rate feedback mode. 0 0 interrupt endpoint is in the toggle mode. 1 interrupt endpoint is in the rate feedback mode. this means that transfer takes place without data toggle bit. 7 cnd_st conditional stall bit. 0 0 unstalls both control endpoints. 1 stall both control endpoints, unless the stp bit is set in the select endpoint register. it is defined only for control out endpoints.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 365 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.12.13 clear buffer (command: 0xf2 , data: read 1 by te (optional)) when an out packet sent by the host has been received successfully, an internal hardware fifo status buffer_full flag is se t. all subsequent packets will be refused by returning a nak. when the device software has read the data, it should free the buffer by issuing the clear buffer command. this clears the internal buffer_full flag. when the buffer is cleared, new packets will be accepted. when bit 0 of the optional data byte is 1, the previously received packet was over-written by a setup packet. the packet over-written bit is used only in control transfers. according to the usb specification, a setup packet should be accepted irrespective of the buffer status. the software should always check the status of the po bit after reading the setup data. if it is set then it should discard the previously read data, clear the po bit by issuing a select endpoint/clear interrupt command, read the new setup data and again check the status of the po bit. see section 12.14 ? slave mode operation ? for a description of when this command is used. 12.12.14 validate buffer (c ommand: 0xfa, data: none) when the cpu has written data into an in buffer, software should issue a validate buffer command. this tells hardware that the buffer is ready for sending on the usb bus. hardware will send the contents of the buffer when the next in token packet is received. internally, there is a hardware fi fo status flag called buffer_fu ll. this flag is set by the validate buffer command and cleared when the data has been sent on the usb bus and the buffer is empty. a control in buffer cannot be validated when its corresponding out buffer has the packet over-written (po) bit (see the clear buffer register) set or contains a pending setup packet. for the control endpoint the validated buffer will be invalidated when a setup packet is received. see section 12.14 ? slave mode operation ? for a description of when this command is used. table 306. clear buffer command bit description bit symbol value description reset value 0 po packet over-written bit. this bit is only applicable to the control endpoint ep0. 0 0 the previously received packet is intact. 1 the previously received packet was over-written by a later setup packet. 7:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 366 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.13 usb device controller initialization the usb device controlle r initialization includ es the following steps: 1. enable the device controller by setting the pcusb bit of pconp. 2. configure and enable the pll and clock dividers to provide 48 mhz for usbclk and the desired frequency for cclk. for the procedure for determining the pll setting and configuration, see section 3.10.5 ? procedure for determining pll settings ? . 3. enable the device contro ller clocks by setting dev_clk_ en and ahb_clk_en bits in the clkctrl register. poll th e respective clock bits in the clkst register until they are set. 4. select the desired usb port pins usin g the portsel register. the portsel_clk_en bit must be set in clkctrl before accessing portsel and should be cleared after accessing portsel. 5. enable the usb pin functions by writing to the corresponding iocon registers. 6. disable the pull-ups and pull-downs on the v bus pin using the corresponding iocon register by putting the pin in the ?plain-input? mode. see section 7.4.1 ? i/o configuration register contents (iocon) ? . 7. set epin and maxpsize registers for ep0 and ep1, and wait until the ep_rlzed bit in devintst is set so that ep0 and ep1 are realized. 8. enable endpoint interrupts (slave mode): ? clear all endpoint inte rrupts using epintclr. ? clear any device interrupts using devintclr. ? enable slave mode for the desired endpoints by setting the corresponding bits in epinten. ? set the priority of each enabled interrupt using epintpri. ? configure the desired interrupt mode using the sie set mode command. ? enable device interrupts using devinten (normally dev_stat, ep_slow, and possibly ep_fast). 9. configure the dma (dma mode): ? disable dma operation for all endpoints using epdmadis. ? clear any pending dma requests using dmarclr. ? clear all dma interrupts using eotint clr, nddrintclr, and syserrintclr. ? prepare the udca in system memory. ? write the desired address for the udca to udcah. ? enable the desired endpoints for dma operation using epdmaen. ? set eot, ddr, and err bits in dmainten. 10. install usb interrupt handler in the nvic by writing its address to the appropriate vector table location and enabling the usb interrupt in the nvic. 11. set default usb address to 0x0 and dev_en to 1 using the sie set address command. a bus reset will also cause this to happen. 12. set con bit to 1 to ma ke connect active using th e sie set device status command.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 367 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller the configuration of the endpoints varies depending on the software application. by default, all the endpoints are disabled except control endpoints ep0 and ep1. additional endpoints are enabled and configured by software after a set_configuration or set_interface device request is received from the host.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 368 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.14 slave mode operation in slave mode, the cpu transfers data between ram and the endpoint buffer using the register interface. 12.14.1 interrupt generation in slave mode, data packet transfer between ram and an endpoint buffer can be initiated in response to an endpoint interrupt. endpoint interrupts are enabled using the epinten register, and are observable in the epintst register. all non-isochronous out endpoints generate an endpoint interrupt when they receive a packet without an error. all non-isochronous in endpoints generate an interrupt when a packet is successfully transmitted, or when a nak handshake is sent on the bus and the interrupt on nak feature is enabled. for isochronous endpoints, transfer of data is done when the frame interrupt (in devintst) occurs. 12.14.2 data transfer for out endpoints when the software wants to read the data from an endpoint buffer it should set the rd_en bit and program log_endpoint with the desired endpoint number in the ctrl register. the control logic will fetch the packet length to the rxplen register, and set the pkt_rdy bit ( table 271 ). software can now start reading the data from the rxdata register ( ta b l e 2 7 0 ). when the end of packet is reached, the rd_en bit is cleared, and the rxendpkt bit is set in the devst register. software now issues a clear buffer (refer to table 306 ) command. the endpoint is now ready to accept the next packet. for out isochronous endpoints, the next packet will be received irrespective of wh ether the buffer has bee n cleared. any data not read from the buffer before the end of the frame is lost. see section 12.16 ? double buffered endpoint operation ? for more details. if the software clears rd_en before the entire packet is read, reading is terminated, and the data remains in the endpoint?s buffer. wh en rd_en is set again for this endpoint, the data will be read from the beginning. 12.14.3 data transfer for in endpoints when writing data to an endpoint buffer, wr_en ( section 12.10.5.5 ? usb control register ? ) is set and software writes to the number of bytes it is going to send in the packet to the txplen register ( section 12.10.5.4 ). it can then write data continuously in the txdata register. when the number of bytes programmed in txplen have been written to txdata, the wr_en bit is cleared, and the txendpkt bit is set in the devintst register. software issues a validate buffer ( section 12.12.14 ? validate buffer (command: 0xfa, data: none) ? ) command. the endpoint is now ready to send the packet. for in isochronous endpoints, the data in the buffer will be sent only if the buffer is va lidated before the next frame interrupt occurs; otherwise, an empty pa cket will be sent in the next frame. if the software clears wr_en before th e entire packet is wr itten, writing will st art again from the beginning the next time wr_en is set for this endpoint.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 369 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller both rd_en and wr_en can be high at the same time for the same logical endpoint. interleaved read and write operation is possible.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 370 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15 dma operation in dma mode, the dma transfers data between ram and the endpoint buffer. the following sections discuss dma mode operation. background information is given in sections section 12.15.2 ? usb device communication area ? and section 12.15.3 ? triggering the dma engine ? . the fields of the dma descriptor are described in section 12.15.4 ? the dma descriptor ? . the last three sections describe dma operation: section 12.15.5 ? non-isochronous endpoint operation ? , section 12.15.6 ? isochronous endpoint operation ? , and section 12.15.7 ? auto length transfer extraction (atle) mode operation ? . 12.15.1 transfer terminology within this section three types of transfers are mentioned: 1. usb transfers ? transfer of data over th e usb bus. the usb 2.0 specification refers to these simply as transfers. within this se ction they are referred to as usb transfers to distinguish them from dma transfers. a usb transfer is compos ed of transactions. each transaction is composed of packets. 2. dma transfers ? the transfer of data between an endpoint buffer and system memory (ram). 3. packet transfers ? in this section, a packet transfer refers to the transfer of a packet of data between an endpoint buffer and sy stem memory (ram). a dma transfer is composed of one or more packet transfers. 12.15.2 usb device communication area the cpu and dma controller communicate through a common area of memory, called the usb device communication area, or udca . the udca is a 32-word array of dma descriptor pointers (ddps), each of which co rresponds to a physical endpoint. each ddp points to the start address of a dma descriptor, if one is defined for the endpoint. ddps for unrealized endpoints and endpoints disabled for dma operation are ignored and can be set to a null (0x0) value. the start address of the udca is stored in the udcah register. the udca can reside at any 128-byte boundary of ram that is access ible to both the cpu and dma controller. figure 44 illustrates the udca and its relationshi p to the udca head (udcah) register and dma descriptors.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 371 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15.3 triggering the dma engine an endpoint raises a dma request when slave mode is disabled by setting the corresponding bit in the epinten register to 0 ( section 12.10.3.2 ) and an endpoint interrupt occurs (see section 12.10.7.1 ? usb dma request status register ? ). a dma transfer for an endpoint starts when the endpoint is enabled for dma operation in epdmast, the corresponding bit in dmarst is set, and a valid dd is found for the endpoint. all endpoints share a single dma channel to minimize hardware overhead. if more than one dma request is active in dmarst, the endpoint with the lowest physical endpoint number is processed first. in dma mode, the bits corresponding to inte rrupt on nak for bulk out and interrupt out endpoints (inak_bo and inak_io) should be set to 0 using the sie set mode command ( section 12.12.3 ). 12.15.4 the dma descriptor dma transfers are described by a data structure called the dma descriptor (dd). dds are placed in ram. these descriptors can be located anywhere in on-chip ram at word-aligned addresses. dds for non-isochronous endpoin ts are four words long. dds for isochronous endpoints are five words long. the parameters associated with a dma transfer are: ? the start address of the dma buffer ? the length of the dma buffer fig 44. udca head register and dma descriptors udca head register 1 31 ddp-ep2 2 dd-ep2-a null null next_dd_pointer 0 null ddp-ep31 null ddp-ep16 16 null dd-ep2-b next_dd_pointer dd-ep2-c next_dd_pointer dd-ep16-a next_dd_pointer dd-ep16-b next_dd_pointer udca
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 372 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller ? the start address of the next dma descriptor ? control information ? count information (number of bytes transferred) ? status information table 307 lists the dma descriptor fields. [1] write-only in atle mode legend: r - read; w - write; i - initialize 12.15.4.1 next_dd_pointer pointer to the memory location from wher e the next dma descript or will be fetched. table 307. dma descriptor word position access (h/w) access (s/w) bit position description 0 r r/w 31:0 next_dd_pointer 1 r r/w 1:0 dma_mode (00 -normal; 01 - atle) r r/w 2 next_dd_valid (1 - valid; 0 - invalid) - - 3 reserved. read value is undefined, only zero should be written. r r/w 4 isochronous_endpoint (1 - isochronous; 0 - non-isochronous) r r/w 15:5 max_packet_size r/w [1] r/w 31:16 dma_buffer_length this value is specified in bytes fo r non-isochronous endpoints and in number of packets for isochronous endpoints. 2 r/w r/w 31:0 dma_buffer_start_addr 3 r/w r/i 0 dd_retired (to be initialized to 0) w r/i 4:1 dd_status (to be initialized to 0000): 0000 - notserviced 0001 - beingserviced 0010 - normalcompletion 0011 - dataunderrun (short packet) 1000 - dataoverrun 1001 - systemerror w r/i 5 packet_valid (to be initialized to 0) w r/i 6 ls_byte_extracted (atle mode) (to be initialized to 0) w r/i 7 ms_byte_extracted (atle mode) (to be initialized to 0) r w 13:8 message_length_position (atle mode) - - 15:14 reserved. read value is undefined, only zero should be written. r/w r/i 31:16 present_dma_count (to be initialized to 0) 4 r/w r/w 31:0 isochronous_packetsize_memory_address
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 373 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15.4.2 dma_mode specifies the dma mode of operation. two modes have been defined: normal and automatic transfer length extraction (atle) mode. in normal mode, software initializes the dma_buffer_length for out endpoints. in atle mode, the dma_buffer_length is extracted from the incoming data. see section 12.15.7 ? auto length transfer extraction (atle) mode operation ? on page 378 for more details. 12.15.4.3 next_dd_valid this bit indicates whether the software has prepared the next dma descriptor. if set, the dma engine fetches the new descriptor when it is finished with the current one. 12.15.4.4 isochronous_endpoint when set, this bit indicates that the descriptor belongs to an isochronous endpoint. hence 5 words have to be read when fetching it. 12.15.4.5 max_packet_size the maximum packet size of the endpoint. this parameter is used while transferring the data for in endpoints from the memory. it is used for out endpoints to detect the short packet. this is applicable to non-isochronous endpoints only. this field should be set to the same mps value that is assigned for the endpoint using the maxpsize register. 12.15.4.6 dma_buffer_length this indicates the depth of the dma buffer allocated for transferring the data. the dma engine will stop using this desc riptor when this limit is reac hed and will look for the next descriptor. in normal mode operation, software sets this value for both in and out endpoints. in atle mode operation, software sets this value for in endpoints only. for out endpoints, hardware sets this value using the extracted length of the data stream. for isochronous endpoints, dma_buffer_length is specified in numb er of packets, for non-isochronous endpoints in bytes. 12.15.4.7 dma_buffer_start_addr the address where the data is read from or written to. this field is updated each time the dma engine finishes transferring a packet. 12.15.4.8 dd_retired this bit is set by hardware when the dma e ngine finishes the current descriptor. this happens when the end of the buffer is reached, a short packet is transferred (non-isochronous endpoints), or an error condition is detected. 12.15.4.9 dd_status the status of the dma transfer is encoded in this field. the following codes are defined: ? notserviced - no packet has been transferred yet. ? beingserviced - at least one packet is transferred. ? normalcompletion - the dd is retired because the end of the buffer is reached and there were no errors. the dd_retired bit is also set.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 374 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller ? dataunderrun - before reaching the end of th e dma buffer, the usb transfer is terminated because a short packet is re ceived. the dd_retired bit is also set. ? dataoverrun - the end of the dma buffer is reached in the middle of a packet transfer. this is an error situation. the dd_retired bit is set. the present dma count field is equal to the value of dma_buffer_length. the packet must be re-transmitted from the endpoint buffer in another dma transfer. the corresponding epxx_dma_enable bit in epdmast is cleared. ? systemerror - the dma transfer being serviced is terminated because of an error on the ahb bus. the dd_retired bit is not set in this case. the corresponding epxx_dma_enable in epdmast is cleared. since a system error can happen while updating the dd, the dd fields in ram may be unreliable. 12.15.4.10 packet_valid this bit is used for isochronous endpoints. it indicates whether the last packet transferred to the memory is received with errors or not. th is bit is set if the packet is valid, i.e., it was received without errors. see section 12.15.6 ? isochronous endpoint operation ? on page 376 for isochronous endpoint operation. this bit is unnecessary for non-isochronous endpoints because a dma request is generated only for packets withou t errors, and thus packet_valid will always be set when the request is generated. 12.15.4.11 ls_byte_extracted used in atle mode. when set, this bit indicates that the least significant byte (lsb) of the transfer length has been extracted. th e extracted size is reflected in the dma_buffer_length field, bits 23:16. 12.15.4.12 ms_byte_extracted used in atle mode. when set, this bit indica tes that the most significant byte (msb) of the transfer size has been extracted. t he size extracted is reflected in the dma_buffer_length field, bits 31:24. ex traction stops when ls _byte_extracted and ms_byte_extracted bits are set. 12.15.4.13 present_dma_count the number of bytes transferred by the dma engine. the dma engine updates this field after completing each packet transfer. for isochronous endpoints, present_dma_count is the number of packets transferred; for non-isochronous endpoint s, present_dma_count is the number of bytes. 12.15.4.14 message_length_position used in atle mode. this field gives the offset of the message length position embedded in the incoming data packets. this is applicable only for out endpoints. offset 0 indicates that the message length starts from the first byte of the first packet. 12.15.4.15 isochronous_packetsize_memory_address the memory buffer address where the packet size information along with the frame number has to be transferred or fetched. see figure 45 . this is applicable to isochronous endpoints only.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 375 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15.5 non-isochronous endpoint operation 12.15.5.1 setting up dma transfers software prepares the dma descriptors (dds) for those physical endpoints to be enabled for dma transfer. these dds are present in on- chip ram. the start address of the first dd is programmed into the dma description po inter (ddp) location for the corresponding endpoint in the udca. software then sets the epxx_dma_enable bit for this endpoint in the epdmaen register ( section 12.10.7.6 ).the dma_mode bit field in the descriptor is set to ?00? for normal mode operation. all other dd fields are initialized as specified in table 307 . dma operation is not supported for physical en dpoints 0 and 1 (default control endpoints). 12.15.5.2 finding dma descriptor when there is a trigger for a dma transfer for an endpoi nt, the dma engine will first determine whether a new descriptor has to the fetched or not. a new descriptor does not have to be fetched if the last packet transferred was for the same endpoint and the dd is not yet in the retired state. an internal flag called dma_proceed is used to identify this condition (see section 12.15.5.4 ? optimizing descriptor fetch ? on page 375 ). if a new descriptor has to be read, the dma en gine will calculate the location of the ddp for this endpoint and will fetc h the start addr ess of the dd from th is location. a dd start address at location zero is c onsidered invalid. in this case the nddr interr upt is raised. all other word-aligned addresses are considered valid. when the dd is fetched, the dd status word (word 3) is read first and the status of the dd_retired bit is checked. if not set, ddp poin ts to a valid dd. if dd_retired is set, the dma engine will read the control word (word 1) of the dd. if next_dd_valid bit is set, the dma engine w ill fetch the next_dd_poi nter field (word 0) of the dd and load it to the ddp. the new ddp is written to the udca area. the full dd (4 words) will then be fetched from the address in the ddp. the dd will give the details of the dma transfer to be don e. the dma engine will load its hardware resources with the information fetched from the dd (start address, dma count etc.). if next_dd_valid is not set and dd_retired bit is set, the dma engine raises the nddr interrupt for this endpoint and clears the corresponding epxx_dma_enable bit. 12.15.5.3 transferring the data for out endpoints, the current packet is re ad from the ep_ram by the dma engine and transferred to on-chip ram memory locations starting from dma_buffer_start_addr. for in endpoints, the data is fetched from on-c hip ram at dma_buffer_start_addr and written to the ep_ram. the dma_buffer_start_addr an d present_dma_count fields are updated after each packet is transferred. 12.15.5.4 optimizing descriptor fetch a dma transfer normally involves multiple pa cket transfers. hardwa re will not re-fetch a new dd from memory unless the endpoint changes. to indicate an ongoing multi-packet transfer, hardware sets an internal flag called dma_proceed.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 376 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller the dma_proceed flag is cleared after the re quired number of bytes specified in the dma_buffer_length field is transferred. it is al so cleared when the software writes into the epdmadis register. the ability to clear the dma_pr oceed flag allows software to force the dd to be re-fetched for the next packet transfer. writing all ze ros into the epdmadis register clears the dma_proceed flag without disabling dma operation for any endpoint. 12.15.5.5 ending the packet transfer on completing a packet transfer, the dma engine writes back the dd with updated status information to the same memory location from where it was read. the dma_buffer_start_addr, present_dma_count, and the dd_status fields in the dd are updated. a dd can have the following types of completion: normal completion - if the current packet is fully transferred and the present_dma_count field equals the dma_ buffer_length, the dd has completed normally. the dd will be written back to memory with dd_retired set and dd_status set to normalcompletion. the eot interrupt is raised for this endpoint. usb transfer end completion - if the current packet is fully transferred and its size is less than the max_packet_size field, and the end of the dma buffer is still not reached, the usb transfer end completion occurs. t he dd will be written ba ck to the memory with dd_retired set and dd_status set to the dataunderrun completion code. the eot interrupt is raised for this endpoint. error completion - if the current packet is partially transferred i.e. the end of the dma buffer is reached in the middle of the packet transfer, an error situation occurs. the dd is written back with dd_retired set and dd_s tatus set to the dataoverrun status code. the eot interrupt is raised for this endpoint and the corresponding bit in epdmast register is cleared. the packet will be re-sen t from the endpoint buffer to memory when the corresponding epxx_dma_enable bit is set again using the epdmaen register. 12.15.5.6 no_packet dd for an in transfer, if the system does not have any data to send for a while, it can respond to an nddr interrupt by prog ramming a no_packet dd. this is done by setting both the max_packet_size and dma_buffer_length fields in the dd to 0. on processing a no_packet dd, the dma engine clears the dma request bit in dmarst corresponding to the endpoint without transferring a packet. the dd is retired with a status code of normalcompletion. this can be repeated as often as nece ssary. the device will respond to in token packets on the usb bus with a nak until a dd with a data packet is programmed and the dma transfers the packet into the endpoint buffer. 12.15.6 isochronous endpoint operation for isochronous endpoints, the packet size c an vary for each packet. there is one packet per isochronous endpoi nt for each frame. 12.15.6.1 setting up dma transfers software sets the isochronous endpoint bit to 1 in the dd, and programs the initial value of the isochronous_packetsize_memory_address fiel d. all other fields are initialized the same as for non-isochronous endpoints.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 377 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller for isochronous endpoints, the dma_buffer_l ength and present_dma_ count fields are in frames rather than bytes. 12.15.6.2 finding the dma descriptor finding the descriptors is done in the same way as that for a non-isochronous endpoint. a dma request will be placed for dma-enabled isochronous endpoints on every frame interrupt. on processing the request, the dma engine will fetch the descriptor and if isochronous_endpoint is set, will fetch the isochronous_packetsize_memory_address from the fifth word of the dd. 12.15.6.3 transferring the data the data is transferred to or from the memory location dma_buffer_start_addr. after the end of the packet transfer the present_dma_count value is incremented by 1. the isochronous packet size is stored in memory as shown in figure 45 . each word in the packet size memory shown is divided into fields: frame_number (bits 31 to 17), packet_valid (bit 16), and packet_length (bits 15 to 0). the space allocated for the packet size memory for a given dd should be dma_buffer_length words in size ? one word for each packet to transfer. out endpoints at the completion of each frame, the packet size is written to the address location in isochronous_packet_size_memory_address, and isochronous_packet_size_memory_a ddress is incremented by 4. in endpoints only the packet_length field of the isochronous packet size word is used. for each frame, an isochronous data packet of size specified by this field is transferred from the usb device to the host, and isochronous_packet _size_memory_address is incremented by 4 at the end of the packet transf er. if packet_length is zero, an empty packet will be sent by the usb device. 12.15.6.4 dma descriptor completion dds for isochronous endpoints can only end with a status code of normalcompletion since there is no short packet on isochronous endpoints, and the usb transfer continues indefinitely until a systemerror occurs. there is no dataoverrun detection for isochronous endpoints. 12.15.6.5 isochronous out endpoint operation example assume that an isochronous endpoint is programmed for the transfer of 10 frames and that the transfer begins when the frame number is 21. after transferring four frames with packet sizes of 10,15, 8 and 20 bytes without errors, the descriptor and memory map appear as shown in figure 45 . the_total_number_of_bytes_transferred = 0x0a + 0x0f + 0x08 + 0x14 = 0x35. the packet_valid bit (bit 16) of all the words in the packet length memory is set to 1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 378 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15.7 auto length tr ansfer extraction (atle) mode operation some host drivers such as ndis (network driver interface specificatio n) host drivers are capable of concatenating small usb transfers (d elta transfers) to form a single large usb transfer. for out usb transfers, the device hardware has to break up this concatenated transfer back into the original delta transfers and transfer them to separate dma buffers. this is achieved by setting the dma mode to auto transfer length extraction (atle) mode in the dma descriptor. atle mode is supported for bulk endpoints only. out transfers in atle mode fig 45. isochronous out endpoint operation example dma_mode next_dd_valid isochronous_endpoint max_packet_size dma_buffer_length 0 16 31 after 4 packets 15 0x60000010 0x80000035 0x000a0010 0x4 0x0 w1 w2 w3 w4 w0 full empty data memory packet size memory 0x60000000 0x80000000 w1 w2 w3 w4 w0 00 1 0x0 0x000a next_dd_pointer null dma_buffer_start_addr isocronous_packetsize_memory_address dd_retired dd_status packet_valid atle settings present_dma_count 0x0 0 na na 0x0 packet_length frame_ number packet_valid 10 15 8 20 1 1 1 1 21 22 23 24 0 0x1 --
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 379 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller figure 46 shows a typical out usb transfer in at le mode, where the host concatenates two usb transfers of 160 bytes and 100 byte s, respectively. given a maxpacketsize of 64, the device hardware interprets this usb transfer as four packets of 64 bytes and a short packet of 4 bytes. the third and fourth packets are concatenated. note that in normal mode, the usb transfer would be interpreted as packets of 64, 64, 32, and 64 and 36 bytes. it is now the responsibility of the dma engine to separate th ese two usb tran sfers and put them in the memory locations in the dma_buffer_start_addr field of dma descriptor 1 (dd1) and dma descriptor 2 (dd2). hardware reads the two-byte-wide dma_buffer_le ngth at the offset (from the start of the usb transfer) specified by me ssage_length_position from the incoming data packets and writes it in the dma_buffer_length field of the dd. to ensure that both bytes of the dma_buffer_length are extracted in the event they are split between two packets, the flags ls_byte_extracted and ms_byte_extracted are set by hardware after the respective byte is extracted. after the extraction of the ms byte, the dma transfer continues as in the normal mode. the flags ls_byte_extracted and ms_byte_ext racted are set to 0 by software when preparing a new dd. therefore, once a dd is reti red, the transfer leng th is extracted again for the next dd. if dd1 is retired during the transfer of a co ncatenated packet (such as the third packet in figure 46 ), and dd2 is not programmed (next_dd_valid field of dd1 is 0), then dd1 is retired with dd_status set to the dataoverru n status code. this is treated as an error condition and the corresponding epxx_dma_enable bit of epdmast is cleared by hardware. fig 46. data transfer in atle mode dma_buffer_start_addr of dd1 dma_buffer_start_addr of dd2 data to be sent by host driver data in packets as seen on usb data to be stored in ram by dma engine 160 bytes 100 bytes 64 bytes 64 bytes 32 bytes 32 bytes 64 bytes 4 bytes 160 bytes 100 bytes
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 380 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller in atle mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the usb transfer. if the concatenated transfer lengths are such that the usb transfer ends on a maxp acketsize packet boundary, the (ndis) host will send an empty packet to ma rk the end of the usb transfer. in transfers in atle mode for in usb transfers from the device to the ho st, dma_buffer_length is set by the device software as in normal mode. in atle mode, the device concatenates data from multiple dds to form a single usb transfer. if a dd is retired in the middle of a packet (packet size is less than maxpacketsize), the next dd referenced by next_dd_pointer is fetched, and the remaining bytes to form a packet of maxpacketsize are transferred from the next dd?s buffer. if the next dd is not programmed (i.e. next_dd_valid field in dd is 0), and the dma buffer length for the current dd has completed before the maxpacketsize packet boundary, then the available bytes from current dd are sent as a short packet on usb, which marks the end of the usb transfer for the host. if the last buffer length completes on a maxpacketsize packet boundary, the device software must program the next dd with dma_buffer_length field 0, so that an empty packet is sent by the device to mark th e end of the usb transfer for the host. 12.15.7.1 setting up the dma transfer for out endpoints, the host hardware needs to set the field message_length_position in the dd. this indicates the star t location of the message le ngth in the incoming data packets. also the device software has to se t the dma_buffer_length field to 0 for out endpoints because this field is updated by the device hardware after the extraction of the buffer length. for in endpoints, descriptors are set in th e same way as in normal mode operation. since a single packet can be split between two dds, software should always keep two dds ready, except for the last dma transfer which ends with a short or empty packet. 12.15.7.2 finding the dma descriptor dma descriptors are found in the same way as the normal mode operation. 12.15.7.3 transferring the data out endpoints if the ls_byte_extracted or ms_byte_extracted bit in the status field is not set, the hardware will extract the tr ansfer length fr om the data stream and program dma_buffer_length. once the extraction is complete both the ls_byte_extracted and ms_byte_extracted bits will be set. in endpoints the dma transfer proceeds as in normal mode and continues until the number of bytes transferred equals the dma_buffer_length.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 381 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.15.7.4 ending the packet transfer the dma engine proceeds with the transfer unt il the number of bytes specified in the field dma_buffer_length is transfer red to or from on-chip ram. then the eot in terrupt will be generated. if this happens in the middle of the packet, the linked dd will get loaded and the remaining part of the packet gets transf erred to or from the address pointed by the new dd. out endpoints if the linked dd is not valid and the packet is partially transferred to memory, the dd ends with dataoverrun status code set, and the dma will be disabled for this endpoint. otherwise dd_status will be updated with the normalcompleti on status code. in endpoints if the linked dd is not valid and the packet is partially transferred to usb, the dd ends with a status code of normalcompletion in th e dd_status field. this situation corresponds to the end of the usb transfer, and the pack et will be sent as a short packet. also, when the linked dd is valid and buffer length is 0, an empty packet will be sent to indicate the end of the usb transfer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 382 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller 12.16 double buffered endpoint operation the bulk and isochronous endpoints of the us b device controller are double buffered to increase data throughput. when a double-buffered endpoint is realized, enough space for both endpoint buffers is automatically allocate d in the ep_ram. see section 12.10.4.1 . for the following discussion, the endpoint buffer currently accessible to the cpu or dma engine for reading or writing is said to be the active buffer. 12.16.1 bulk endpoints for bulk endpoints, the active endpoint buffer is switched by the sie clear buffer or validate buffer commands. the following example illustrate s how double buffering works for a bulk out endpoint in slave mode: assume that both buffer 1 (b_1) and buffer 2 (b_2) are empty, and that the active buffer is b_1. 1. the host sends a data packet to the endpoint. the device hardware puts the packet into b_1, and generates an endpoint interrupt. 2. software clears the endpoint interrupt and begins reading the packet data from b_1. while b_1 is still bei ng read, the host sends a second packet, which device hardware places in b_2, and generates an endpoint interrupt. 3. software is still reading from b_1 when the host attempts to send a third packet. since both b_1 and b_2 are full, the device hardware responds with a nak. 4. software finishes reading the first pack et from b_1 and sends a sie clear buffer command to free b_1 to receive another packet. b_2 becomes the active buffer. 5. software sends the sie select endpoi nt command to read the select endpoint register and test the fe bit. software finds that the active buffer (b_2) has data (fe=1). software clears the endpoint interrupt and begins reading the contents of b_2. 6. the host re-sends the third packet which de vice hardware places in b_1. an endpoint interrupt is generated. 7. software finishes reading the second packet from b_2 and sends a sie clear buffer command to free b_2 to receive another packet. b_1 becomes the active buffer. software waits for the next endpoint interrupt to occur (it already has been generated back in step 6). 8. software responds to the endpoint interrupt by clearing it and begins reading the third packet from b_1. 9. software finishes reading the third pack et from b_1 and sends a sie clear buffer command to free b_1 to receive another packet. b_2 becomes the active buffer. 10. software tests the fe bit and finds that the active buffer (b_2) is empty (fe=0). 11. both b_1 and b_2 are empty. software waits for the next endpoint interrupt to occur. the active buffer is now b_2. the next data packet sent by the ho st will be placed in b_2.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 383 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller the following example illustrate s how double buffering works for a bulk in endpoint in slave mode: assume that both buffer 1 (b_1) and buffer 2 (b_2) are empty and that the active buffer is b_1. the interrupt on nak feature is enabled. 1. the host requests a data packet by sending an in token packet. the device responds with a nak and generates an endpoint interrupt. 2. software clears the endpoint interrupt. the device has three packets to send. software fills b_1 with the first packet and sends a sie validat e buffer command. the active buffer is switched to b_2. 3. software sends the sie select endpoi nt command to read the select endpoint register and test the fe bit. it finds that b_2 is empty (fe=0) and fills b_2 with the second packet. software sends a sie validate buffer command, and the active buffer is switched to b_1. 4. software waits for the en dpoint interrupt to occur. 5. the device successfully sends the packet in b_1 and clears the buffer. an endpoint interrupt occurs. 6. software clears the endpoint interrupt. so ftware fills b_1 with the third packet and validates it using the sie validate buffer co mmand. the active buffer is switched to b_2. 7. the device successfully sends the second packet from b_2 and generates an endpoint interrupt. 8. software has no more packets to se nd, so it simply clears the interrupt. 9. the device successfully sends the third pa cket from b_1 and generates an endpoint interrupt. 10. software has no more packets to send, so it simply clears the interrupt. 11. both b_1 and b_2 are empty, and the active buffer is b_2. the next packet written by software will go into b_2. in dma mode, switching of the active buffer is handled automatically in hardware. for bulk in endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the dmarset register. 12.16.2 isochronous endpoints for isochronous endpoints, the active data buffer is switched by hardware when the frame interrupt occurs. the sie clear buffer and validate buffer commands do not cause the active buffer to be switched. double buffering allows the software to make full use of the frame interval writing or reading a packet to or from the active buffer, while the packet in the other buffer is being sent or received on the bus. for an out isochronous endpoint, any data not read from the active buffer before the end of the frame is lost when it switches.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 384 of 942 nxp semiconductors UM10562 chapter 12: lpc408x/407x usb device controller for an in isochronous endpoint, if the active buffer is not validated before the end of the frame, an empty packet is sent on the bus when the active buffer is switched, and its contents will be overwritten when it becomes active again.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 385 of 942 13.1 how to read this chapter this chapter describes the usb host controller which is present on some lpc408x/407x devices (see section 1.4 for details). on these devices, the usb controller can be configured for device, host, or otg operation. 13.2 basic configuration the usb controller is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcusb. remark: on reset, the usb block is disabled (pcusb = 0). 2. clock: the usb block can be used with the alt pll (pll1) to obtain the usb clock or with the main pll (pll0). see section 3.10 . 3. pins: select usb pins and their mo des in the relevant iocon registers ( section 7.4.1 ). 4. wake-up: activity on the usb bus port can wake up the microcontroller from power-down mode, see section 3.12.8 . 5. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. initialization: see section 14.11 . UM10562 chapter 13: lpc408x/407x usb host controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 386 of 942 nxp semiconductors UM10562 chapter 13: lpc408x/407x usb host controller 13.3 introduction this section describes the host portion of the usb 2.0 otg dual role core which integrates the host controller (ohci compliant), device controller, and i 2 c interface. the i 2 c interface controls the external otg atx. the usb is a 4 wire bus that supports comm unication between a host and a number (127 max.) of peripherals. the host controller alloca tes the usb bandwidth to attached devices through a token based protocol. the bus supports hot plugging, un-plugging and dynamic configuration of the devices. all transacti ons are initiated by the host controller. the host controller enables data exchange with various usb devices attached to the bus. it consists of register interface, serial in terface engine and dma controller. the register interface complies to th e ohci specification. 13.3.1 features ? ohci compliant. ? openhci specifies the operation and interf ace of the usb host controller and sw driver ? usboperational: process lists and generate sof tokens. ? usbreset: forces reset signaling on the bus, sof disabled. ? usbsuspend: monitor usb for wake-up activity. ? usbresume: forces resume signaling on the bus. ? the host controller has four usb st ates visible to the sw driver. ? hcca register points to interrupt and isochronous descriptors list. ? controlheaded and bulkheaded registers poin t to control and bulk descriptors list. table 308. usb (ohci) related acronyms and abbreviations used in this chapter acronym/abbreviation description ahb advanced high-performance bus atx analog transceiver dma direct memory access fs full speed ls low speed ohci open host controller interface usb universal serial bus
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 387 of 942 nxp semiconductors UM10562 chapter 13: lpc408x/407x usb host controller 13.3.2 architecture the architecture of the usb host controller is shown below in figure 47 . fig 47. usb host controller block diagram register interface bus master interface usb at x usb at x dma interface (ahb master) register interface (ahb slave) ahb bus host controller at x control logic/ port mux port 1 port 2 u2 port u1 port usb host block
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 388 of 942 nxp semiconductors UM10562 chapter 13: lpc408x/407x usb host controller 13.4 interfaces the otg controller has two usb ports indicated by suffixes 1 and 2 in the usb pin names and referred to as usb port 1 (u1) and usb port 2 (u2) in the following text. 13.4.1 pin description table 309. usb otg port pins pin name direction description pin category v bus iv bus status input. when this function is not enabled via its corresponding iocon register, it is driven high internally. usb connector port u1 usb_d+1 i/o positive differential data usb connector usb_d ? 1 i/o negative differential data usb connector usb_connect1 o softconnect control signal control usb_up_led1 o goodlink led control signal control usb_int1 i otg atx interrupt external otg transceiver usb_scl1 i/o i 2 c serial clock external otg transceiver usb_sda1 i/o i 2 c serial data external otg transceiver usb_tx_e1 o transmit enable external otg transceiver usb_tx_dp1 o d+ transmit data external otg transceiver usb_tx_dm1 o d ? transmit data external otg transceiver usb_rcv1 i differential receive data external otg transceiver usb_rx_dp1 i d+ receive data external otg transceiver usb_rx_dm1 i d ? receive data external otg transceiver usb_ls1 o low speed status (applies to host functionality only) external otg transceiver usb_sspnd1 o bus suspend status external otg transceiver usb_ppwr1 o port power enable host power switch usb_pwrd1 i port power status host power switch usb_ovrcr1 i over-current status host power switch usb_hsten1 o host enabled status port u2 usb_d+2 i/o positive differential data usb connector usb_d ? 2 i/o negative differential data usb connector usb_connect2 o softconnect control signal control usb_up_led2 o goodlink led control signal control usb_ppwr2 o port power enable host power switch usb_pwrd2 i port power status host power switch usb_ovrcr2 i over-current status host power switch usb_hsten2 o host enabled status control
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 389 of 942 nxp semiconductors UM10562 chapter 13: lpc408x/407x usb host controller 13.4.1.1 usb host usage note both ports can be configured as usb hosts. for details on how to connect the usb ports, see the usb otg chapter, section 14.7 . the usb device/host/otg controller is disabled after reset and must be enabled by writing a 1 to the pcusb bit in the pconp register, see section 3.3.2.2 . 13.4.2 software interface the software interface of the usb host block consists of a register view and the format definitions for the endpoint descriptors. fo r details on these two aspects see the ohci specification. the register map is shown in the next subsection. 13.4.2.1 register map the following registers are located in the ahb clock ?cclk? domain. they can be accessed directly by the processor. all registers are 32 bits wide and aligned in the word address boundaries. table 310. usb host register address definitions name function address r/w [1] reset value hcrevision bcd representation of the version of the hci specification that is implemented by the host controller. 0x2008 c000 r 0x10 hccontrol defines the operating modes of the hc. 0x2008 c004 r/w 0 hccommandstatus this register is used to receive the commands from the host controller driver (hcd). it also indicates the status of the hc. 0x2008 c008 r/w 0 hcinterruptstatus indicates the status on various events that cause hardware interrupts by setting the appropriate bits. 0x2008 c00c r/w 0 hcinterruptenable controls the bits in the hcinterruptstatus register and indicates which events will generate a hardware interrupt. 0x2008 c010 r/w 0 hcinterruptdisable the bits in this register are used to disable corresponding bits in the hcinterruptstatus register and in turn disable that event leading to hard ware interrupt. 0x2008 c014 r/w 0 hchcca contains the physical address of the host controller communication area. 0x2008 c018 r/w 0 hcperiodcurrented contains the physical ad dress of the current isochronous or interrupt endpoint descriptor. 0x2008 c01c r 0 hccontrolheaded contains the physical address of the first endpoint descriptor of the control list. 0x2008 c020 r/w 0 hccontrolcurrented contains the physical address of the current endpoint descriptor of the control list 0x2008 c024 r/w 0 hcbulkheaded contains the physical address of the first endpoint descriptor of the bulk list. 0x2008 c028 r/w 0 hcbulkcurrented contains the physical address of the current endpoint descriptor of the bulk list. 0x2008 c02c r/w 0 hcdonehead contains the physical address of the last transfer descriptor added to the ?done? queue. 0x2008 c030 r 0 hcfminterval defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun. 0x2008 c034 r/w 0x2edf hcfmremaining a 14-bit counter showing the bit time remaining in the current frame. 0x2008 c038 r 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 390 of 942 nxp semiconductors UM10562 chapter 13: lpc408x/407x usb host controller [1] the r/w column lists the accessibility of the register: a) registers marked ?r? for access will return their current value when read. b) registers marked ?r/w? allow both read and write. 13.4.2.2 usb host register definitions refer to the ohci specification document on the compaq website for register definitions. hcfmnumber contains a 16-bit counter and provides the timing reference among events happening in the hc and the hcd. 0x2008 c03c r 0 hcperiodicstart contains a programmable 14-bit value which determines the earliest time hc should start processing a periodic list. 0x2008 c040 r/w 0 hclsthreshold contains 11-bit value which is used by the hc to determine whether to commit to transfer a maximum of 8-byte ls packet before eof. 0x2008 c044 r/w 0x628h hcrhdescriptora first of the two registers which describes the characteristics of the root hub. 0x2008 c048 r/w 0xff000902 hcrhdescriptorb second of the two regist ers which describes the characteristics of the root hub. 0x2008 c04c r/w 0x60000h hcrhstatus this register is divided into two parts. the lower d-word represents the hub status field and the upper word represents the hub status change field. 0x2008 c050 r/w 0 hcrhportstatus[1] controls and reports the port events on a per-port basis. 0x2008 c054 r/w 0 hcrhportstatus[2] controls and reports the port events on a per port basis. 0x2008 c058 r/w 0 module_id/ ver_rev_id ip number, where yy (0x00) is unique version number and zz (0x00) is a unique revision number. 0x2008 c0fc r 0x3505yyzz table 310. usb host register address definitions ?continued name function address r/w [1] reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 391 of 942 14.1 how to read this chapter this chapter describes the usb otg controlle r which is present on some lpc408x/407x devices (see section 1.4 for details). on these devices, the usb controller can be configured for device, host, or otg operation. 14.2 basic configuration the usb controller is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcusb. remark: on reset, the usb block is disabled (pcusb = 0). 2. clock: the usb clock can generated using the alt pll (pll1) or with the main pll (pll0). see section 3.10 . 3. pins: select usb pins and their mo des in the relevant iocon registers ( section 7.4.1 ). 4. wake-up: activity on the usb bus port can wake up the microcontroller from power-down mode (see section 14.10.2 and section 3.12.8 ). 5. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. the usb global interrupt status is visible in the usbintstat register ( ta b l e 3 7 ). 7. initialization: see section 14.11 . 14.3 introduction this chapter describes the otg and i 2 c portions of the usb 2.0 otg dual role device controller which integrates the (ohci) host controller, device controller, and i 2 c. the i 2 c interface that is part of the usb block is in tended to control an external otg transceiver, and is not the same as the i 2 c peripherals described in section 22.1 . usb otg (on-the-go) is a supplement to th e usb 2.0 specification that augments the capability of existing mobile devices and usb peripherals by adding host fu nctionality for connection to usb peripherals. the specification and more information on usb otg can be found on the usb implementers forum web site. 14.4 features ? fully compliant with on-th e-go supplement to the usb 2.0 specificat ion, revision 1.0a . ? hardware support for host negotiation protocol (hnp). ? includes a programmable timer required for hnp and srp. ? supports any otg transceiver compliant with the otg transceiver specification (cea-2011), rev. 1.0 . UM10562 chapter 14: lpc408x/407x usb otg controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 392 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.5 architecture the architecture of the usb otg controller is shown below in the block diagram. the host, device, otg, and i 2 c controllers can be programmed through the register interface. the otg controller enables dynamic switching between host and device roles through the hnp protocol. one port may be conn ected to an external otg transceiver to support an otg connection. the communication between the register interface and an external otg transceiver is handled through an i 2 c interface and through the external otg transceiver interrupt signal. for usb connections that use the device or host controller only (not otg), the ports use an embedded usb analog transceiver (atx). 14.6 modes of operation the otg controller is capable of operating in the following modes: ? one dual-role otg port and optionally another host port (see figure 49 and figure 50 ) ? two host ports (see figure 51 ) ? one host port and one device port (see figure 52 ) fig 48. usb otg controller block diagram register interface bus master interface usb at x usb at x dma interface (ahb master) register interface (ahb slave) ahb bus i2c controller device controller host controller ep_ram otg controller at x control logic/ port mux port 1 port 1 port 2 u2 port u1 port otg transceiver usb otg block
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 393 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.7 pin configuration the otg controller has two usb ports indicated by suffixes 1 and 2 in the usb pin names and referred to as usb port 1 (u1) and usb port 2 (u2) in the following text. table 311. usb otg port 1 pins pin name direction description pin category v bus iv bus status input. when this function is not enabled via its corresponding iocon register, it is driven high internally. usb connector port u1 usb_d+1 i/o positive differential data usb connector usb_d ? 1 i/o negative differential data usb connector usb_connect1 o softconnect control signal control usb_up_led1 o goodlink led control signal control usb_int1 i otg atx interrupt external otg transceiver usb_scl1 i/o i 2 c serial clock external otg transceiver usb_sda1 i/o i 2 c serial data external otg transceiver usb_tx_e1 o transmit enable external otg transceiver usb_tx_dp1 o d+ transmit data external otg transceiver usb_tx_dm1 o d ? transmit data external otg transceiver usb_rcv1 i differential receive data external otg transceiver usb_rx_dp1 i d+ receive data external otg transceiver usb_rx_dm1 i d ? receive data external otg transceiver usb_ls1 o low speed status (applies to host functionality only) external otg transceiver usb_sspnd1 o bus suspend status external otg transceiver usb_ppwr1 o port power enable host power switch usb_pwrd1 i port power status host power switch usb_ovrcr1 i over-current status host power switch usb_hsten1 o host enabled status port u2 usb_d+2 i/o positive differential data usb connector usb_d ? 2 i/o negative differential data usb connector usb_connect2 o softconnect control signal control usb_up_led2 o goodlink led control signal control usb_ppwr2 o port power enable host power switch usb_pwrd2 i port power status host power switch usb_ovrcr2 i over-current status host power switch usb_hsten2 o host enabled status control
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 394 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.7.1 using port u1 for otg operation the following figures show different ways to realize connections to a usb device using ports u1 and u2. the example described he re uses an isp1302 (st-ericsson) for the external otg transceiver and the usb host power switch lm3526-l (national semiconductors). there are two ways to connect the otg transceiver: 1. use the internal usb transceiver for usb signalling and us e the external otg transceiver for otg func tionality only (see figure 49 ). this option uses the internal transceiver in vp/vm mode. 2. use the external otg transceiver in vp/vm mode for otg functionality and usb signalling (see figure 50 ). in both cases port u2 is connected as a host. solution one uses fewer pins. fig 49. usb otg port configuration: port u1 otg dual-role device, port u2 host usb_up_led1 usb_d+1 usb_d-1 usb_pwrd2 usb_sda1 usb_scl1 rstout 15 k? 15 k? microcontroller usb-a connector mini-ab connector 33 ? 33 ? 33 ? 33 ? v dd v dd v dd usb_up_led2 v dd usb_ovrcr2 lm3526-l ena in 5 v outa flaga v dd d+ d- v bus usb_ppwr2 usb_d+2 usb_d-2 002aac708 r7 r4 r5 r6 r1 r2 r3 r4 r8 usb_int1 reset_n adr/psw speed suspend oe_n/int_n scl sda int_n vbus id dp dm isp1302 v ss v ss
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 395 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller fig 50. usb otg port configuration: vp_vm mode usb_tx_dp1 usb_tx_dm1 usb_rcv1 usb_rx_dp1 usb_rx_dm1 usb_scl1 usb_sda1 speed adr/psw sda scl reset_n int_n vp vm suspend oe_n/int_n se0_vm dat_vp rcv vbus id dp dm microcontroller isp1302 usb mini-ab connector 33 ? 33 ? 002aac711 usb_tx_e1 rstout v dd v dd usb_int1 usb_up_led1 v dd v ss
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 396 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.7.2 using both ports u1 and u2 for host operation both ports u1 and u2 are connected as hosts using an embedded usb transceiver. there is no otg functionality on the port. fig 51. usb host port configuration: port u1 and u2 as hosts usb_up_led1 usb_d+1 usb_d-1 usb_pwrd1 usb_pwrd2 15 k? 15 k? 15 k? 15 k? microcontroller usb-a connector usb-a connector 33 ? 33 ? 33 ? 33 ? 002aac709 v dd usb_up_led2 v dd usb_ovrcr1 usb_ovrcr2 usb_ppwr1 lm3526-l ena enb in 5 v flaga outa outb flagb v dd v dd d+ d- d+ d- v bus v bus usb_ppwr2 usb_d+2 usb_d-2 v ss v ss
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 397 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.7.3 using u1 for host operation and u2 for device operation port u2 is connected as device, and port u1 is connected as host. both ports use embedded usb transceivers. there is no otg functionality on either usb port. fig 52. usb device port configuration: port u1 host and port u2 device usb_up_led1 usb_d+1 usb_d-1 usb_pwrd1 15 k? 15 k? microcontroller usb-a connector usb-b connector 33 ? 33 ? 33 ? 33 ? 002aac710 v dd usb_up_led2 usb_connect2 v dd v dd usb_ovrcr1 usb_ppwr1 lm3526-l ena in 5 v flaga outa v dd d+ d- d+ d- v bus usb_d+2 usb_d-2 v bus v bus v ss v ss
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 398 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8 register description the otg and i 2 c registers are summarized in the following table. the device and host registers are explained in table 254 and ta b l e 3 1 0 in the usb device controller and usb host (ohci) controlle r chapters. all register s are 32 bits wide and aligned to word address boundaries. the usb interrupt status is captured in th e usbintstat register in the syscon block. bits 0 and 1 of the stctrl register are used to control the routing of the usb pins to ports 1 and 2 in device-only applications (see section 12.10.1 ). 14.8.1 otg interrupt status register bits in this register are set by hardware w hen the interrupt event occurs during the hnp handoff sequence. see section 14.9 for more information on when these bits are set. table 312. register overview: usb otg controller (base address 0x2008 c000) name access address offset description reset value table otg registers intst ro 0x100 otg interrupt status 0 313 inten r/w 0x104 otg interrupt enable 0 313 intset wo 0x108 otg interrupt set na 313 intclr wo 0x10c otg interrupt clear na 313 portsel r/w 0x110 otg status and control and usb port select 0 317 tmr r/w 0x114 otg timer 0xffff 318 i 2 c registers i2c_rx ro 0x300 i 2 c receive na 319 i2c_tx wo 0x300 i 2 c transmit na 320 i2c_sts ro 0x304 i 2 c status 0x0a00 321 i2c_ctl r/w 0x308 i 2 c control 0 322 i2c_clkhi r/w 0x30c i 2 c clock high 0xb9 323 i2c_clklo r/w 0x310 i 2 c clock low 0xb9 324 clock control registers clkctrl r/w 0xff4 otg clock controller 0 325 clkst ro 0xff8 otg clock status 0 326 table 313. otg interrupt status register (intst - address 0x2008 c100) bit description bit symbol description reset value 0 tmr timer time-out. 0 1 remove_pu remove pull-up. this bit is set by hardware to indicate that software needs to disable the d+ pull-up resistor. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 399 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.2 otg interrupt enable register writing a one to a bit in this register enables the corresponding bit in otgintst to generate an interrupt on one of the in terrupt lines. the interrupt is routed to the usb_otg_int interrupt line in the usbintst register. the bit allocation and reset value of otginten is the same as otgintst. 14.8.3 otg interrupt set register writing a one to a bit in this register will set the corresponding bit in the otgintst register. writing a zero has no effect. the bit allocation of otgintset is the same as in otgintst. 14.8.4 otg interrupt clear register writing a one to a bit in this register will clear the corresponding bi t in the otgintst register. writing a zero has no effect. the bit allocation of otgintclr is the same as in otgintst. 2 hnp_failure hnp failed. this bit is set by hardware to indicate that the hnp switching has failed. 0 3 hnp_success hnp succeeded. this bit is set by hardware to indicate that the hnp switching has succeeded. 0 31:4 - reserved. read value is undefined, only zero should be written. na table 313. otg interrupt status register (intst - address 0x2008 c100) bit description bit symbol description reset value table 314. otg interrupt enable register (inten - address 0x2008 c104) bit description bit symbol description reset value 0 tmr_en 1 = enable the corresponding bit in the intst register. 0 1 remove_pu_en 1 = enable the corresponding bit in the intst register. 0 2 hnp_failure_en 1 = enable the corresponding bit in the intst register. 0 3 hnp_succes_en 1 = enable the corresponding bit in the intst register. 0 31:4 - reserved. read value is undefined, only zero should be written. na table 315. otg interrupt enable register (intset - address 0x2008 c108) bit description bit symbol description reset value 0 tmr_set 0 = no effect. 1 = set the corresponding bit in the intst register. 0 1 remove_pu_set 0 = no effect. 1 = set the corresponding bit in the intst register. 0 2 hnp_failure_set 0 = no effect. 1 = set the corresponding bit in the intst register. 0 3 hnp_succes_set 0 = no effect. 1 = set the corresponding bit in the intst register. 0 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 400 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller table 316. otg interrupt enable register (intclr - address 0x2008 c10c) bit description bit symbol description reset value 0 tmr_clr 0 = no effect. 1 = clear the corresponding bit in the intst register. 0 1 remove_pu_clr 0 = no effect. 1 = clear the corresponding bit in the intst register. 0 2 hnp_failure_clr 0 = no effect. 1 = clear the corresponding bit in the intst register. 0 3 hnp_succes_clr 0 = no effect. 1 = clear the corresponding bit in the intst register. 0 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 401 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.5 otg status a nd control register the otgstctrl register allows enabling hard ware tracking during the hnp hand over sequence, controlling th e otg timer, monitoring the timer count, and controlling the functions mapped to port u1 and u2. time critical events during the switching se quence are controlled by the otg timer. the timer can operate in two modes: 1. monoshot mode: an interrupt is gener ated at the end of timeout_cnt (see section 14.8.6 ? otg timer register ? ), the tmr bit is set in otgintst, and the timer will be disabled. 2. free running mode: an interrupt is ge nerated at the end of timeout_cnt (see section 14.8.6 ? otg timer register ? ), the tmr bit is set, and the timer value is reloaded into the counter. the timer is not disabled in this mode. table 317. otg status control register (stctrl - address 0x2008 c110) bit description bit symbol description reset value 1:0 port_func controls connection of usb functions (see figure 53 ). bit 0 is set or cleared by hardware when b_hnp_track or a_hnp_track is set and hnp succeeds. see section 14.9 . 00: u1 = device (otg), u2 = host 01: u1 = host (otg), u2 = host 10: reserved 11: u1 = host, u2 = device - 3:2 tmr_scale timer scale selection. this field determines the duration of each timer count. 00: 10 ? s (100 khz) 01: 100 ? s (10 khz) 10: 1000 ? s (1 khz) 11: reserved 0 4 tmr_mode timer mode selection. 0: monoshot 1: free running 0 5 tmr_en timer enable. when set, tmr_cnt increments. when cleared, tmr_cnt is reset to 0. 0 6 tmr_rst timer reset. writing one to this bit resets tmr_cnt to 0. this provides a single bit control for the software to restart the timer when the timer is enabled. 0 7 - reserved. read value is undefined, only zero should be written. na 8 b_hnp_track enable hnp tracking for b-device (peripheral), see section 14.9 . hardware clears this bit when hnp_success or hnp_failure is set. 0 9 a_hnp_track enable hnp tracking for a-device (host), see section 14.9 . hardware clears this bit when hnp_success or hnp_failure is set. 0 10 pu_removed when the b-device changes its role from peripheral to host, software sets this bit when it removes the d+ pull-up, see section 14.9 . hardware clears this bit when hnp_success or hnp_failure is set. 0 15:11 - reserved. read value is undefined, only zero should be written. na 31:16 tmr_cnt current timer count value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 402 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.6 otg timer register 14.8.7 i 2 c receive register this register is the top byte of the receive fifo. the receive fifo is 4 bytes deep. the rx fifo is flushed by a hard reset or by a soft reset (i2c_ctl bit 7). reading an empty fifo gives unpredictable data results. fig 53. port selection for port_func bit 0 = 0 and port_func bit 1 = 0 device controller host controller otgstctrl port_func[1] = 0 port_func[0] = 0 u1 u2 port2 port1 port1 table 318. otg timer register (tmr - address 0x2008 c114) bit description bit symbol description reset value 15:0 timeout_cnt the tmr interrupt is set when tmr_cnt reaches this value. 0xffff 31:16 - reserved. read value is undefined, only zero should be written. na table 319. i 2 c receive register (i2c_rx - address 0x2008 c300) bit description bit symbol description reset value 7:0 rx data receive data. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 403 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.8 i 2 c transmit register this register is the top byte of the transm it fifo. the transmit fifo is 4 bytes deep. the tx fifo is flushed by a hard reset, soft rese t (i2c_ctl bit 7) or if an arbitration failure occurs (i2c_sts bit 3). data writes to a full fifo are ignored. i2c_tx must be written for both write and read operations to transfer each byte. bits [7:0] are ignored for master-receive operations. t he master-receiver must write a dummy byte to the tx fifo for each byte it expects to receive in the rx fifo. when the stop bit is set or the start bit is set to cause a restart condition on a byte written to the tx fifo (master-receiver), then the byte read from the slave is not acknowledged. that is, the last byte of a master-receive operation is not acknowledged. 14.8.9 i 2 c status register the i2c_sts register provides status informat ion on the tx and rx blocks as well as the current state of the external buses. individual bits are enabled as interrupts by the i2c_ctl register and routed to the i2c_usb_int bit in usbintst. table 320. i 2 c transmit register (i2c_tx - address 0x2008 c300) bit description bit symbol description reset value 7:0 tx data transmit data. - 8 start when 1, issue a start condition before transmitting this byte. - 9 stop when 1, issue a stop condition after transmitting this byte. - 31:10 - reserved. read value is undefined, only zero should be written. - table 321. i 2 c status register (i2c_sts - address 0x2008 c304) bit description bit symbol value description reset value 0 tdi transaction done interrupt. this flag is set if a transaction completes successfully. it is cleared by writing a one to bit 0 of the status register. it is unaffected by slave transactions. 0 0 transaction has not completed. 1 transaction completed. 1 afi arbitration failure interrupt. when transmitting, if the sda is low when sdaout is high, then this i 2 c has lost the arbitration to another device on the bus. the arbitration failure bit is set when this happens. it is cleared by writing a one to bit 1 of the status register. 0 0 no arbitration failure on last transmission. 1 arbitration failure occurred on last transmission. 2 nai no acknowledge interrupt. after every byte of data is sent, the transmitter expects an acknowledge from the receiver. this bit is set if the acknowledge is not received. it is cleared when a byte is written to the master tx fifo. 0 0 last transmission received an acknowledge. 1 last transmission did not receive an acknowledge.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 404 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 3 drmi master data request interrupt. once a transmission is started, the transmitter must have data to transmit as long as it isn?t followed by a stop condition or it will hold scl low until more data is available. the master data req uest bit is set when the master transmitter is data-starved. if the master tx fifo is empty and the last byte did not have a stop condition flag, then scl is held low until the cp u writes another byte to transmit. this bit is cleared when a byte is written to the master tx fifo. 0 0 master transmitter does not need data. 1 master transmitter needs data. 4 drsi slave data request interrupt. once a transmission is started, the transmitter must have data to transmit as long as it isn?t followed by a stop condition or it will hold scl low until more data is available. the slave data requ est bit is set when the slave transmitter is data-starved. if the slave tx fifo is empty and the last byte transmitted was acknowledged, then scl is held low until the cp u writes another byte to transmit. this bit is cleared when a byte is written to the slave tx fifo. 0 0 slave transmitter does not need data. 1 slave transmitter needs data. 5 active indicates whether the bus is busy. this bi t is set when a start condition has been seen. it is cleared when a stop condition is seen.. 0 6 scl the current value of the scl signal. - 7 sda the current value of the sda signal. - 8 rff receive fifo full (rff). this bit is set when the rx fifo is full and cannot accept any more data. it is cleared when the rx fifo is not full. if a byte arrives when the receive fifo is full, the scl is held low until the cp u reads the rx fifo and makes room for it. 0 0 rx fifo is not full 1 rx fifo is full 9 rfe receive fifo empty. rfe is set when the rx fifo is empty and is cleared when the rx fifo contains valid data. 1 0 rx fifo contains data. 1 rx fifo is empty 10 tff transmit fifo full. tff is set when the tx fifo is full and is cleared when the tx fifo is not full. 0 0 tx fifo is not full. 1 tx fifo is full 11 tfe transmit fifo empty. tfe is set when the tx fifo is empty and is cleared when the tx fifo contains valid data. 1 0 tx fifo contains valid data. 1 tx fifo is empty 31:12 - reserved. read value is undefined, only zero should be written. na table 321. i 2 c status register (i2c_sts - address 0x2008 c304) bit description bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 405 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.10 i 2 c control register the i2c_ctl register is used to enable interrupts and reset the i 2 c state machine. enabled interrupts cause the usb_i2c_int interrupt output line to be asserted when set. table 322. i 2 c control register (i2c_ctl - address 0x2008 c308) bit description bit symbol value description reset value 0 tdie transmit done interrupt enable. this enables the tdi interrupt signalling that this i 2 c issued a stop condition. 0 0 disable the tdi interrupt. 1 enable the tdi interrupt. 1 afie transmitter arbitration failure interrupt e nable. this enables the afi interrupt which is asserted during transmission when trying to set sda high, but the bus is driven low by another device. 0 0 disable the afi. 1 enable the afi. 2 naie transmitter no acknowledge interrupt enable. this enables the nai interrupt signalling that transmitted byte was not acknowledged. 0 0 disable the nai. 1 enable the nai. 3 drmie master transmitter data request interrupt enable. this enables the drmi interrupt which signals that the master transmitter has run out of data, has not issued a stop, and is holding the scl line low. 0 0 disable the drmi interrupt. 1 enable the drmi interrupt. 4 drsie slave transmitter data request interrupt enable. this enables the drsi interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the scl line is being held low. 0 0 disable the drsi interrupt. 1 enable the drsi interrupt. 5 refie receive fifo full interrupt enable. this enables the receive fifo full interrupt to indicate that the receive fifo cannot accept any more data. 0 0 disable the rffi. 1 enable the rffi. 6 rfdaie receive data available interrupt enable. this enables the dai interrupt to indicate that data is available in the receive fifo (i.e. not empty). 0 0 disable the dai. 1 enable the dai. 7 tffie transmit fifo not full interrupt enable. this enables the transmit fifo not full interrupt to indicate that the more data can be written to the transmit fifo. note that this is not full. it is intended help the cpu to write to the i 2 c block only when there is room in the fifo and do this without polling the status register. 0 0 disable the tffi. 1 enable the tffi.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 406 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.11 i 2 c clock high register the clk register holds a terminal count for counting 48 mhz clock cycles to create the high period of the slower i 2 c serial clock, scl. 14.8.12 i 2 c clock low register the clk register holds a terminal count for counting 48 mhz clock cycles to create the low period of the slower i 2 c serial clock, scl. 8 srst soft reset. this is only needed in unusual circumstances. if a device issues a start condition without issuing a st op condition. a system timer may be used to reset the i 2 c if the bus remains busy longer than the time-out period. on a soft reset, the tx and rx fifos are flushed, i2c_sts register is cleared, and all internal state machines are reset to appear idle. the i2c_clkhi, i2c_clklo and i2c_ctl (except soft reset bit) are not modified by a soft reset. 0 0 see the text. 1 reset the i 2 c to idle state. self clearing. 31:9 - reserved. read value is undefined, only zero should be written. na table 322. i 2 c control register (i2c_ctl - address 0x2008 c308) bit description bit symbol value description reset value table 323. i 2 c_clkhi register (i2c_clkhi - address 0x2008 c30c) bit description bit symbol description reset value 7:0 cdhi clock divisor high. this value is the number of 48 mhz clocks the serial clock (scl) will be high. 0xb9 31:8 - reserved. read value is undefined, only zero should be written. na table 324. i 2 c_clklo register (i2c_clklo - address 0x2008 c310) bit description bit symbol description reset value 7:0 cdlo clock divisor low. this val ue is the number of 48 mhz clocks the serial clock (scl) will be low. 0xb9 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 407 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.13 otg clock control register this register controls the clocking of the otg controller. whenever software wants to access the registers, the corresponding clock control bit needs to be set. the software does not have to repeat this exercise fo r every register access, provided that the corresponding otgclkctrl bits are already set. table 325. otg clock control register (clkctrl - address 0x2008 cff4) bit description bit symbol value description reset value 0 host_clk_en host clock enable 0 0 disable the host clock. 1 enable the host clock. 1 dev_clk_en device clock enable 0 0 disable the device clock. 1 enable the device clock. 2 i2c_clk_en i 2 c clock enable 0 0 disable the i 2 c clock. 1 enable the i 2 c clock. 3 otg_clk_en otg clock enable. in device-only applications, this bit enables access to the portsel register. 0 0 disable the otg clock. 1 enable the otg clock. 4 ahb_clk_en ahb master clock enable 0 0 disable the ahb clock. 1 enable the ahb clock. 31:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 408 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.14 otg clock status register this register holds the clo ck availability status. when ena bling a clock via otgclkctrl, software should poll the corresponding bit in this register. if it is set, then software can go ahead with the register access. software does not have to repeat this exercise for every access, provided that the otgclkctrl bits are not disturbed. table 326. otg clock status register (clkst - address 0x2008 cff8) bit description bit symbol value description reset value 0 host_clk_on host clock status. 0 0 host clock is not available. 1 host clock is available. 1 dev_clk_on device clock status. 0 0 device clock is not available. 1 device clock is available. 2 i2c_clk_on i 2 c clock status. 0 0i 2 c clock is not available. 1i 2 c clock is available. 3 otg_clk_on otg clock status. 0 0 otg clock is not available. 1 otg clock is available. 4 ahb_clk_on ahb master clock status. 0 0 ahb clock is not available. 1 ahb clock is available. 31:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 409 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.8.15 interrupt handling the interrupts set in the otgintst register are set and cleared during hnp switching. all otg related interrupts, if enabled, are rout ed to the usb_otg_int bit in the usbintst register. i 2 c related interrupts are set in the i2c_sts register and routed, if enabled by i2c_ctl, to the usb_i2c_int bit. for more details on the interrupts created by device controller, see the usb device chapter. for interrupts created by the hos t controllers, see the ohci specification. the en_usb_ints bit in the usbintst register enables the routing of any of the usb related interrupts to th e nvic controller (see figure 54 ). remark: during the hnp switching between host and device with the otg stack active, an action may raise seve ral levels of inte rrupts. it is advised to let the otg stack initiate any actions based on interrupts and ignore device and host level interrupts. this means that during hnp switching, the otg stack provides the communication to the host and device controllers. fig 54. usb otg interrupt handling usb_int_req_hp usb_int_req_lp usb_int_req_dma en_usb_ints to nvic usb_host_int usb_otg_int usb_i2c_int usb_need_clock usbintst usb device interrupts usb host interrupts otgintst tmr remove_pu hnp_success hnp_failure usb i2c interrupts
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 410 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.9 hnp support this section describes the hardware support for the host negotiation protocol (hnp) provided by the otg controller. when two dual-role otg devices are connected to each other, the plug inserted into the mini-ab receptacle determines the default role of each device. the device with the mini-a plug inserted becomes the default host (a-device), and the device with the mini-b plug inserted becomes the default peripheral (b-device). once connected, the default host (a-device) and the default peripheral (b-device) can switch host and peripheral roles using hnp. the context of the otg controller operation is shown in figure 55 . each controller (host, device, or otg) communicates with its software stack through a set of status and control registers and interrupts. in addition, the otg software stack communicates with the external otg transceiver through the i 2 c interface and the external transceiver interrupt signal. the otg software stack is responsible for implementing the hnp state machines as described in the on-the-go supplement to the usb 2.0 specification. the otg controller hardware provides support for some of the stat e transitions in the hnp state machines as described in the following subsections. the usb state machines, the hnp switching, and the communications between the usb controllers are described in more de tail in the followi ng documentation: ? usb ohci specification ? usb otg supplement, version 1.2 ? usb 2.0 specification ? isp1302 data sheet and user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 411 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.9.1 b-device: peripheral to host switching in this case, the default role of the otg cont roller is peripheral (b-dev ice), and it switches roles from peripheral to host. the on-the-go supplement defines the behavior of a dual-role b-device during hnp using a state machine diagram. the otg software stack is responsible for implementing all of the states in the dual-role b-device state diagram. the otg controller hardware provides support for the state transitions between the states b_peripheral, b_wait_acon, and b_host in the dual-role b-device state diagram. setting b_hnp_track in the otgstctrl register en ables hardware support for the b-device switching from peripheral to host. the hardware actions after setting this bit are shown in figure 56 . fig 55. usb otg controller with software stack host controller mux ohci stack otg stack device stack usb bus isp1302 otg controller device controller i2c controller
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 412 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller figure 57 shows the actions that the otg software stack should take in response to the hardware actions setting remove_pu, hnp_success, and hnp_failure. the relationship of the software actions to the dual-role b-device states is also shown. b-device states are in bold fo nt with a circle around them. fig 56. hardware support for b-device switchin g from peripheral state to host state idle set hnp_success set port_func[0] drive j on internal host controller port and se0 on u1 wait 25 ? s for bus to settle disconnect device controller from u1 set remove_pu bus suspended ? set hnp_failure, clear b_hnp_track, clear pu_removed reconnect port u1 to the device controller reconnect port u1 to the device controller connect u1 to host controller clear b_hnp_track clear pu_removed pu_removed set? pu_removed set? bus reset/resume detected? connect from a-device detected? bus reset/resume detected? se0 sent by host? b_hnp_track = 0 no yes yes no no yes yes no b_hnp_track = 1 ? no no no yes
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 413 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller note that only the subset of b-device hnp states and state transitions supported by hardware are shown. software is responsible for implementing all of the hnp states. figure 57 may appear to imply that the interrupt bits such as remove_pu should be polled, but this is not necessary if the corresponding interrupt is enabled. following are code examples that show how the actions in figure 57 are accomplished. the examples assume that isp1302 is bein g used as the external otg transceiver. remove d+ pull-up /* remove d+ pull-up through isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x007; // send otg control (clear) register address fig 57. state transitions implemented in software during b-device switching from peripheral to host remove_pu set? hnp_failure set? hnp_success set? b_peripheral when host sends set_feature with b_hnp_enable, set b_hnp_track remove d+ pull-up, set pu_removed b_peripheral add d+ pull-up b_wait_acon b_host no yes go to go to go to yes no no yes
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 414 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller otg_i2c_tx = 0x201; // clear dp_pullup bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi; add d+ pull-up /* add d+ pull-up through isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x006; // send otg control (set) register address otg_i2c_tx = 0x201; // set dp_pullup bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi; 14.9.2 a-device: host to peripheral hnp switching in this case, the role of the otg controller is host (a-device), an d the a-device switches roles from host to peripheral. the on-the-go supplement defines the behavior of a dual-role a-device during hnp using a state machine diagram. the otg software stack is responsible for implementing all of the states in the dual-role a-device state diagram. the otg controller hardware provides suppor t for the state transitions between a_host, a_suspend, a_wait_vfall, and a_peripheral in the dual-role a-device state diagram. setting a_hnp_track in the otgstctrl regist er enables hardware support for switching the a-device from the host state to the device state. the hardware actions after setting this bit are shown in figure 58 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 415 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller figure 59 shows the actions that the otg software stack should take in response to the hardware actions setting tmr, hnp_succ ess, and hnp_failure. the relationship of the software actions to the dual-role a-device states is also shown. a-device states are shown in bold font with a circle around them. fig 58. hardware support for a-device switchin g from host state to peripheral state disconnect host controller from u1 set hnp_failure, clear a_hnp_track clear a_hnp_track set hnp_success connect device to u1 by clearing port_func[0] bus reset detected? otg timer expired? (tmr =1 ) resume detected? connnect host controller back to u1 no no no yes yes yes yes yes idle a_hnp_track = 0 bus suspended ? resume detected ? no no a_hnp_track = 1 ? no
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 416 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller note that only the subset of a-device hnp states and state transitions supported by hardware are shown. software is responsible for implementing all of the hnp states. figure 59 may appear to imply that the interrupt bits such as tmr should be polled, but this is not necessary if the co rresponding interrupt is enabled. following are code examples that show how the actions in figure 59 are accomplished. the examples assume that isp1302 is bein g used as the external otg transceiver. fig 59. state transitions implemented in software during a-device switching from host to peripheral hnp_success set? hnp_failure set? tmr set? a_host when host sends set_feature with a_hnp_enable, set a_hnp_track stop the otg timer a_suspend a_host a_wait_vfall go to a_peripheral go to go to yes yes yes set bdis_acon_en in external otg transceiver load and enable otg timer clear bdis_acon_en bit in external otg transceiver clear bdis_acon_en bit in external otg transceiver discharge v bus stop otg timer suspend host on port 1 go to no no no
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 417 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller set bdis_acon_en in external otg transceiver /* set bdis_acon_en in isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x004; // send mode control 1 (set) register address otg_i2c_tx = 0x210; // set bdis_acon_en bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi; clear bdis_acon_en in external otg transceiver /* set bdis_acon_en in isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x005; // send mode control 1 (clear) register address otg_i2c_tx = 0x210; // clear bdis_acon_en bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi; discharge v bus /* clear the vbus_drv bit in isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x007; // send otg control (clear) register address otg_i2c_tx = 0x220; // clear vbus_drv bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi; /* set the vbus_dischrg bit in isp1302 */ otg_i2c_tx = 0x15a; // send isp1302 address, r/w=0 otg_i2c_tx = 0x006; // send otg control (set) register address otg_i2c_tx = 0x240; // set vbus_dischrg bit, send stop condition /* wait for tdi to be set */ while (!(otg_i2c_sts & tdi)); /* clear tdi */ otg_i2c_sts = tdi;
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 418 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller load and enable otg timer /* the following assumes that the otg timer has previously been */ /* configured for a time scale of 1 ms (tmr_scale = ?10?) */ /* and monoshot mode (tmr_mode = 0) */ /* load the timeout value to implement the a_aidl_bdis_tmr timer */ /* the minimum value is 200 ms */ otg_timer = 200; /* enable the timer */ otg_stat_ctrl |= tmr_en; stop otg timer /* disable the timer ? causes tmr_cnt to be reset to 0 */ otg_stat_ctrl &= ~tmr_en; /* clear tmr interrupt */ otg_int_clr = tmr; suspend host on port 1 /* write to portsuspendstatus bit to suspend host port 1 ? */ /* this example demonstrates the low-level action software needs to take. */ /* the host stack code where this is done will be somewhat more involved. */ hc_rh_port_stat1 = pss;
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 419 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.10 clocking and power management the otg controller clocking is shown in figure 60 . a clock switch controls each clock with th e exception of ahb_slave_clk. when the enable of the clock switch is asserted, its clock outp ut is turned on and its clk_on output is asserted. the clk_on signals are obse rvable in the otgclkst register. to conserve power, the clocks to the device, host, otg, and i 2 c controllers can be disabled when not in use by clearing the respective clk_en bit in the otgclkctrl register. when the entire usb block is not in use, all of its clocks can be disabled by clearing the pcusb bit in the pconp register. when software wishes to access registers in one of the controllers, it should first ensure that the respective controller?s 48 mhz clock is enabled by setting its clk_en bit in the otgclkctrl register and then poll the corres ponding clk_on bit in otgclkst until set. once set, the controller?s clock will remain enabled until clk_en is cleared by software. accessing the regist er of a controller when its 48 mhz cl ock is not enabled will result in a data abort exception.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 420 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller fig 60. clocking and power control clock switch usb clock divider register interface device controller host controller otg controller i2c controller ahb_clk_on ahb_slave_clk ahb_master_clk dev_clk_on host_clk_on otg_clk_on i2c_clk_on dev_clk_en host_clk_en otg_clk_en i2c_clk_en dev_dma_need_clk host_dma_need_clk dev_need_clk host_need_clk ahb_clk_en ahb_need_clk pcusb cclk usbclk (48 mhz) en clock switch en clock switch en en clock switch clock switch en usb_need_clk
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 421 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.10.1 device clo ck request signals the device controller has two clock request signals, dev_need_clk and dev_dma_need_clk. when asserted, these signals turn on the device?s 48 mhz clock and ahb_master_clk respectively. the dev_need_clk signal is asserted while the device is not in the suspend state, or if the device is in the suspend state and activity is detected on the usb bus. the dev_need_clk signal is de-asserted if a disco nnect is detected (con bit is cleared in the sie get device status register ? section 12.10.6 ). this signal allows dev_clk_en to be cleared during normal operation when software does not need to access the device controller registers ? the device will continue to func tion normally and auto matically shut off its clock when it is suspended or disconnected. the dev_dma_need_clk signal is asserted on any device controller dma access to memory. once asserted, it rema ins active for 2 ms (2 frames), to help assure that dma throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last dma access, dev_dma_need_ clk is de-asserted to help conserve power. this signal allows ahb_clk_en to be cleared during normal operation. 14.10.1.1 host clock request signals the host controller has two clock request signals, host_need_clk and host_dma_need_clk. when asserted, these signals turn on the host?s 48 mhz clock and ahb_master_clk respectively. the host_need_clk signal is asserted while the host controller functional state is not usbsuspend, or if the func tional state is usbsuspend and resume signaling or a disconnect is detected on the usb bus. this signal allows host_clk_en to be cleared during normal operation when software does not need to access the host controller registers ? the host will continue to function no rmally and automatically shut off its clock when it goes into the usbsuspend state. the host_dma_need_clk signal is asserted on any host controller dma access to memory. once asserted, it rema ins active for 2 ms (2 frames), to help assure that dma throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last dma access, host_dma_nee d_clk is de-asserted to help conserve power. this signal allows ahb_clk_en to be cleared during normal operation. 14.10.2 power-down mode support the cpu can be configured to wake up from power-down mode on any usb bus activity. when the chip is in power-down mode and the usb interrupt is enabled, the assertion of usb_need_clk causes the chip to wake up from power-down mode. before power-down mode can be entered when the usb activity interrupt is enabled, usb_need_clk must be de-asserted. this is accomplished by clearing all of the clk_en bits in otgclkctrl and putting the host controller into the usbsuspend functional state. if it is necessary to wait for either of the dma_need_clk signals or the dev_need_clk to be de-asserted, the stat us of usb_need_clk can be polled in the usbintst register to determine when they have all been de-asserted.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 422 of 942 nxp semiconductors UM10562 chapter 14: lpc408x/407x usb otg controller 14.11 usb otg controller initialization the otg device controller initializat ion includes the following steps: 1. enable the device controller by setting the pcusb bit of pconp. 2. configure and enable the alt pll (pll1) or main pll (pll0) to provide 48 mhz for usbclk and the desired frequency for cclk. for the procedure for determining the pll setting and configuration, see section 3.10.5 . 3. enable the desired controller clocks by setting their respective clk_en bits in the usbclkctrl register. poll the corresponding clk_on bits in the usbclkst register until they are set. 4. enable the desired usb pin functions by writing to the corresponding iocon registers. 5. follow the appropriate steps in section 12.13 ? usb device controller initialization ? to initialize the device controller. 6. follow the guidelines given in the openhc i specification for initializing the host controller.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 423 of 942 15.1 basic configuration the spifi peripheral is configured using the following registers: 1. power: in the pconp register (see section 3.3.2.2 ), set bit pcspifi. remark: on reset, the spifi is disabled (pcspifi = 0). 2. spifi clock: see section 3.3.3.6 . 3. pins: select spifi pins and pin mode s through the relevant iocon registers ( section 7.4.1 ). 15.2 features ? quad spi flash interface (spifi) interface to external flash. ? transfer rates of up to spifi_clk/2 bytes per second. ? code in the serial flash memory can be executed as if it was in the cpu?s internal memory space. this is accomplished by ma pping the external flash memory directly into the cpu memory space. ? supports 1-, 2-, and 4-bit bidirectional serial protocols. ? half-duplex protocol compatible with various vendors and devices (see table 329 ). ? using the spifi, as described in this chap ter, accomplished with a driver library available from nxp semiconductors. UM10562 chapter 15: lpc408x/407x sp i flash interface (spifi) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 424 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.3 general description the spi flash interface (spifi) allows low-cost serial flash memories to be connected to the cpu with little performance penalty compared to parallel flash devices with higher pin count. a driver api included in on-chip rom handles setup, programming and erasure. after an initialize call to the spifi driver, the flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or dma. many serial flash devices use a half-duplex command-driven spi protocol for device setup and initialization. quad devices then use a half-duplex, command-driven 4-bit protocol for normal operation. different serial flash vendo rs and devices accept or require different commands and command formats. spifi provides sufficient flexibility to be compatible with common flash devices, and includes extensions to help insure compatibility with future devices. serial flash devices respond to commands sent by software or automatically sent by the spifi when software reads either of the two read-only serial flash regions in the memory map (see ta b l e 3 2 7 ). 15.4 pin description table 327. spifi flash memory map memory address spifi data 0x2800 0000 to 0x28ff ffff remark: this is the address space allocated to the spifi. the area allocated allows a maximum of 16 mb of spi flash to be mapped into the cpu memory space. in practice, the usable space is limited to the size of the connected device table 328. spifi pin description pin function direction description spifi_sck o serial clock for the flash memory, switched only during active bits on the mosi/io0, miso/io1, and io3:2 lines. spifi_cs o chip select for the flash memory, driven low while a command is in progress, and high between commands. in the typical case of one serial slave, this signal can be connected directly to the device. if more than one serial slave is connected, software and off-chip hardware should use general-purpose i/o signals in combination with this signal to generate the chip selects for the various slaves. spifi_mosi or io0 i/o this is an output except in quad/dual input data fields. after a quad/dual input data field, it becomes an output again one serial clock period after cs goes high. spifi_miso or io1 i/o this is an output in quad/dual opcode, address, intermediate, and output data fields, and an input in spi mode and in quad/dual input data fields. after an input data field in quad/dual mode, it becomes an output again one serial clock period after cs goes high. spifi_sio[3:2] i/o these are outputs in quad opcode, address, intermediate, and output data fields, and inputs in quad input data fields. if the flash memory does not have quad capability, these pins can be assigned to gpio or other functions.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 425 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.5 supported devices serial flash devices with the following features are supported: ? read jdec id ? page programming ? at least one command with uniform erase size throughout the device table 329 shows a list of vendor qspi devices wh ich are verified to support the spifi api. other devices can be used and will run in basic single spi mode at lower speed. remark: all qspi devices have been tested at an operating voltage of 3.3 v. [1] level translation circuitry, which might af fect performance, is required for these parts. the following devices lack one or more of these features and are not supported: ? elite: f25l004, f25l008, f25l016. ? eon: 25b64. ? sst: 25vf512, 25wf512, 25vf010, 25 wf010, 25lf020, 25vf020, 25wf020, 25vf040, 25wf040, 25vf080, 25wf080, 25vf016, 25vf032. table 329. supported qspi devices manufacturer device name amic a25l512, a25l010, a25l020, a25l040, a25l080, a25l016, a25l032, a25lq032 atmel at25f512b, at25df021, at25df041a, at25df081a, at25df161, at25dq161, at25df321a, at25df641 chingis pm25ld256, pm25ld512, pm25ld010, pm25ld020, pm25ld040, pm25lq032 elite (esmt) f25l08p, f25l16p, f25l32p, f25l32q eon en25f10, en25f20, en25f40, en25q40, en25f80, en25q80, en25qh16, en25q32, en25q64, en25q128 gigadevice gd25q512, gd25q10, gd25q20, gd25q40, gd25q80, gd25q16, gd25q32, gd25q64 macronix mx25l8006, mx25l8035, mx25l8036, mx25u8035 [1] , mx25l1606, mx25l1633, mx25l1635, mx25l1636, mx25u1635 [1] , mx25l3206, mx25l3235, mx25l3236, mx25u3235 [1] , mx25l6436, mx25l6445, mx25l6465, mx25l12836, mx25l12845, mx25l12865, mx25l25635, mx25l25735 numonyx m25p10, m25p20, m25p40, m25p80, m25px80, m25p16, m25px16, m25p32, m25px32, m25p64, m25px64, n25q032, n25q064, n25q128 spansion s25fl004k, s25fl008k, s25fl016k, s25fl032k, s25fl032p, s25fl064k, s25fl064p, s25fl129p sst sst26vf016, sst26vf032, sst25vf064 winbond w25q40, w25q80, w25q16, w25q32, w25q64
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 426 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.6 spifi hardware the spifi has a base address for the registers and a base address for the memory area in which the serial flash connected to the spifi can be read. the first operation with the serial flash is read jedec id, which is implemented by most serial flash devices. depending on the device identity code returned by the serial flash in this operation, device-specific commands are used for further operation. programming and other operations on the serial flash are performed by api calls as described in this document. 15.7 spifi software library 15.7.1 spifi function allocation table 330 shows an overview of the spifi api calls. for details see section 15.7.2 . table 330. spifi function allocation function description spifi_init this call sends the standardized jedec id command to the attached serial flash device. if a serial flash responds with an id known to the spifi api, it is set up for operation as standard memory. parameter0 - pointer to spifiobj parameter1 - (minimum clock cy cles with cs pin high) - 1 parameter2 - spifi options parameter3 - serial clock rate return - spifi error code spifi_program this call programs length bytes in the serial flash. obj must point to the object returned by the preceding spifi_init call. parameter0 - pointer to the object returned by the preceding spifi_init call. parameter1 - source address (in ram or ot her memory) of the data to be programmed. parameter2 - number of bytes to be programmed. return - spifi error code. spifi_erase this command can be used to erase sections of the serial flash. it is not needed for re-programing because spifi_program automatically erases as necessary in order to accomplish required programming. obj should point to the object returned by the preceding spifi_init call. parameter0 - pointer to the object returned by the preceding spifi_init call. parameter1 - spifi memory area to be erased. return - spifi error code
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 427 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.7.2 spifi function calls 15.7.2.1 calling the spifi driver remark: compile any module that calls the spifi api with the compiler set for arm abi compatibility. this is the default in most compilers. 15.7.2.2 spifi initialization call spifi_init the spifi initialization api call sends the standardized read jedec id command to the attached serial flash device. if a serial flash responds, it is set up for reading in arm memory space. int spifi_init (spifiobj *obj, unsigned cshigh, unsigned options, uclnsigned mhz) after a spifi_init call that returns one of the unknown error codes (0x20009 to 0x20006, see table 332 ), the caller can read and check the spifi memory area but should not issue any spifi_program or spifi_erase calls because not enough is known about the device to accomplish these tasks. spifi_init can be called repeatedly in order to change some of its operands. the subsequent call need not use the same spifiobj , and need not use the same version of the driver as the preceding call. the only case in which problems should arise with reusing spifi_init is if the spifi and microcontroller hardware has been reset but the serial flash hardware has not (since most serial flashes don't have a reset pin). parameter0 obj obj points to an area of memory large enough to receive the object created by spifi_init. the space required for the spifi object is 192 bytes. parameter1 cshigh cshigh is one less than the minimum number of clock cycles with the cs pin high, that the spifi should maintain between commands. compute this parameter from the spifi clock period and the minimum high time of cs from the serial flash data sheet: cshigh = ceiling(min cs high / spifi_clk ) - 1 where ceiling means round up to the next higher integer if the argument isn't an integer. parameter2 options options contains 10 bits controlling the binary choices shown in table 331 . options can be 0 or any and or or combinati on of the bits represented in table 331 . an optional use of names for the enumeration of bit values is also shown. table 331. bit values for spifi_init options parameter bit value description name 0 scl output mode 0 scl is low when a frame/command is not in progress. s_mode0 1 the scl output is high when a frame/ command is not in progress. note that s_mode3+ s_fullclk+s_rcvclk is not allowed. use s_mode0 or s_intclk. s_mode3 1 spifi read mode 0 the fastest read operation provided by the device will be used. s_maximal 1 spi mode and the slowest, most basic/ compatible read operation will be used. s_minimal
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 428 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) parameter3 mhz mhz is the serial clock rate divided by 1000000, rounded to an integer. it is used for devices that allow a variable number of dummy bytes between the address and the read data in a memory read command. this operand is only required for some numonyx and winbond quad devices, but it is good practice to include it in a ll spifi_init calls. return a return value of zero indicates succes s. non-zero error codes are listed in table 332 5:2 0 reserved - 6 sampling edge - 0 data from the serial flash is sampled on rising edges of the scl output, as in classic spi applications. suitable for slower clock rates. s_halfclk 1 data from the serial flash is sampled on falling edges on the scl output, allowing a full clock period for the serial flash to present each bit or group of bits. s_fullclk 7 sampling clock 0 data is sampled using the internal clock from which the scl pin is driven. s_intclk 1 data is sampled using the scl clock fed back from the pin. this allows more time for the serial flash to present each bit or group of bits, but when used with s_fullclk can endanger hold time for data from the flash. s_rcvclk 8 spifi mode 0 if the device can operate in quad mode, quad mode will be used, else spi mode. - 1 if the connected device can operate in dual mode (2 bits per clock), dual mode will be used, else spi mode. s_dual 90reserved - table 331. bit values for spifi_init options parameter bit value description name table 332. error codes for spifi_init error code description 0x2000a no operative serial flash (jedec id all zeroes or all ones) 0x20009 unknown manufacturer code 0x20008 unknown device type code 0x20007 unknown device id code 0x20006 unknown extended device id value 0x20005 device status error 0x20004 operand error: s_mode3 + s_fullclk + s_rcvclk selected in options
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 429 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.7.2.3 spifi program call spifi_program the spifi program api call programs opers.length bytes in the serial flash. int spifi_program (spifiobj *obj, char *source, spifiopers *opers) a spifi_program call with source equal to opers.dest and opers.options not including s_force_erase will not do any erasing nor programming, since the data at opers.dest is equal to the data at source. such a call can be used to protect or unprotect sectors depending on the value of opers.protect . parameter0 obj obj points to the object returned by the preceding spifi_init call. parameter1 source source is the address in ram or other memory of the data to be programmed. parameter2 opers parameter2 is defined through the spifiopers c struct (see section 15.7.2.5 ). opers.length is the length of bytes to be programmed in the serial flash. opers.dest is the destination address of the data in the spifi memory, and opers.options defines the options for programming the spifi. return spifi_program does not return until programming and erasure have been completed or an error is encountered. a return value of zero indicates success. non-zero error codes are listed in table 333 . table 333. error codes for spifi_program and spifi_erase error code description 0x20007 programming and erasure cannot be done because the serial flash was not identified in the spifi_init operation. 0x20005 device status error 0x20004 operand error: the dest and/or length operands were out of range. see address operands and checking below. 0x20003 time-out waiting for program or erase to begin: protection could not be removed. 0x20002 internal error in api code. 0x2000b s_caller_erase is included in options, and erasure is required. other other non-zero values can occur if options selects verification. they will be the address in the spifi memory area at which the first discrepancy was found.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 430 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.7.2.4 spifi erase call spifi_erase the spifi_erase call can be used instead of the spifi_program call to speed up erasing large memory areas. since erasing is also done by spifi_program , the spifi_erase call is not strictly necessary. int spifi_erase (spifiobj *obj, spifiopers *opers) parameter0 obj obj points to the object returned by the preceding spifi_init call. parameter1 opers parameter1 is defined through the spifiopers c struct (see section 15.7.2.5 ). the code will use the largest un its of erasure it can to acco mplish the indicated operation and will use the opers. scratch area only when required by a starting or ending address that is not a multiple of the smallest available erase size. th e driver will attempt to remove any protection on the sectors indicated by opers.dest and opers.length. if this removal succeeds, the opers.protect val ue determines the protection of the sectors on return, as described in section 15.7.2.7 . return return values are the same as for spifi_program. a return value of zero indicates success. non-zero error codes are listed in table 333
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 431 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.7.2.5 spifi operands for program and erase spifiopers is a c struct that contains operands for the spifi_program and spifi_erase calls. typedef struct { char *dest; /* starting address for programming or erasing */ unsigned length;/* number of bytes to be programmed or erased */ char *scratch;/* address of work area or null */ int protect; /* protection to apply after programming/erasing is done */ unsigned options;/* see the table below */ } spifiopers; dest specifies the first address to be programme d or erased, either in the spifi memory area or as a zero-based device address. if dest is not a multiple of th e smallest sector size that's uniformly available throughout the serial fl ash, the first part of the first sector is one of the following: ? preserved if a scratch addres s is provided and/or an erase isn't needed for the first sector. ? erased to all ones if scratch is null and an erase is needed for the first sector. similarly, if dest plus l ength is not a multiple of the sector size, the last part of the last sector is one of the following: ? preserved if scratch is non-zero and/or an erase isn't needed for the last sector. ? erased to all ones if scratch is zero an d an erase is needed for the last sector. for either spifi_program or spifi_erase , scratch should be null or the address of an area of ram that the spifi driver can use to save data during erase operations. if provided, the scratch area should be as large as the smallest erase size that is available throughout the serial flash device. if scratch is null (zero) and an erase is necessary, any bytes in the first erase block before dest are left in erased state (all ones), as are any bytes in the last erase block after dest + length . the driver uses the least number of by tes possible in the scratch area. if dest and dest + length - 1 are in separate erase blocks, the driver will use the larger of (the number of bytes before dest in the first erase block) and (the number of bytes after ( dest + length ) in the last erase block). if only one er ase block is involved , the driver will use the sum of these two numbers. options contains 10 bits controlling the binary choices shown in table 334 . options can be 0 or any and or or combinati on of the bits represented in table 334 . an optional use of names for the enumeration of bit values is also shown. unless options includes s_caller_prot, the driver attempts to remove write-protection on the sectors implied by dest and length . the protect operand indicates whether the driver should protect the sectors after programming is completed. see section 15.7.2.7 for details of the protect value.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 432 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) table 334. bit values for spifiopers options parameter bit value description name 1:0 0 reserved - 2erase mode - 0 erasing is done when necessary. s_erase_as_reqd 1 all sectors in dest to dest + length will be erased. s_force_erase 3e r a s e m o d e 0 erasing is done when necessary. s_erase_as_reqd 1 erasing is handled by the caller not by the driver. s_caller_erase 4 verify program - 0 no reading or checking will be done. s_no_verify 1 data will be read back and check ed after programming. s_verify_prog 5 verify erase - 0 no reading or checking will be done. s_no_verify 1 sectors will be read back and checked for 0xff after erasing s_verify_erase 8:6 0 reserved - 9 write protection - 0 the driver removes protection before t he operation and sets it as specified afterward. s_driver_prot 1 write protection is handled by the caller not by the driver. s_caller_prot
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 433 of 942 nxp semiconductors UM10562 chapter 15: lpc408x/407x spi flash interface (spifi) 15.7.2.6 address operands and checking for both spifi_program and spifi_erase , the opers.dest value can be either the (zero-based) address within the serial flash or an address in the spifi memory area. opers.dest and opers.length operands are always checked against the device size; when verification is requested, they are also ch ecked against the allocated size of the spifi memory area. 15.7.2.7 protection serial flash devices provide write-protection in several ways. most devices simply have 2 to 5 bits in their status registers that specify what fraction of the device is write protected, possibly in conjunction with a bit that specifies whether the fraction is at top or bottom and/or a bit that specifies whether the fracti on is protected or unprotected. for such devices, at the start of spifi_program or spifi_erase the driver simply saves the status byte, then clears all of the 2 to 5 bits, so that the whole device is write-enabled. the opers.protect value of a spifi_program or spifi_erase on such a device can be 0 to leave the device fully write-enabled, -1 to restore the protection status saved at the start of the call, or any other non-zero value to set the protection status to that value. (consult the device data sheet for the content of the latter value.) some serial flash devices use individual protection bits for each sector. these include sst quad devices, atmel devices, and ma cronix devices that provide a wpsel command and on which such a command has been executed (setting wpsel is an irrevocable operation). similarly to devices whic h include status register protection, -1 in the opers.protect value makes the driver restore protecti on to the state in effect before the call. 0 leaves the programmed/erased sectors write-enabled, and 1 write-protects them. for small (high and low) sectors on sst quad devices only, opers.protect can be 3 to read- and write-protect the sectors, or 2 to read-protect but write-enable them (write only memory!). 2 and 3 work like 0 and 1 respecti vely for other sectors and other devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 434 of 942 16.1 how to read this chapter the sd card interface is available on most lpc408x/407x devices, see section 1.4 for details. 16.2 basic configuration the sd card interface (also known as mci or multimedia card interf ace) is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pc_sd. remark: on reset, the sd card interface is disabled (pcsd = 0). 2. peripheral clock: the sd card interface operates from the common pclk that clocks both the bus interface and functional portion of most apb peripherals. see section 3.3.3.5 . 3. pins: select sd card inte rface pins and their modes through the relevant iocon registers ( section 7.4.1 ). 4. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 16.3 introduction the secure digital card interface is an in terface between the advanced peripheral bus (apb) system bus and multimedia and/or secure digital memory cards. it consists of two parts: ? the sd card interface provides all functions specific to the secure digital memory card, such as the clock generation unit, power management control, command and data transfer. the interface also supports the multimedia card interface. ? the apb interface accesses sd card interfac e registers, and gene rates interrupt and dma request signals. 16.4 features the following features are provided by the sd card interface: ? conformance to secure digital memory card physi cal layer specification, v0.96 . ? conformance to multimedia card sp ecification v2.11 . ? use as a multimedia card bus or a secure digital memory card bus host. it can be connected to several multim edia cards, or a single secure digital memory card. ? dma supported through the general purpose dma controller. UM10562 chapter 16: lpc408x/407x sd card interface rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 435 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.5 pin description 16.6 functional overview the sd card interface may be used as a secure digital memory card bus host (see section 16.6.1 ? secure digital memory card ? ) or as a multimedia card bus host (see section 16.6.2 ? multimedia card ? ). a single secure digital memory card or up to 4 multimedia cards (depending on board loading) may be connected. 16.6.1 secure digital memory card figure 61 shows the secure digital memory card connection. 16.6.1.1 secure digital memory card bus signals the following signals are used on the secure digital memory card bus: ? sd_clk host to card clock signal ? sd_cmd bidirectional command/response signal ? sd_dat[3:0] bidirectional data signals 16.6.2 multimedia card figure 62 shows the multimedia card system. table 335. sd/mmc card interface pin description pin name type description sd_clk output clock output sd_cmd input command input/output. sd_dat[3:0] output data lines. only sd_dat[0] is used for multimedia cards. sd_pwr output power supply enable for external card power supply. fig 61. secure digital memory card connection secure digital memory card controller secure digital memory card clk cmd d[3:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 436 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface multimedia cards are grouped into three types according to their function: ? read only memory (rom) cards, containing pre-programmed data ? read/write (r/w) cards, used for mass storage ? input/output (i/o ) cards, used for communication the multimedia card system transfers commands and data using three signal lines: ? clk: one bit is transferred on both command and data lines with each clock cycle. the clock frequency varies between 0 mhz and 20 mhz (for a multimedia card) or 0 mhz and 25 mhz (for a secu re digital memory card). ? cmd: bidirectional command channel that in itializes a card and transfers commands. cmd has two operational modes: ? open-drain for initialization ? push-pull for command transfer ? dat: bidirectional data channel, operating in push-pull mode 16.6.3 sd card interface details figure 63 shows a simplified block diagram of the sd card interface. fig 62. multimedia card system multimedia card bus power supply multimedia card interface multimedia card stack card card card
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 437 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface the sd card interface is a secure digital/ multimedia memory card bus master that provides an interface to a mu ltimedia card stack or to a secure digital memory card. it consists of five subunits: ? adapter register block ? control unit ? command path ? data path ? data fifo 16.6.3.1 adapter register block the adapter register block contains all system registers. this block also generates the signals that clear the static flags in the mu ltimedia card. the clear signals are generated when 1 is written into the corresponding bit location of the mciclear register. 16.6.3.2 control unit the control unit contains the power manageme nt functions and the clock divider for the memory card clock. there are three power phases: ? power-off ? power-up ? power-on the power management logic controls an exte rnal power supply unit, and disables the card bus output signals during the power-off or power-up phases. the power-up phase is a transition phase between the power-off and power-on phases, and allows an external power supply to reach the card bus operating voltage. a device driver is used to ensure that the interface remains in the power-up ph ase until the external power supply reaches the operating voltage. fig 63. sd card interface multimedia card interface adapter registers control unit fifo command path data path apb bus apb interface sd_cmd sd_clk sd_data [3:0] sd_pwr
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 438 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface the clock management logic generates and co ntrols the sd_clk signal. the sd_clk output can use either a clock divide or clock bypass mode. the clock output is inactive: ? after reset ? during the power-off or power-up phases ? if the power saving mode is enabled and the card bus is in the idle state (eight clock periods after both the command and data path subunits enter the idle phase) 16.6.3.3 command path the command path subunit sends commands to and receives responses from the cards. 16.6.3.4 command path state machine when the command register is written to and the enable bit is set, command transfer starts. when the command has been sent, the command path state machine (cpsm) sets the status flags and enters the idle stat e if a response is not required. if a response is required, it waits for the response (see figure 64 ). when the response is received, the received crc code and the internally generated code are compared, and the appropriate status flags are set. when the wait state is entered, the comm and timer starts running. if the timeout 1 is reached before the cpsm moves to the recei ve state, the timeout flag is set and the idle 2 state is entered. if the interrupt bit is set in the command register, the timer is disabled and the cpsm waits for an interrupt reques t from one of the cards. if a pending bit is set in the command register, the cpsm enters the pend state, and waits for a cmdpend signal from the data path subunit. when cmdpend is detected, the cpsm moves to the send state. this enables the data counter to tri gger the stop command transmission. fig 64. command path state machine idle pend send wait receive enabled and pending command disabled enabled and command start lastdata wait for response disabled or no response disabled or timeout response started response received or disabled or command crc failed 1. the timeout period has a fixed va lue of 64 sd_clk clocks period. 2. the cpsm remains in the idle state for at least eight sd_clk periods to meet ncc and nrc timing constraints.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 439 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface figure 65 shows the command transfer. 16.6.3.5 command format the command path operates in a half-duplex mode, so that commands and responses can either be sent or received. if the cpsm is not in the send state, the sd_cmd output is in hi-z state, as shown in figure 65 . data on sd_cmd is synchronous to the rising sd_clk edge. all commands have a fixed length of 48 bits. table 336 shows the command format. the sd card interface supports two response types. both use crc error checking: ? 48 bit short response (see table 337 ) ? 136 bit long response (see table 338 ) note: if the response does not contain crc (cmd1 response), the device driver must ignore the crc failed status. fig 65. command transfer sd_clk state sd_cmd command response command idle send wait receive idle send hi-z controller drives hi-z card drives hi-z controller drives min 8 sd_clk table 336. command format bit position width value description 0 1 1 end bit. 7:1 7 - crc7 39:8 32 - argument. 45:40 6 - command index. 46 1 1 transmission bit. 47 1 0 stat bit. table 337. simple response format bit position width value description 0 1 1 end bit. 7:1 7 - crc7 (or 1111111). 39:8 32 - argument. 45:40 6 - command index. 46 1 0 transmission bit. 47 1 0 start bit.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 440 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface the command register contains the command index (six bits sent to a card) and the command type. these determine whether the command requires a response, and whether the response is 48 or 136 bits long (see section 16.7.4 ? command register ? for more information). the command path implements the status flags shown in table 339 (see section 16.7.11 ? status register ? for more information). the crc generator calculates the crc checks um for all bits before the crc code. this includes the start bit, transmitter bit, co mmand index, and command argument (or card status). the crc checksum is calculated for t he first 120 bits of cid or csd for the long response format. note that the start bit, transmitter bit and the six reserved bits are not used in the crc calculation. the crc checksum is a 7 bit value: crc[6:0] = remainder [(m(x) ? x 7 ) / g(x)] g(x) = x 7 + x 3 + 1 m(x) = (start bit) ? x 39 + ? + (last bit before crc) ? x 0 , or m(x) = (start bit) ? x 119 + ? + (last bit before crc) ? x 0 16.6.3.6 data path the card data bus width can be programmed using the clock control register. if the wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (sd_dat[3:0]). if the wide bus mode is not enabled, only one bit per clock cycle is transferred over sd_dat[0]. depending on the transfer direction (send or receive), the data path state machine (dpsm) moves to the wait_s or wait_r state when it is enabled: ? send: the dpsm moves to the wait_s state. if there is data in the send fifo, the dpsm moves to the send state, and the data path subunit starts sending data to a card. table 338. long response format bit position width value description 0 1 1 end bit. 127:1 127 - cid or csd (including internal crc7). 133:128 6 111111 reserved. 134 1 1 transmission bit. 135 1 0 start bit. table 339. command path status flags flag description cmdrespend set if response crc is ok. cmdcrcfail set if response crc fails. cmdsent set when command (that does not require response) is sent. cmdtimeout response timeout. cmdactive command transfer in progress.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 441 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface ? receive: the dpsm moves to the wait_r state and waits for a start bit. when it receives a start bit, the dpsm moves to t he receive state, and the data path subunit starts receiving data from a card. 16.6.3.7 data path state machine the dpsm operates at sd_clk frequency. data on the card bus signals is synchronous to the rising edge of sd_clk. the dpsm has six states, as shown in figure 66 . ? idle: the data path is inactive, and the sd_dat[3:0] outputs ar e in hi-z. when the data control register is written and the enable bit is set, the dpsm loads the data counter with a new value and, depending on the data direction bit, moves to either the wait_s or wait_r state. wait_r: if the data counter equals zero, the dpsm moves to the idle state when the receive fifo is empty. if the data coun ter is not zero, the dpsm waits for a start bit on sd_dat. the dpsm moves to the receive state if it receives a start bit before a timeout, and loads the data block counter. if it reaches a time out before it detects a start bit, or a start bit error occurs, it moves to the idle state and sets the timeout status flag. ? receive: serial data received from a card is packed in bytes and written to the data fifo. depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: ? in block mode, when the data block counter reaches zero, the dpsm waits until it receives the crc code. if the received code matches the internally generated crc code, the dpsm moves to the wait_r stat e. if not, the crc fail status flag is set and the dpsm moves to the idle state. fig 66. data path state machine idle busy send wait_r receive wait_s reset disabled or fifo underrun or end of data or crc fail disabled or crc fail or timeout disabled or end of data not busy end of packet data ready enable and send disabled or rx fifo empty or timeout or start bit error enable and not send disabled or crc fail start bit end of packet or end of data or fifo overrun
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 442 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface ? in stream mode, the dpsm receives data while the data counter is not zero. when the counter is zero, the remaining data in the shift register is written to the data fifo, and the dpsm moves to the wait_r state. if a fifo overrun error occurs, the dpsm sets the fifo error flag and moves to the wait_r state. ? wait_s: the dpsm moves to the idle state if the data counter is zero. if not, it waits until the data fifo empty flag is deasserted, and moves to the send state. note: the dpsm remains in the wait_s state for at least two clock periods to meet nwr timing constraints. ? send: the dpsm starts sending data to a card. depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: ? in block mode, when the data block counter reaches zero, the dpsm sends an internally generated crc code and end bit, and moves to the busy state. ? in stream mode, the dpsm sends data to a card while the enable bit is high and the data counter is not zero. it then moves to the idle state. if a fifo underrun error occurs, the dpsm sets the fifo error flag and moves to the idle state. ? busy: the dpsm waits for the crc status flag: ? if it does not receive a positive crc status, it moves to the idle state and sets the crc fail status flag. ? if it receives a positive crc status, it moves to the wait_s state if sd_dat[0] is not low (the card is not busy). if a timeout occurs while the dpsm is in the busy state, it se ts the data timeout flag and moves to the idle state. the data timer is enabled when the dpsm is in the wait_r or busy state, and generates the data timeout error: ? when transmitting data, the timeout occurs if the dpsm stays in the busy state for longer than the programmed timeout period ? when receiving data, the timeout occurs if the end of the data is not true, and if the dpsm stays in the wait_r state for l onger than the programmed timeout period. 16.6.3.8 data counter the data counter has two functions: ? to stop a data transfer when it reaches ze ro. this is the end of the data condition. ? to start transferring a pending command (see figure 67 ). this is used to send the stop command for a stream data transfer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 443 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface the data block counter determines the end of a data block. if the counter is zero, the end-of-data condition is true (see section 16.7.9 ? data control register ? for more information). 16.6.3.9 bus mode in wide bus mode, all four data signals (sd_dat[3:0]) are used to transfer data, and the crc code is calculated separately for each da ta signal. while transmitting data blocks to a card, only sd_dat[0] is used for the crc token and busy signalling. the start bit must be transmitted on all four data signals at the same time (during the same clock period). if the start bit is not detected on all data signals on the same clock edge while receiving data, the dpsm sets the start bit error flag and moves to the idle state. the data path also operates in half-duplex mode, where data is either sent to a card or received from a card. while not being transf erred, sd_dat[3:0] are in the hi-z state. data on these signals is synchronous to the rising edge of the clock period. if standard bus mode is selected the sd_dat[3:1] outputs are always in hi-z state and only the sd_dat[0] output is dr iven low when data is transmitted. design note: if wide mode is selected, all data outputs enabled at the same time. if not, the sd_dat[3:1] outputs are always off, and on ly the sd_dat[0] output is driven low when data is transmitted. 16.6.3.10 crc token status the crc token status follows each write data block, and determines whether a card has received the data block correctly. when the token has been received, the card asserts a busy signal by driving sd_dat[0] low. table 340 shows the crc token status values. fig 67. pending command start 3 2 1 0 7 6 5 4 3 2 1 z z z z z s cmd cmd cmd cmd cmd 7 6 pend send data counter sd_clk sd_cmd cmd state sd_dat0 cmdpend table 340. crc token status token description 010 card has received error-free data block. 101 card has detected a crc error.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 444 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.6.3.11 status flags table 341 lists the data path status flags (see section 16.7.11 ? status register ? on page 452 for more information). 16.6.3.12 crc generator the crc generator calculates the crc checksum only for the data bits in a single block, and is bypassed in data stream mo de. the checksum is a 16 bit value: crc[15:0] = remainder [(m(x) ? x 15 ) / g(x)] g(x) = x 16 + x 12 + x 5 + 1 m(x) - (first data bit) ? x n + ? + (last data bit) ? x 0 16.6.3.13 data fifo the data fifo (first-in-first-out) subunit is a data buffer with transmit and receive logic. the fifo contains a 32 bit wide, 16-word deep data buffer, and transmit and receive logic. because the data fifo operates in th e apb clock domain (pclk), all signals from the subunits in the sd card interface clock domain (mclk) are re-synchronized. depending on txactive and rxactive, the fifo can be disabled, transmit enabled, or receive enabled. txactive and rxactive are driven by the data path subunit and are mutually exclusive: ? the transmit fifo refers to the transmit logic and data buffer when txactive is asserted (see section 16.6.3.14 ? transmit fifo ? ) table 341. data path status flags flag description txfifofull transmit fifo is full. txfifoempty transmit fifo is empty. txfifohalfempty transmi t fifo is half full. txdataavlbl transmit fifo data available. txunderrun transmit fifo underrun error. rxfifofull receive fifo is full. rxfifoempty receive fifo is empty. rxfifohalffull receive fifo is half full. rxdataavlbl receive fifo data available. rxoverrun receive fi fo overrun error. datablockend data block sent/received. startbiterr start bit not detected on all data signals in wide bus mode. datacrcfail data packet crc failed. dataend data end (data counter is zero). datatimeout data timeout. txactive data transmission in progress. rxactive data reception in progress.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 445 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface ? the receive fifo refers to the receive lo gic and data buffer when rxactive is asserted (see section 16.6.3.15 ? receive fifo ? ). 16.6.3.14 transmit fifo data can be written to the transmit fifo through the apb interface once the sd card interface is enable d for transmission. the transmit fifo is accessible via 16 sequential addresses (see section 16.7.15 ? data fifo register ? ). the transmit fifo contains a data ou tput register that holds the data word pointed to by the read pointer. when the data path subunit has loaded its shift register, it increments the read pointer and drives new data out. if the transmit fifo is disabled, all status flags are deasserted. the data path subunit asserts txactive when it transmits data. table 342 lists the transmit fifo status flags. 16.6.3.15 receive fifo when the data path subunit receives a word of data, it drives data on the write data bus and asserts the write enable signal. this signal is synchronized to the pclk domain. the write pointer is increm ented after the write is completed, and the receive fifo control logic asserts rxwrdone, that then deasserts the write enable signal. on the read side, the content of the fifo word pointed to by the current value of the read pointer is driven on the read data bus. the read pointer is incremented when the apb bus interface asserts rxrdprtinc. if the receive fifo is disabled, all status flags are deasserted, and the read and write pointers are reset. the data path subunit asserts rxactive when it receives data. table 353 lists the receive fifo status flags. the receive fifo is accessible via 16 sequential addresses (see section 16.7.15 ? data fifo register ? ). if the receive fifo is disabled, all status flags are deasserted, and the read and write pointers are reset. the data path subunit asserts rxactive when it receives data. table 343 lists the receive fifo status flags. table 342. transmit fifo status flags flag description txfifofull set to high when all 16 transmit fifo words contain valid data. txfifoempty set to high when the transmit fifo does not contain valid data. txhalfempty set to high when 8 or more transmit fifo words are empty. this flag can be used as a dma request. txdataavlbl set to high when the transmit fifo contains valid data. this flag is the inverse of the txfifoempty flag. txunderrun set to high when an underrun error occurs. this flag is cleared by writing to the mciclear register. table 343. receive fifo status flags symbol description rxfifofull set to high when all 16 receive fifo words contain valid data. rxfifoempty set to high when the receive fifo does not contain valid data.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 446 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.6.3.16 apb interfaces the apb interface generates the interrupt and dma requests, and accesses the sd card interface registers and the data fifo. it consists of a data path, register decoder, and interrupt/dma logic. dm a is controlled by the general purpose dma controller, see that chapter for details. 16.6.3.17 interrupt logic the interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. a mask register is provided to allow selection of the conditions that will generate an interrupt. a status flag generat es the interrup t request if a corresponding mask flag is set. rxhalffull set to high when 8 or more receive fifo words contain valid data. this flag can be used as a dma request. rxdataavlbl set to high when the receive fifo is not empty. this flag is the inverse of the rxfifoempty flag. rxoverrun set to high when an overru n error occurs. this flag is cleared by writing to the mciclear register. table 343. receive fifo status flags symbol description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 447 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7 register description [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 16.7.1 power control register the pwr register controls an external power supply. power can be switched on and off, and adjust the output voltage. table 345 shows the bit assignment of the power register. the active level of the sd_pwr pin can be se lected by bit 3 of the scs register (see section 3.3.7.1 ? system controls and status register ? on page 44 for details). table 344. register overview: sd card interface (base address 0x400c 0000) name access address offset description reset value [1] table pwr r/w 0x000 power control register. 0 345 clock r/w 0x004 clock control register. 0 346 argument r/w 0x008 argument register. 0 347 command r/w 0x00c command register. 0 348 respcmd ro 0x010 response command register. 0 350 response0 ro 0x014 response register. 0 351 response1 ro 0x018 response register. 0 351 response2 ro 0x01c response register. 0 351 response3 ro 0x020 response register. 0 351 datatimer r/w 0x024 data timer. 0 353 datalength r/w 0x028 data length register. 0 354 datactrl r/w 0x02c data control register. 0 355 datacnt ro 0x030 data counter. 0 357 status ro 0x034 status register. 0 358 clear wo 0x038 clear register. - 359 mask0 r/w 003c interrupt 0 mask register. 0 360 fifocnt ro 0x4048 fifo counter. 0 361 fifo r/w 0x080 to 0x0bc data fifo register. 0 362 table 345: power control register (pwr - address 0x400c 0000) bit description bit symbol value description reset value 1:0 ctrl power control 0 0x0 power-off 0x1 reserved 0x2 power-up 0x3 power-on 5:2 - reserved. read value is undefined, only zero should be written. na 6 opendrain sd_cmd output control. 0 7 rod rod control. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 448 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface when the external power supply is switched on, the software first enters the power-up phase, and waits until the supply output is stable before moving to the power-on phase. during the power-up phase, sd_pwr is set high. the card bus outlets are disabled during both phases. note: after a data write, data cannot be writt en to this register for three mclk clock periods plus two pclk clock periods. 16.7.2 clock control register the clock register contro ls the sd_clk output. table 346 shows the bit assignment of the clock control register. while the sd card interface is in identification mode, the sd_clk frequency must be less than 400 khz. the clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. note: after a data write, data cannot be writt en to this register for three mclk clock periods plus two pclk clock periods. 16.7.3 argument register the argument register contains a 32 bit command argument, which is sent to a card as part of a command message. table 347 shows the bit assignment of the argument register. if a command contains an argument, it must be loaded into the argument register before writing a command to the command register. table 346: mci clock control register (clock - address 0x400c 0004) bit description bit symbol value description reset value 7:0 clkdiv bus clock period: sd_clk frequency = mclk / [2 ? (clkdiv+1)]. 0 8 enable enable sd card bus clock: 0 0 clock disabled. 1 clock enabled. 9 pwrsave disable sd_clk output when bus is idle: 0 0 always enabled. 1 clock enabled when bus is active. 10 bypass enable bypass of clock divide logic: 0 0 disable bypass. 1 enable bypass. mclk driven to card bus output (sd_clk). 11 widebus enable wide bus mode. 0 0 standard bus mode (only sd_dat[0] used). 1 wide bus mode (sd_dat[3:0] used) 31:12 - reserved. read value is undefined, only zero should be written. na table 347: mci argument register (argument - address 0x400c 0008) bit description bit symbol description reset value 31:0 cmdarg command argument 0x0000 0000
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 449 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7.4 command register the command register contains the command index and command type bits: ? the command index is sent to a card as part of a command message. ? the command type bits control the command path state machine (cpsm). writing 1 to the enable bit starts the command send operation, while clearing the bit disables the cpsm. table 348 shows the bit assignment of the command register. note: after a data write, data cannot be writt en to this register for three mclk clock periods plus two pclk clock periods. table 349 shows the response types. 16.7.5 command response register the respcommand register contains the command index field of the last command response received. ta b l e 3 4 8 shows the bit assignment of the respcommand register. if the command response transmission does not contain the command index field (long response), the respcmd field is unknown, although it must contain 111111 (the value of the reserved field from the response). 16.7.6 response registers the response0-3 registers contain the status of a card, which is part of the received response. table 351 shows the bit assignment of the response0-3 registers. table 348: mci command register (command - address 0x400c 000c) bit description bit symbol description reset value 5:0 cmdindex command index. 0 6 response if set, cpsm waits for a response. 0 7 longrsp if set, cpsm receives a 136 bit long response. 0 8 interrupt if set, cpsm disables command timer and waits for interrupt request. 0 9 pending if set, cpsm waits for cmdpend before it starts sending a command. 0 10 enable if set, cpsm is enabled. 0 31:11 - reserved. read value is undefined, only zero should be written. na table 349: command response types response long response description 0 0 no response, expect cmdsent flag. 0 1 no response, expect cmdsent flag. 1 0 short response, expect cmdrespend or cmdcrcfail flag. 1 1 long response, expect cmdrespend or cmdcrcfail flag. table 350: mci command respon se register (respcmd - address 0x400c 0010) bit description bit symbol description reset value 5:0 respcmd response command index 0 31:6 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 450 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface the card status size can be 32 or 127 bits, depending on the response type (see table 352 ). the most significant bit of the card status is received first. the response3 register lsbit is always 0. 16.7.7 data timer register the datatimer register contains the data timeout period, in card bus clock periods. table 353 shows the bit assignment of the datatimer register. a counter loads the value from the data timer register, and starts decrementing when the data path state machine (dpsm) enters the wa it_r or busy state. if the timer reaches 0 while the dpsm is in either of these states, the timeout status flag is set. a data transfer must be written to the data timer register and the data length register before being written to the data control register. 16.7.8 data length register the datalength register contains the number of data bytes to be transferred. the value is loaded into the data counter when data transfer starts. table 354 shows the bit assignment of the datalength register. for a block data transfer, the value in the data length register must be a multiple of the block size (see section 16.7.9 ? data control register ? ). to initiate a data transfer, write to the data timer register and the data length register before writing to the data control register. table 351: mci response registers (respon se[0:3] - addresses 0x400c 0014, 0x400c 0018, 0x400c 001c and 0x400c 0020) bit description bit symbol description reset value 31:0 status card status 0 table 352: response register type description short response long response response0 card status [31:0] card status [127:96] response1 unused card status [95:64] response2 unused card status [63:32] response3 unused card status [31:1] table 353: mci data timer register (datatimer - address 0x400c 0024) bit description bit symbol description reset value 31:0 datatime data timeout period. 0 table 354: mci data length register (datalength - address 0x400c 0028) bit description bit symbol description reset value 15:0 datalength data length value 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 451 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7.9 data control register the datactrl register controls the dpsm. table 355 shows the bit assignment of the datactrl register. note: after a data write, data cannot be writt en to this register for three mclk clock periods plus two pclk clock periods. data transfer starts if 1 is written to the e nable bit. depending on the direction bit, the dpsm moves to the wait_s or wait_r state. it is not necessary to clear the enable bit after the data transfer. blocksize controls the data block length if mode is 0, as shown in table 356 . 16.7.10 data counter register the datacnt register loads the value from the data length register (see section 16.7.8 ? data length register ? ) when the dpsm moves from the idle state to the wait_r or wait_s state. as data is transferred, the c ounter decrements the value until it reaches 0. the dpsm then moves to the idle state and the data status end flag is set. table 357 shows the bit assignment of the datacnt register. table 355: data control register (datactrl - address 0x400c 002c) bit description bit symbol value description reset value 0 enable data transfer enable. 0 1 direction data transfer direction 0 0 from controller to card. 1 from card to controller. 2 mode data transfer mode 0 0 block data transfer. 1 stream data transfer. 3 dmaenable enable dma 0 0 dma disabled. 1 dma enabled. 7:4 blocksize data block length 0 31:8 - reserved. read value is undefined, only zero should be written. na table 356: data block length block size block length 02 0 = 1 byte. 12 1 = 2 bytes. :: 11 2 11 = 2048 bytes. 12:15 reserved.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 452 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface note: this register should be read only when the data transfer is complete. 16.7.11 status register the status register is a read-only register. it contains two types of flag: ? static [10:0]: these remain asserted until they are clea red by writing to the clear register (see section 16.7.12 ? clear register ? ). ? dynamic [21:11]: these change state depending on the state of the underlying logic (for example, fifo full and empty flags are asserted and deasserted as data while written to the fifo). table 358 shows the bit assignment of the status register. table 357: mci data counter register (d atacnt - address 0x400c 0030) bit description bit symbol description reset value 15:0 datacount remaining data 0 31:16 - reserved. read value is undefined, only zero should be written. na table 358: mci status register (status - address 0x400c 0034) bit description bit symbol description reset value 0 cmdcrcfail command response received (crc check failed). 0 1 datacrcfail data block sent/received (crc check failed). 0 2 cmdtimeout command response timeout. 0 3 datatimeout data timeout. 0 4 txunderrun transmit fifo underrun error. 0 5 rxoverrun receive fifo overrun error. 0 6 cmdrespend command response received (crc check passed). 0 7 cmdsent command sent (no response required). 0 8 dataend data end (data counter is zero). 0 9 startbiterr start bit not detected on all data signals in wide bus mode. 0 10 datablockend data block sent/received (crc check passed). 0 11 cmdactive command transfer in progress. 0 12 txactive data transmit in progress. 0 13 rxactive data receive in progress. 0 14 txfifohalfempty transmit fifo half empty. 0 15 rxfifohalffull receive fifo half full. 0 16 txfifofull transmit fifo full. 0 17 rxfifofull receive fifo full. 0 18 txfifoempty transmit fifo empty. 0 19 rxfifoempty receive fifo empty. 0 20 txdataavlbl data available in transmit fifo. 0 21 rxdataavlbl data available in receive fifo. 0 31:22 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 453 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7.12 clear register the clear register is a write-only register. the corresponding static status flags can be cleared by writing a 1 to the co rresponding bit in the register. table 359 shows the bit assignment of the clear register. table 359: mci clear register (clear - address 0x400c 0038) bit description bit symbol description 0 cmdcrcfailclr clears cmdcrcfail flag. 1 datacrcfailclr clears datacrcfail flag. 2 cmdtimeoutclr clears cmdtimeout flag. 3 datatimeoutclr clears datatimeout flag. 4 txunderrunclr clears txunderrun flag. 5 rxoverrunclr clears rxoverrun flag. 6 cmdrespendclr clears cmdrespend flag. 7 cmdsentclr clears cmdsent flag. 8 dataendclr clears dataend flag. 9 startbiterrclr clears startbiterr flag. 10 datablockendclr clears datablockend flag. 31:11 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 454 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7.13 interrupt mask registers the interrupt mask registers deter mine which status flags generate an interrupt request by setting the corresponding bit to 1. table 360 shows the bit assignment of the maskx registers. 16.7.14 fifo counter register the fifocnt register contains the remaining number of words to be written to or read from the fifo. the fifo counter loads the value from the data length register (see section 16.7.8 ? data length register ? ) when the enable bit is set in the data control register. if the data length is not word aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word. ta b l e 3 6 1 shows the bit assignment of the fifocnt register. table 360: mci interrupt mask registers (mask0 - address 0x400c 003c) bit description bit symbol description reset value 0 mask0 mask cmdcrcfail flag. 0 1 mask1 mask datacrcfail flag. 0 2 mask2 mask cmdtimeout flag. 0 3 mask3 mask datatimeout flag. 0 4 mask4 mask txunderrun flag. 0 5 mask5 mask rxoverrun flag. 0 6 mask6 mask cmdrespend flag. 0 7 mask7 mask cmdsent flag. 0 8 mask8 mask dataend flag. 0 9 mask9 mask startbiterr flag. 0 10 mask10 mask datablockend flag. 0 11 mask11 mask cmdactive flag. 0 12 mask12 mask txactive flag. 0 13 mask13 mask rxactive flag. 0 14 mask14 mask txfifohalfempty flag. 0 15 mask15 mask rxfifohalffull flag. 0 16 mask16 mask txfifofull flag. 0 17 mask17 mask rxfifofull flag. 0 18 mask18 mask txfifoempty flag. 0 19 mask19 mask rxfifoempty flag. 0 20 mask20 mask txdataavlbl flag. 0 21 mask21 mask rxdataavlbl flag. 0 31:22 - reserved. read value is undefined, only zero should be written. na table 361: mci fifo counter register (fifocnt - address 0x400c 0048) bit description bit symbol description reset value 14:0 datacount remaining data 0 31:15 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 455 of 942 nxp semiconductors UM10562 chapter 16: lpc408x/407x sd card interface 16.7.15 data fifo register the receive and transmit fifos can be read or written as 32 bit wide registers. the fifos contain 16 entries on 16 sequential addresses. this allows the microprocessor to use its load and store multiple operands to read/write to the fifo. table 362 shows the bit assignment of the fifo register. table 362: mci data fifo register (fifo - address 0x400c 0080 to 0x400c 00bc) bit description bit symbol description reset value 31:0 data fifo data. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 456 of 942 17.1 basic configuration the uart1 peripheral is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bits pcuart1. remark: on reset, uart1 is enabled (pcuart1 = 1). 2. peripheral clock: uart1 operates from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . 3. baud rate: in register u1lcr ( ta b l e 3 7 3 ), set bit dlab =1. this enables access to registers dll ( table 367 ) and dlm ( table 368 ) for setting the baud rate. also, if needed, set the fractional baud rate in the fractional divider register ( table 380 ). 4. uart fifo: use bit fifo enable (bit 0) in register u1fcr ( table 372 ) to enable the fifos. 5. pins: select uart pins and pin modes through the in the relevant iocon registers ( section 7.4.1 ). remark: uart receive pins should not have pull-down resistors enabled. 6. interrupts: to enable uart interrupts set bit dlab =0 in register u1lcr ( ta b l e 3 7 3 ). this enables acce ss to u1ier ( table 369 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 7. dma: uart1 transmit and receive function s can operated with the gpdma controller (see table 692 ). 17.2 features ? full modem control handshaking available ? data sizes of 5, 6, 7, and 8 bits. ? parity generation and checking: odd, even mark, space or none. ? one or two stop bits. ? 16 byte receive and transmit fifos. ? built-in baud rate generator, including a fractional rate divider for great versatility. ? supports dma for both transmit and receive. ? auto-baud capability ? break generation and detection. ? multiprocessor addressing mode. ? rs-485/eia-485 support. UM10562 chapter 17: lpc408x/407x uart1 rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 457 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.3 architecture the architecture of the uart1 is shown below in the block diagram. the apb interface provides a communicatio ns link between the cpu or host and the uart1. the uart1 receiver block, u1rx, monitors the serial input line, rxd1, for valid input. the uart1 rx shift register (u1rsr) accepts valid characters via rxd1. after a valid character is assembled in the u1rsr, it is passed to the uart1 rx buffer register fifo to await access by the cpu or host via the generic host interface. the uart1 transmitter block, u1tx, accepts dat a written by the cpu or host and buffers the data in the uart1 tx holding register fifo (u1thr). the uart1 tx shift register (u1tsr) reads the data stored in the u1thr and assembles the data to transmit via the serial output pin, txd1. the uart1 baud rate generator block, u1brg, generates the timing enables used by the uart1 tx block. the u1brg clock input source is the apb clock (pclk). the main clock is divided down per the divisor specified in the u1dll and u1dlm registers. this divided down clock is the 16x oversample clock. the modem interface contains registers u1mcr and u1msr. th is interface is responsible for handshaking between a modem peripheral and the uart1. the interrupt interface contains registers u1ier and u1iir. the interrupt interface receives several one clock wide enables from the u1tx and u1rx blocks. status information from the u1tx and u1rx is stored in the u1lsr. control information for the u1tx and u1rx is stored in the u1lcr.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 458 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 fig 68. uart1 block diagram transmitter shift register transmitter holding register transmitter fifo transmitter receiver shift register receiver buffer register receiver fifo receiver tx_dma_req tx_dma_clr rx_dma_req rx_dma_clr baud rate generator fractional rate divider main divider (dlm, dll) modem control & status transmitter dma interface receiver dma interface pclk line control & status fifo control & status u1_txd u1_rxd u1_oe u1_cts u1_rts u1_dtr u1_dsr u1_ri u1_dcd rs485 & auto-baud uart1 interrupt interrupt control & status 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 459 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.4 pin description table 363: uart1 pin description pin type description u1_rxd input serial input. serial receive data. u1_txd output serial output. serial transmit data. u1_cts input clear to send. active low signal indicates if the external modem is ready to accept transmitted data via txd1 from the uart1. in normal operation of the modem interface (u1mcr[4] = 0), the complement value of this signal is stored in u1msr[4]. state change information is stored in u1msr[0] and is a source for a priority level 4 interrupt, if enabled (u1ier[3] = 1). clear to send. cts1 is an asynchronous, active low modem status signal. its condition can be checked by reading bit 4 (cts) of the modem status register. bit 0 (dcts) of the modem status register (msr) indicates that cts1 has changed states since the last read from the msr. if the modem status interrupt is enabled when cts1 changes levels and the auto-cts mode is not enabled, an interrupt is generated. cts1 is also used in the auto-cts mode to control the transmitter. u1_dcd input data carrier detect. active low signal indicates if the external modem has established a communication link with the uart1 and data may be exchanged. in normal operation of the modem interface (u1mcr[4]=0), the complement value of this signal is stored in u1msr[7]. state change information is stored in u1msr3 and is a source for a priority level 4 interrupt, if enabled (u1ier[3] = 1). u1_dsr input data set ready. active low signal indicates if the external modem is ready to establish a communications link with the uart1. in normal o peration of the modem interface (u1mcr[4] = 0), the complement value of this signal is stored in u1msr[5]. state change information is stored in u1msr[1] and is a source for a priority level 4 interrupt, if enabled (u1ier[3] = 1). u1_dtr output data terminal ready. active low signal indicates that the uart1 is ready to establish connection with external modem. the complement value of this signal is stored in u1mcr[0]. the dtr pin can also be used as an rs-485/eia-485 output enable signal. u1_ri input ring indicator. active low signal indicates that a telephone ringing signal has been detected by the modem. in normal operation of the modem interfac e (u1mcr[4] = 0), the complement value of this signal is stored in u1msr[6]. state change information is stored in u1msr[2] and is a source for a priority level 4 interrupt, if enabled (u1ier[3] = 1). u1_rts output request to send. active low signal indicates that the uart1 would like to transmit data to the external modem. the complement value of this signal is stored in u1mcr[1]. in auto-rts mode, rts1 is used to control the transmitter fifo threshold logic. request to send. rts1 is an active low signal informing the modem or data set that the uart is ready to receive data. rts1 is set to the active (low) level by setting the rts modem control register bit and is set to the inactive (high) level either as a result of a system reset or during loop-back mode operations or by clearing bit 1 (rts) of the mcr. in the auto -rts mode, rts1 is controlled by the transmitter fifo threshold logic. the rts pin can also be used as an rs-485/eia-485 output enable signal.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 460 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5 register description the divisor latch access bit (dlab) is contai ned in u1lcr[7] and enables access to the divisor latches. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 364: register overview: uart1 (base address 0x4001 0000) name access address offset description reset value [1] table rbr ro 0x000 dlab =0. receiver buffer register. contains the next received character to be read. na 365 thr wo 0x000 dlab =0. transmit holding register. the next character to be transmitted is written here. na 366 dll r/w 0x000 dlab =1. divisor latch lsb. least significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider. 0x01 367 dlm r/w 0x004 dlab =1. divisor latch msb. most significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider. 0 368 ier r/w 0x004 dlab =0. interrupt enable register. contains individual interrupt enable bits for the 7 potential uart1 interrupts. 0 369 iir ro 0x008 interrupt id register. identifies which interrupt(s) are pending. 0x01 370 fcr wo 0x008 fifo control register. controls uart1 fifo usage and modes. 0 372 lcr r/w 0x00c line control register. contains controls for frame formatting and break generation. 0 373 mcr r/w 0x010 modem control register. contains controls for flow control handshaking and loopback mode. 0 374 lsr ro 0x014 line status register. contains flags for transmit and receive status, including line errors. 0x60 376 msr ro 0x018 modem status register. contains handshake signal status flags. 0 377 scr r/w 0x01c scratch pad register. 8-bit temporary storage for software. 0 378 acr r/w 0x020 auto-baud control register. contains controls for the auto-baud feature. 0 379 fdr r/w 0x028 fractional divider register. generates a clock input for the baud rate divider. 0x10 380 ter r/w 0x030 transmit enable register. turns off uart transmitter for use with software flow control. 0x80 382 rs485ctrl r/w 0x04c rs-485/eia-485 control. c ontains controls to configure various aspects of rs-485/eia-485 modes. 0 383 rsadrmatch r/w 0x050 rs-485/eia-485 addre ss match. contains the address match value for rs-485/eia-485 mode. 0 384 rs485dly r/w 0x054 rs-485/eia-485 direction control delay. 0 385
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 461 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.1 uart1 receiver buffer register the u1rbr is the top byte of the uart1 rx fifo. the top byte of the rx fifo contains the oldest character received and can be read via the bus interface. the lsb (bit 0) represents the ?oldest? received data bit. if the character received is less than 8 bits, the unused msbs are padded with zeroes. the divisor latch access bit (dlab) in u1l cr must be zero in order to access the u1rbr. the u1rbr is always read-only. since pe, fe and bi bits correspond to the by te sitting on the top of the rbr fifo (i.e. the one that will be read in the next read from the rbr), t he right appr oach for fetching the valid pair of received byte and its status bits is first to read the content of the u1lsr register, and then to read a byte from the u1rbr. 17.5.2 uart1 transmitter holding register the write-only u1thr is the top byte of the uart1 tx fifo. the top byte is the newest character in the tx fifo and can be written via the bus interface. the lsb represents the first bit to transmit. the divisor latch access bit (dlab) in u1l cr must be zero in order to access the u1thr. the u1thr is write-only. table 365: uart1 receiver buffer register when dlab = 0 (rbr - address 0x4001 0000 ) bit description bit symbol description reset value 7:0 rbr the uart1 receiver buffer register contains th e oldest received byte in the uart1 rx fifo. undefined 31:8 - reserved, the value read from a reserved bit is not defined. na table 366: uart1 transmitter holding register when dlab = 0 (thr - address 0x4001 0000 ) bit description bit symbol description 7:0 thr writing to the uart1 transmit holding register c auses the data to be stored in the uart1 transmit fifo. the byte will be sent when it reaches the bottom of the fifo and the transmitter is available. 31:8 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 462 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.3 uart1 divisor latch lsb and msb registers the uart1 divisor latch is part of the uart 1 baud rate generator and holds the value used, along with the fractional divider, to divide the apb clock (pclk) in order to produce the baud rate clock, which must be 16x the desired baud rate. the u1dll and u1dlm registers together form a 16 -bit divisor where u1dll contains the lower 8 bits of the divisor and u1dlm contains the higher 8 bits of the divisor. a 0x0000 value is treated like a 0x0001 value as division by zero is not allowed.the divisor latch access bit (dlab) in u1lcr must be one in order to access th e uart1 divisor latches. details on how to select the right value for u1dll and u1dlm can be found later in this chapter, see section 17.5.16 . table 367: uart1 divisor latch lsb register when dlab = 1 (dll - address 0x4001 0000 ) bit description bit symbol description reset value 7:0 dllsb the uart1 divisor latch lsb register, along with the u1dlm register, determines the baud rate of the uart1. 0x01 31:8 - reserved. read value is undefined, only zero should be written. na table 368: uart1 divisor latch msb register when dlab = 1 (dlm - address 0x4001 0004 ) bit description bit symbol description reset value 7:0 dlmsb the uart1 divisor latch msb register, along with the u1dll register, determines the baud rate of the uart1. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 463 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.4 uart1 interrupt enable register the u1ier is used to enable th e four uart1 interrupt sources. table 369: uart1 interrupt enable register when dlab = 0 (ier - address 0x4001 0004 ) bit description bit symbol value description reset value 0 rbrie rbr interrupt enable. enables the receive data available interrupt for uart1. it also controls the character receive time-out interrupt. 0 0 disable the rda interrupts. 1 enable the rda interrupts. 1 threie thre interrupt enable. enables the thre interrupt for uart1. the status of this interrupt can be read from lsr[5]. 0 0 disable the thre interrupts. 1 enable the thre interrupts. 2 rxie rx line interrupt enable. enables the uart1 rx line status interrupts. the status of this interrupt can be read from lsr[4:1]. 0 0 disable the rx line status interrupts. 1 enable the rx line status interrupts. 3 msie modem status interrupt enable. enables the modem interrupt. the status of this interrupt can be read from msr[3:0]. 0 0 disable the modem interrupt. 1 enable the modem interrupt. 6:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7 ctsie cts interrupt enable. if auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a cts1 signal transition. if auto-cts mode is disabled a cts1 transition will generate an interrupt if modem status in terrupt enable (ier[3]) is set. in normal operation a cts1 signal transition will generate a modem status interrupt unless the interrupt has been disabled by clearing the ier[3] bit in the ier register. in auto-cts mode a transition on the cts1 bit will trigger an interrupt only if both the ier[3] and ier[7] bits are set. 0 0 disable the cts interrupt. 1 enable the cts interrupt. 8 abeoie enables the end of auto-baud interrupt. 0 0 disable end of auto-baud interrupt. 1 enable end of auto-baud interrupt. 9 abtoie enables the auto-baud time-out interrupt. 0 0 disable auto-baud time-out interrupt. 1 enable auto-baud time-out interrupt. 31:10 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 464 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.5 uart1 interrupt identification register the u1iir provides a status code that denot es the priority and source of a pending interrupt. the interrupts are frozen during an u1 iir access. if an interrupt occurs during an u1iir access, the interrupt is recorded for the next u1iir access. bit u1iir[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. the auto-baud interrupt conditions are cleared by setting the corresponding clear bits in the auto-baud control register. if the intstatus bit is 1 no interr upt is pending and the intid bits will be zero. if the intstatus is 0, a non auto-baud interrupt is pending in which case the intid bits identify the type of interrupt and handling as described in table 371 . given the status of u1iir[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. the u1iir must be read in order to clear the interrupt prior to exiting the interrupt service routine. the uart1 rls interrupt (u1iir[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the uart1rx input: overrun error (oe), parity error (pe), framing error (fe) and break interrupt (bi). the uart1 rx error condition that set the interrupt can be observed via u1lsr[4:1]. the interrupt is cleared upon an u1lsr read. table 370: uart1 interrupt identification register (iir - address 0x4001 0008) bit description bit symbol value description reset value 0 intstatus interrupt status. note that iir[0] is active low. the pending interrupt can be determined by evaluating iir[3:1]. 1 0 at least one interrupt is pending. 1 no interrupt is pending. 3:1 intid interrupt identification. ier[3:1] identifies an interrupt corresponding to the uart1 rx or tx fifo. all other combinations of ier[3:1] not listed below are reserved (100,101,111). 0 0x3 1 - receive line status (rls). 0x2 2a - receive data available (rda). 0x6 2b - character time-out indicator (cti). 0x1 3 - thre interrupt. 0x0 4 - modem interrupt. 5:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7:6 fifoenable copies of fcr[0]. 0 8 abeoint end of auto-baud inte rrupt. true if auto-baud has finished successfully and interrupt is enabled. 0 9 abtoint auto-baud time-out interrupt. true if auto-baud has timed out and interrupt is enabled. 0 31:10 - reserved, the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 465 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 the uart1 rda interrupt (u1iir[3:1] = 010) shar es the second level priority with the cti interrupt (u1iir[3:1] = 110). the rda is acti vated when the uart1 rx fifo reaches the trigger level defined in u1fcr7:6 and is reset when the uart1 rx fifo depth falls below the trigger level. when the rda interrupt goes active, the cpu can read a block of data defined by the trigger level. the cti interrupt (u1iir[3:1] = 11 0) is a second level interrup t and is set when the uart1 rx fifo contains at least one character and no uart1 rx fifo activity has occurred in 3.5 to 4.5 character times. an y uart1 rx fifo activity (read or write of uart1 rsr) will clear the interrupt. this interrupt is intended to flush the uart1 rbr after a message has been received that is not a multiple of the tr igger level size. for example, if a peripheral wished to send a 105 character message an d the trigger level was 10 characters, the cpu would receive 10 rda interrupts resulting in the transfer of 100 characters and 1 to 5 cti interrupts (depending on the service routine) resulting in the tran sfer of the remaining 5 characters. [1] values "0000", ?0011?, ?0101?, ?0111?, ?1000?, ?100 1?, ?1010?, ?1011?,?1101?,?1110?,?1111? are reserved. [2] for details see section 17.5.10 ? uart1 line status register ? [3] for details see section 17.5.1 ? uart1 receiver buffer register ? [4] for details see section 17.5.5 ? uart1 interrupt identification register ? and section 17.5.2 ? uart1 transmitter holding register ? the uart1 thre interrupt (u1i ir[3:1] = 001) is a third leve l interrupt and is activated when the uart1 thr fifo is empty provided certain initialization conditions have been met. these initialization conditions are inten ded to give the uart1 thr fifo a chance to fill up with data to eliminate many thre interr upts from occurring at system start-up. the initialization conditions implement a one c haracter delay minus the stop bit whenever thre = 1 and there have not been at least two characters in the u1thr at one time table 371: uart1 interrupt handling u1iir[3:0] value [1] priority interrupt type interrupt source interrupt reset 0001 - none none - 0110 highest rx line status / error oe [2] or pe [2] or fe [2] or bi [2] u1lsr read [2] 0100 second rx data available rx data available or trigger level reached in fifo (u1fcr0=1) u1rbr read [3] or uart1 fifo drops below trigger level 1100 second character time-out indication minimum of one character in the rx fifo and no character input or removed during a time period depending on how many characters are in fifo and what the trigger level is set at (3.5 to 4.5 character times). the exact time will be: [(word length) ? 7 - 2] ? 8 + [(trigger level - number of characters) ? 8 + 1] rclks u1rbr read [3] 0010 third thre thre [2] u1iir read [4] (if source of interrupt) or thr write 0000 fourth modem status cts or dsr or ri or dcd msr read
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 466 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 since the last thre = 1 event. this delay is pr ovided to give the cpu time to write data to u1thr without a thre interr upt to decode and service. a thre interrupt is set immediately if the uart1 thr fifo has held two or more characters at one time and currently, the u1thr is empty. the thre interrupt is reset when a u1thr write occurs or a read of the u1iir occurs and the thre is the highest interr upt (u1iir[3:1] = 001). it is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, dcd, dsr or cts. in addition, a low to high transition on modem input ri will gene rate a modem interrupt. the source of the modem interrupt can be determined by examining u1msr[3:0]. a u1 msr read will clear the modem interrupt.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 467 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.6 uart1 fifo control register the write-only u1fcr controls the oper ation of the uart1 rx and tx fifos. 17.5.6.1 dma operation the user can optionally operate the uart tr ansmit and/or receive using dma. the dma mode is determined by the dma mode select bit in the fcr register. this bit only has an affect when the fifos are enabled via the fifo enable bit in the fcr register. uart receiver dma in dma mode, the receiver dm a request is asserted on the event of the receiver fifo level becoming equal to or greater than trigger level, or if a character timeout occurs. see the description of the rx trigger level above. the receiver dma request is cleared by the dma controller. table 372: uart1 fifo control register (fcr - address 0x4001 0008) bit description bit symbol value description reset value 0 fifoen fifo enable. 0 0 must not be used in the application. 1 active high enable for both uart1 rx and tx fifos and fcr[7:1] access. this bit must be set for pro per uart1 operation. any transiti on on this bit will automatically clear the uart1 fifos. 1 rxfifores rx fifo reset. 0 0 no impact on either of uart1 fifos. 1 writing a logic 1 to fcr[1] will clear all bytes in uart1 rx fifo, reset the pointer logic. this bit is self-clearing. 2 txfifores tx fifo reset. 0 0 no impact on either of uart1 fifos. 1 writing a logic 1 to fcr[2] will clear all bytes in uart1 tx fifo, reset the pointer logic. this bit is self-clearing. 3 dmamode dma mode select. when the fifo enable bit (bit 0 of this register) is set, this bit selects the dma mode. see section 17.5.6.1 . 0 5:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na 7:6 rxtriglvl rx trigger level. these two bits determine how many receiver uart1 fifo characters must be written before an interrupt is activated. 0 0x0 trigger level 0 (1 character or 0x01). 0x1 trigger level 1 (4 characters or 0x04). 0x2 trigger level 2 (8 characters or 0x08). 0x3 trigger level 3 (14 characters or 0x0e). 31:8 - reserved, user software should not write ones to reserved bits. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 468 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 uart transmitter dma in dma mode, the transmitter dma request is asserted on the event of the transmitter fifo transitioning to not full. the transmitter dma request is cleared by the dma controller.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 469 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.7 uart1 line control register the u1lcr determines the format of the data character that is to be transmitted or received. table 373: uart1 line control register (lcr - address 0x4001 000c) bit description bit symbol value description reset value 1:0 wls word length select. 0 0x0 5-bit character length. 0x1 6-bit character length. 0x2 7-bit character length. 0x3 8-bit character length. 2 sbs stop bit select. 0 0 1 stop bit. 1 2 stop bits (1.5 if lcr[1:0]=00). 3 pe parity enable. 0 0 disable parity generation and checking. 1 enable parity generation and checking. 5:4 ps parity select. 0 0x0 odd parity. number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 even parity. number of 1s in the transmitted character and the attached parity bit will be even. 0x2 forced "1" stick parity. 0x3 forced "0" stick parity. 6 bc break control. 0 0 disable break transmission. 1 enable break transmission. output pin uart1 txd is forced to logic 0 when lcr[6] is active high. 7 dlab divisor latch access bit (dlab) 0 0 disable access to divisor latches. 1 enable access to divisor latches. 31:8 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 470 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.8 uart1 modem control register the u1mcr enables the modem loopback mode and controls the modem output signals. 17.5.9 auto-flow control if auto-rts mode is enabled the uart1?s re ceiver fifo hardware controls the rts1 output of the uart1. if the auto-cts mode is enabled the uart1?s u1tsr hardware will only start transmitting if the cts1 input signal is asserted. 17.5.9.1 auto-rts the auto-rts function is enabled by setting th e rtsen bit. auto-rts data flow control originates in the u1rbr module and is linke d to the programmed receiver fifo trigger level. if auto-rts is enabled, th e data-flow is controlled as follows: table 374: uart1 modem control register (mcr - address 0x4001 0010) bit description bit symbol value description reset value 0 dtrctrl - dtr control. source for modem output pin, dtr. this bit reads as 0 when modem loopback mode is active. 0 1 rtsctrl - rts control. source for modem output pin rts. this bit reads as 0 when modem loopback mode is active. 0 3:2 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0 4 lms loopback mode select. the modem loopback mode provides a mec hanism to perform diagnostic loopback testing. serial data from the transmitter is connected internally to serial input of the receiver. input pin, rxd1, has no effect on loopback and output pin, txd1 is held in marking state. the 4 modem inputs (cts, dsr, ri and dcd) are disconnected externally. externally, the modem outputs (rts , dtr) are set inactive. internally, the 4 modem outputs are connected to the 4 modem inputs. as a result of these connections, the upper 4 bits of the msr will be driven by the lower 4 bits of the mcr rather than the 4 modem inputs in normal mode. this permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of mcr. 0 0 disable modem loopback mode. 1 enable modem loopback mode. 5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0 6 rtsen rts enable. 0 0 disable auto-rts flow control. 1 enable auto-rts flow control. 7 ctsen cts enable. 0 0 disable auto-cts flow control. 1 enable auto-cts flow control. 31:8 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 471 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 when the receiver fifo level reaches the programmed trigger level, rts1 is de-asserted (to a high value). it is possible that the sending uart sends an additional byte after the trigger level is reached (assuming the sending uart has another byte to send) because it might not recognize the de-assertion of rts1 until after it has begun sending the additional byte. rts1 is automatically reasse rted (to a low value) once the receiver fifo has reached the previous trigger level. the re-assertion of rts1 signals to the sending uart to continue transmitting data. if auto-rts mode is disabled, the rtsen bit co ntrols the rts1 output of the uart1. if auto-rts mode is enabled, hardware controls the rts1 output, and the actual value of rts1 will be copied in the rts control bit of the uart1. as long as auto-rts is enabled, the value of the rts control bit is read-only for software. example: suppose the uart1 operating in ?550 mode has trigger level in u1fcr set to 0x2 then if auto-rts is enabled the uart1 w ill de-assert the rts1 ou tput as soon as the receive fifo contains 8 bytes ( table 372 on page 467 ). the rts1 output will be reasserted as soon as the receive fifo hits the previous trigger level: 4 bytes. 17.5.9.2 auto-cts the auto-cts function is enabled by setting the ctsen bit. if auto-cts is enabled the transmitter circuitry in the u1tsr module ch ecks cts1 input before sending the next data byte. when cts1 is active (low), the transmitter sends the next byte. to stop the transmitter from sending the following byte, cts1 must be released before the middle of the last stop bit that is currently being s ent. in auto-cts mode a change of the cts1 signal does not trigger a modem status interrup t unless the cts interrupt enable bit is set, delta cts bit in the u1 msr will be set though. table 375 lists the conditions for generating a modem status interrupt. fig 69. auto-rts functional timing start byte n stop start bits0..7 stop start bits0..7 stop n-1 n n-1 n-1 n-2 n-2 m+2 m+1 m m-1 uart1 rx rts1 pin uart1 rx fifo level uart1 rx fifo read ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ table 375: modem status interrupt generation enable modem status interrupt (u1er[3]) ctsen (u1mcr[7]) cts interrupt enable (u1ier[7]) delta cts (u1msr[0]) delta dcd or trailing edge ri or delta dsr (u1msr[3] or u1msr[2] or u1msr[1]) modem status interrupt 0xxx x n o 10x0 0 n o 10x1 x y e s 10xx 1 y e s 110x 0 n o 110x 1 y e s
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 472 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 the auto-cts function reduces interrupts to the host system. when flow control is enabled, a cts1 state change does not trigger host interrupts because the device automatically controls its own transmitter. without auto-cts, the transmitter sends any data present in the transmit fifo and a receiver overrun error can result. figure 70 illustrates the auto-cts functional timing. while starting transmission of the initial character the cts1 signal is asserted. transmission will stall as soon as the pending transmission has completed. the uart will continue transmitting a 1 bit as long as cts1 is de-asserted (high). as soon as cts1 gets de-asserted transmission resumes and a start bit is sent followed by the data bits of the next character. 1110 0 n o 1111 x y e s 111x 1 y e s table 375: modem status interrupt generation enable modem status interrupt (u1er[3]) ctsen (u1mcr[7]) cts interrupt enable (u1ier[7]) delta cts (u1msr[0]) delta dcd or trailing edge ri or delta dsr (u1msr[3] or u1msr[2] or u1msr[1]) modem status interrupt fig 70. auto-cts functional timing start bits0..7 start bits0..7 stop start bits0..7 stop uart1 tx cts1 pin ~ ~ ~ ~ ~ ~ ~ ~ stop
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 473 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.10 uart1 line status register the u1lsr is a read-only register that prov ides status information on the uart1 tx and rx blocks. table 376: uart1 line status register (lsr - address 0x4001 0014) bit description bit symbol value description reset value 0 rdr receiver data ready. lsr[0] is set when the rbr holds an unread character and is cleared when the uart1 rbr fifo is empty. 0 0 the uart1 receiver fifo is empty. 1 the uart1 receiver fifo is not empty. 1 oe overrun error. the overrun error condition is set as soon as it occurs. an lsr read clears lsr[1]. lsr[1] is set when uart1 rsr has a new character a ssembled and the uart1 rbr fifo is full. in this case, the uart1 rbr fi fo will not be overwritten a nd the character in the uart1 rsr will be lost. 0 0 overrun error status is inactive. 1 overrun error status is active. 2 pe parity error. when the parity bit of a received character is in the wrong state, a parity error occurs. an lsr read clears lsr[2]. time of parity error detection is dependent on fcr[0]. note: a parity error is associated with the character at the top of the uart1 rbr fifo. 0 0 parity error status is inactive. 1 parity error status is active. 3 fe framing error. when the stop bit of a received character is a logic 0, a framing error occurs. an lsr read clears lsr[3]. the time of the framing error detection is dependent on fcr0. upon detection of a framing error, the rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. however, it cannot be assumed that the next received byte will be correct even if there is no framing error. note: a framing error is associated with the character at the top of the uart1 rbr fifo. 0 0 framing error status is inactive. 1 framing error status is active. 4 bi break interrupt. when rxd1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. once the break condition has been detected, the receiver goes idle until rxd1 goes to marking state (all ones). an lsr read clears this status bit. the time of break detection is dependent on fcr[0]. note: the break interrupt is associated with the character at the top of the uart1 rbr fifo. 0 0 break interrupt status is inactive. 1 break interrupt status is active. 5 thre transmitter holding register empty. thre is set immediately upon detection of an empty uart1 thr and is cleared on a thr write. 1 0 thr contains valid data. 1 thr is empty.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 474 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.11 uart1 modem status register the u1msr is a read-only register that provides status information on the modem input signals. u1msr[3:0] is cleared on u1msr read. note that modem signals have no direct effect on uart1 operation, they facilit ate software implementation of modem signal operations. 6 temt transmitter empty. temt is set when both thr and tsr are empty; temt is cleared when either the tsr or the thr contain valid data. 1 0 thr and/or the tsr contains valid data. 1 thr and the tsr are empty. 7 rxfe error in rx fifo. lsr[7] is set when a character with a rx error such as framing error, parity error or break interrupt, is loaded into the rbr. this bit is cleared when the lsr register is read and there are no subsequent errors in the uart1 fifo. 0 0 rbr contains no uart1 rx errors or fcr[0]=0. 1 uart1 rbr contains at least one uart1 rx error. 31:8 - reserved, the value read from a reserved bit is not defined. na table 376: uart1 line status register (lsr - address 0x4001 0014) bit description bit symbol value description reset value table 377: uart1 modem status register (msr - address 0x4001 0018) bit description bit symbol value description reset value 0 dcts delta cts. set upon state change of input cts. cleared on an msr read. 0 0 no change detected on modem input, cts. 1 state change detected on modem input, cts. 1 ddsr delta dsr. set upon state change of input dsr. cleared on an msr read. 0 0 no change detected on modem input, dsr. 1 state change detected on modem input, dsr. 2 teri trailing edge ri. set upon low to high transition of input ri. cleared on an msr read. 0 0 no change detected on modem input, ri. 1 low-to-high transition detected on ri. 3 ddcd delta dcd. set upon state change of input dcd. cleared on an msr read. 0 0 no change detected on modem input, dcd. 1 state change detected on modem input, dcd. 4 cts - clear to send state. complement of input signal cts. this bit is connected to mcr[1] in modem loopback mode. 0 5 dsr - data set ready state. complement of input signal dsr. this bit is connected to mcr[0] in modem loopback mode. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 475 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 6 ri - ring indicator state. complement of input ri. this bit is connected to mcr[2] in modem loopback mode. 0 7 dcd - data carrier detect state. complement of input dcd. this bit is connected to mcr[3] in modem loopback mode. 0 31:8 - - reserved, the value read from a reserved bit is not defined. na table 377: uart1 modem status register (msr - address 0x4001 0018) bit description bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 476 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.12 uart1 scratch pad register the u1scr has no effect on the uart1 operat ion. this register can be written and/or read at user?s discretion. there is no provision in the interrup t interface that would indicate to the host that a read or write of the u1scr has occurred. 17.5.13 uart1 auto-ba ud control register the uart1 auto-baud control register (u1acr) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user?s discretion. table 378: uart1 scratch pad register (scr - address 0x4001 0014) bit description bit symbol description reset value 7:0 pad a readable, writable byte. 0 31:8 - reserved. read value is undefined, only zero should be written. na table 379: auto-baud control register ( acr - address 0x4001 0020) bit description bit symbol value description reset value 0 start auto-baud start bit. this bit is automatically cleared after auto-baud completion. 0 0 auto-baud stop (auto-baud is not running). 1 auto-baud start (auto-baud is runnin g). auto-baud run bit. this bit is automatically cleared after auto-baud completion. 1 mode auto-baud mode select bit. 0 0 mode 0. 1 mode 1. 2 autorestart auto-baud restart bit. 0 0no restart 1 restart in case of time-out (counter restarts at next uart1 rx falling edge) 7:3 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0 8 abeointclr end of auto-baud interrupt clear bit (write-only). 0 0 writing a 0 has no impact. 1 writing a 1 will clear the corre sponding interrupt in the iir. 9 abtointclr auto-baud time-out interrupt clear bit (write-only). 0 0 writing a 0 has no impact. 1 writing a 1 will clear the corre sponding interrupt in the iir. 31:10 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 477 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.14 auto-baud the uart1 auto-baud function can be used to measure the incoming baud rate based on the ?at? protocol (hayes co mmand). if enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers u1dlm and u1dll accordingly. remark: the fractional rate divider is not conn ected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. auto-baud is started by setting the u1acr st art bit. auto-baud can be stopped by clearing the u1acr start bit. the start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pendi ng/finished). two auto-baud measuring modes are availa ble which can be selected by the u1acr mode bit. in mode 0 the baud rate is meas ured on two subsequent falling edges of the uart1 rx pin (the falling edge of the start bit and the falling e dge of the least significant bit). in mode 1 the baud rate is measured betw een the falling edge and the subsequent rising edge of the uart1 rx pin (the length of the start bit). the u1acr autorestart bit can be used to automatically re start baud rate measurement if a time-out occurs (the rate measurement co unter overflows). if this bit is set the rate measurement will restart at the next falling edge of the uart1 rx pin. the auto-baud function can generate two interrupts. ? the u1iir abtoint inte rrupt will get set if the interrup t is enabled (u1ier abtointen is set and the auto-baud rate measurement counter overflows). ? the u1iir abeoint interr upt will get set if the interrupt is enabled (u1ier abeointen is set and the auto-baud has completed successfully). the auto-baud interrupts have to be cleared by setting the corresponding u1acr abtointclr and abeointen bits. typically the fractional baud rate generator is disabled (divaddval = 0) during auto-baud. however, if the fractional baud rate generator is enabled (divaddval > 0), it is going to impact the measuring of uart1 rx pin baud rate, but the value of the u1fdr register is not going to be modified after rate measurement. also, when auto-baud is used, any write to u1dlm and u1dll registers should be done before u1acr register write. the minimum and the maximum baud rates su pported by uart1 ar e function of pclk, number of data bits, stop bits and parity bits. (1) ratemin 2p ? clk 16 2 15 ? ------------------------ - uart 1 baudrate pclk 16 2 databits paritybits stopbits ++ + ?? ? ------------------------------------------------------------------------------------------------------------ ?? ratemax ==
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 478 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.15 auto-baud modes when the software is expecting an ?at? co mmand, it configures the uart1 with the expected character format and sets the u1acr start bit. the initial values in the divisor latches u1dlm and u1dlm don?t care. because of the ?a? or ?a? ascii coding (?a" = 0x41, ?a? = 0x61), the uart1 rx pin sensed start bit and the lsb of the expected character are delim ited by two falling edges. when th e u1acr start bit is set, the auto-baud protocol will ex ecute the follo wing phases: 1. on u1acr start bit setting, the baud ra te measurement counter is reset and the uart1 u1rsr is reset. the u1rsr baud rate is switch to the highest rate. 2. a falling edge on uart1 rx pi n triggers the beginning of the start bit. the rate measuring counter will start counting pc lk cycles optionally pre-scaled by the fractional baud rate generator. 3. during the receipt of the start bit, 16 pu lses are generated on the rsr baud input with the frequency of the (fractional baud rate pre-scaled) uart1 input clock, guaranteeing the start bit is stored in the u1rsr. 4. during the receipt of the start bit (and the character lsb for mode = 0) the rate counter will continue incrementing with the pre-scaled uart1 input clock (pclk). 5. if mode = 0 then the rate counter will stop on next falling edge of t he uart1 rx pin. if mode = 1 then the rate counte r will stop on the next risi ng edge of the uart1 rx pin. 6. the rate counter is loaded into u1dlm/u1dll and the baud rate will be switched to normal operation. after setting the u1dlm/u1dll the end of auto-baud interrupt u1iir abeoint will be set, if enabled. th e u1rsr will now cont inue receiving the remaining bits of the ?a/a? character.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 479 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 a. mode 0 (start bit and lsb are used for auto-baud) b. mode 1 (only start bit is used for auto-baud) fig 71. auto-baud a) mode 0 and b) mode 1 waveform uart1 rx start bit lsb of 'a' or 'a' u1acr start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'a' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate uart1 rx start bit lsb of 'a' or 'a' rate counter 'a' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop u1acr start 16 cycles 16xbaud_rate
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 480 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.16 uart1 fractional divider register the uart1 fractional divider register (u1fdr) controls the clock pre-scaler for the baud rate generation and can be read and writte n at the user?s discretion. this pre-scaler takes the apb clock and generates an output clock according to th e specified fractional requirements. important: if the fractional divider is active (divaddval > 0) and dlm = 0, the value of the dll register must be greater than 2. this register controls the clo ck pre-scaler for the baud rate generation. the reset value of the register keeps the fractio nal capabilities of uart1 disa bled making sure that uart1 is fully software and hardware compatible with uarts not equipped with this feature. uart1 baud rate can be calculated as (n = 1): (2) where pclk is the peripheral clock, u1dlm and u1dll are the standard uart1 baud rate divider registers, and divaddval and mulval are uart1 fractional baud rate generator specific parameters. the value of mulval and divaddval should comply to the following conditions: 1. 1 ? mulval ? 15 2. 0 ? divaddval ? 14 3. divaddval < mulval the value of the u1fdr should not be modified while transmitting/receiving data or data may be lost or corrupted. if the u1fdr register value does not comply to these two requests, then the fractional divider output is undefined. if divaddval is zero then the fractional divider is disabled, and the clock will not be divided. table 380: uart1 fractional divider register (fdr - address 0x4001 0028) bit description bit function value description reset value 3:0 divaddval 0 baud rate generation pre-scaler divisor value. if this field is 0, fractional baud rate generator w ill not impact the uart1 baud rate. 0 7:4 mulval 1 baud rate pre-scaler multiplier value. this field must be greater or equal 1 for uart1 to operate properly, regardless of whether the fractional baud rate generator is used or not. 1 31:8 - reserved. read value is undefined, only zero should be written. 0 uart1 baudrate pclk 16 256 u1dlm ? u1dll + ?? ? 1 divaddval mulval ----------------------------- + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------------- =
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 481 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.16.1 baud rate calculation uart1 can operate with or without using the frac tional divider. in real-life applications it is likely that the desired baud rate can be achieved using several different fractional divider settings. the fo llowing algorithm illustra tes one way of finding a set of dlm, dll, mulval, and divaddval values. such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. fig 72. algorithm for setting uart dividers pclk, br calculating uart baudrate (br) dl est = pclk/(16 x br) dl est is an integer? divaddval = 0 mulval = 1 tr u e fr est = 1.5 dl est = int(pclk/(16 x br x fr est )) 1.1 < fr est < 1.9? pick another fr est from the range [1.1, 1.9] fr est = pclk/(16 x br x dl est ) divaddval = table(fr est ) mulval = table(fr est ) dlm = dl est [15:8] dll = dl est [7:0] end false tr u e false
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 482 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.16.1.1 example 1: pclk = 14.7456 mhz, br = 9600 according to the provided algorithm dl est = pclk/(16 x br) = 14.7456 mhz / (16 x 9600) = 96. since this dl est is an integer number, divaddval = 0, mulval = 1, dlm = 0, and dll = 96. 17.5.16.1.2 example 2: pclk = 12 mhz, br = 115200 according to the provided algorithm dl est = pclk/(16 x br) = 12 mhz / (16 x 115200) = 6.51. this dl est is not an integer number and the next step is to estimate the fr parameter. using an initial estimate of fr est = 1.5 a new dl est = 4 is calculated and fr est is recalculated as fr est = 1.628. since frest = 1.628 is within the specified range of 1.1 and 1.9, divaddval and mulval values can be obtained from the attached look-up table. the closest value for frest = 1.628 in the look-up table 381 is fr = 1.625. it is equivalent to divaddval = 5 and mulval = 8. based on these findings, the suggested uart setup would be: dlm = 0, dll = 4, divaddval = 5, and mulval = 8. according to equation 2 the uart rate is 115384. this rate has a relative error of 0.16% from the originally specified 115200. table 381. fractional divider setting look-up table fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11 1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6 1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13 1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7 1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15 1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8 1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9 1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10 1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11 1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12 1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13 1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14 1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 483 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.17 uart1 transmit enable register in addition to being equipped with full hardware flow control (auto-cts and auto-rts mechanisms described above), u1ter enables implementation of software flow control, too. when txen=1, uart1 transmitter will keep sending data as long as they are available. as soon as txen becomes 0, uart1 transmission will stop. table 382 describes how to use the txen bit in order to achieve hardware flow control. however, it is strongly suggested to let ua rt1 hardware implemented auto flow control features take for this purpose, and limit t he scope of txen to software flow control. u1ter enables implementation of software and hardware flow control. when txen=1, uart1 transmitter will keep sending data as long as they are available. as soon as txen becomes 0, uart1 tr ansmission will stop. table 382: uart1 transmit enable register (ter - address 0x4001 0030) bit description bit symbol description reset value 6:0 - reserved. read value is undefined, only zero should be written. na 7 txen when this bit is 1, as it is after a reset, data written to the thr is output on the txd pin as soon as any preceding data has been sent. if this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. in other words, a 0 in this bit blocks the transfer of characte rs from the thr or tx fifo into the transmit shift register. software can clear this bit when it detects that the a hardware-handshaking tx-permit signal (cts) has gone false, or with software handshaking, when it receives an xoff character (dc3). software can set this bit again when it detects that the tx-permit signal has gone true, or when it receives an xon (dc1) character. 1 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 484 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.18 uart1 rs485 control register the u1rs485ctrl register controls the configuration of the uart in rs-485/eia-485 mode. 17.5.19 uart1 rs-485 ad dress match register the u1rs485adrmatch register contains th e address match value for rs-485/eia-485 mode. table 383: uart1 rs485 control register (rs485ctrl - address 0x4001 004c) bit description bit symbol value description reset value 0 nmmen rs-485/eia-485 normal multidrop mode (nmm) mode select. 0 0 disabled. 1 enabled. in this mode, an address is detected when a received byte causes the uart to set the parity error and generate an interrupt. 1 rxdis receive enable. 0 0 enabled. 1 disabled. 2 aaden auto address detect (aad) enable. 0 0 disabled. 1 enabled. 3 sel direction control. 0 0 rts. if direction control is enabled (bit dctrl = 1), pin rts is used for direction control. 1 dtr. if direction control is enabled (bit dctrl = 1), pin dtr is used for direction control. 4 dctrl direction control enable. 0 0 disable auto direction control. 1 enable auto direction control. 5oinv polarity. this bit reverses the polarity of the direction control signal on the rts (or dtr) pin. 0 0 low. the direction control pin will be driven to logic ?0? when the transmitter has data to be sent. it will be driven to logic ?1? after the last bit of data has been transmitted. 1 high. the direction control pin will be driven to logic ?1? when the transmitter has data to be sent. it will be driven to logic ?0? after the last bit of data has been transmitted. 31:6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 384. uart1 rs-485 address match register (rs485adrmatch - address 0x4001 0050) bit description bit symbol description reset value 7:0 adrmatch contains the address match value. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 485 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 17.5.20 uart1 rs-485 delay value register the user may program the 8-bit rs485dly regist er with a delay between the last stop bit leaving the txfifo and the de-assertion of rts (or dtr ). this delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. 17.5.21 rs-485/eia-485 modes of operation the rs-485/eia-485 feature allows the uart to be configured as an addressable slave. the addressable slave is one of multiple slaves controlled by a single master. the uart master tr ansmitter will identify an address character by se tting the parity bit to ?1?. for data characters, th e parity bit is set to ?0?. each uart slave receiver can be assigned a unique address. the slave can be programmed to either manually or automatically reject data following an address which is not theirs. rs-485/eia-485 normal multidrop mode (nmm) setting the rs485ctrl bit 0 enables this mode. in this mode, the parity bit is used for the alternative purpose of making a distinction between address and data in received data. if the receiver is disabled (rs485ctrl bit 1 = ?1?) any received data bytes will be ignored and will not be stored in the rxfifo. when an address byte is detected (parity bit = ?1?) it will be placed into the rxfifo and an rx data re ady interrupt w ill be generated. the processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. while the receiver is enabl ed (rs485ctrl bit 1 =?0?) all received bytes will be accepted and stored in the rxfifo regardless of whether they are data or address. rs-485/eia-485 auto address detection (aad) mode when both rs485ctrl register bits 0 (9-bit mode enable) and 2 (aad mode enable) are set, the uart is in auto address detect mode. in this mode, the receiver will compare any address by te received (p arity = ?1?) to the 8-bit value programmed into the rs485adrmatch register. if the receiver is disabled (rs 485ctrl bit 1 = ?1?) any received byte w ill be discarded if it is either a data byte or an address byte which fails to match the rs485adrmatch value. when a matching address char acter is detected it will be pushed onto the rxfifo along with the parity bit, and the receiver will be automatically en abled (rs485ctrl bit 1 will be cleared by hardware). the receiver will also generate n rx data ready interrupt. table 385. uart1 rs-485 delay value register (rs485dly - address 0x4001 0054) bit description bit symbol description reset value 7:0 dly contains the direction control (rts or dtr) delay value. this register works in conjunction with an 8-bit counter. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 486 of 942 nxp semiconductors UM10562 chapter 17: lpc408x/407x uart1 while the receiver is enabl ed (rs485ctrl bit 1 = ?0?) all bytes received will be accepted and stored in the rxfifo until an address byte which does not match the rs485adrmatch value is received. when this occurs, the receiver will be automatically disabled in hardware (rs485ctrl bit 1 will be set), the received non-matching address character will not be st ored in th e rxfifo. rs-485/eia-485 auto direction control rs485/eia-485 mode includes the option of allowing the transmitter to automatically control the state of either the rts pin or the dtr pin as a direction control output signal. setting rs485ctrl bit 4 = ?1? enables this feature. direction control, if enabled, will use the rts pin when rs485ctrl bi t 3 = ?0?. it will use the dtr pin when rs485ctrl bit 3 = ?1?. when auto direction control is enabled, the sele cted pin will be asse rted (driven low) when the cpu writes data into the txfifo. th e pin will be de-assert ed (driven high) once the last bit of data has been transmitted. see bits 4 and 5 in the rs485ctrl register. the rs485ctrl bit 4 takes pr ecedence over all other mechanisms controlling rts (or dtr ) with the exception of loopback mode. rs485/eia-485 driver delay time the driver delay time is the delay between th e last stop bit leaving the txfifo and the de-assertion of rts (or dtr). this delay time can be programmed in the 8-bit rs485dly register. the delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. rs485/eia-485 output inversion the polarity of the direction control signal on the rts (or dtr ) pins can be reversed by programming bit 5 in the u1rs485ctrl register. when this bit is set, the direction control pin will be driven to logic 1 wh en the transmitter has data wait ing to be sent. the direction control pin will be driven to logic 0 after the last bit of data has been transmitted.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 487 of 942 18.1 how to read this chapter most lpc408x/407x family devices include 5 uarts. a few devices implement only 4 uarts. refer to a specific device data sheet for details. uarts 0, 2, and 3 are essentially the same as uart1, but without modem/flow control signals. uart4, described in the next chapter, adds a synchronous mode and a smart card mode. 18.2 basic configuration the uart0/2/3 peripherals are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bits pcuart0/2/3. remark: on reset, uart0 is enabled (pcuart0 = 1), and uart2/3 are disabled (pcuart2/3 = 0). 2. peripheral clock: these uarts operate fr om the common pclk that clocks both the bus interface and functional porti on of most apb peripherals. see section 3.3.3.5 . 3. baud rate: in register u0/2/3lcr ( table 396 ), set bit dlab =1. this enables access to registers dll ( table 390 ) and dlm ( table 391 ) for setting the baud rate. also, if needed, set the fractional baud rate in the fractional divider register ( table 400 ). 4. uart fifo: use bit fifo enable (bit 0) in register u0/2/3fcr ( table 395 ) to enable the fifos. 5. pins: select uart pins and pin modes through the relevant iocon registers ( section 7.4.1 ). remark: uart receive pins should not have pull-down resistors enabled. 6. interrupts: to enable uart interrupts set bit dlab =0 in register u0/2/3lcr ( table 396 ). this enables access to u0/2/3ier ( ta b l e 3 9 2 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 7. dma: uart0/2/3 transmit and receive functions can operate with the gpdma controller (see ta b l e 6 9 2 ). UM10562 chapter 18: lpc408x/407x uart0/2/3 rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 488 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.3 features ? data sizes of 5, 6, 7, and 8 bits. ? parity generation and checking: odd, even mark, space or none. ? one or two stop bits. ? 16 byte receive and transmit fifos. ? built-in baud rate generator, including a fractional rate divider for great versatility. ? supports dma for both transmit and receive. ? auto-baud capability ? break generation and detection. ? multiprocessor addressing mode. ? support for software flow control. ? rs-485/eia-485 support. 18.4 architecture the architecture of the uarts 0, 2, a nd 3 are shown below in the block diagram. the apb interface provides a communicatio ns link between the cpu or host and the uart. the uartn receiver block, unrx, monitors the serial input line, rxdn, for valid input. the uartn rx shift register (unrsr) accepts valid characters via rxdn. after a valid character is assembled in the unrsr, it is passed to the uartn rx buffer register fifo to await access by the cpu or host via the generic host interface. the uartn transmitter block, untx, accepts dat a written by the cpu or host and buffers the data in the uartn tx holding register fifo (unthr). the uartn tx shift register (untsr) reads the data stored in the unthr and assembles the data to transmit via the serial output pin, txdn. the uartn baud rate generator block, unbrg, generates the timing enables used by the uartn tx block. the unbrg clock input source is the apb clock (pclk). the main clock is divided down per the divisor specified in the undll and undlm registers. this divided down clock is the 16x oversample clock. the interrupt interface contains registers unier and uniir. the interrupt interface receives several one clock wide enables from the untx and unrx blocks. status information from the untx and unrx is stored in the unlsr. control information for the untx and unrx is stored in the unlcr.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 489 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.5 pin description fig 73. uart0, 2, and 3 block diagram transmitter shift register transmitter holding register transmitter fifo transmitter receiver shift register receiver buffer register receiver fifo receiver tx_dma_req tx_dma_clr rx_dma_req rx_dma_clr baud rate generator fractional rate divider main divider (dlm, dll) transmitter dma interface receiver dma interface pclk line control & status fifo control & status un_txd un_rxd un_oe rs-485 & auto-baud uartn interrupt interrupt control & status 120601 table 386: uartn pin description pin type description u0_rxd, u2_rxd, u3_rxd input serial input. serial receive data. u0_txd, u2_txd, u3_txd output serial output. serial transmit data. u0_oe, u2_oe, u3_oe output output enable. rs-485/eia-485 output enable.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 490 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6 register description each uart contains registers as shown in table 387 . the divisor latch access bit (dlab) is contained in unlcr7 and enables access to th e divisor latches. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 387. register overview: uart0/2/3 (base address: 0x4000 c000, 0x4008 8000, 0x4009 c000) name access address offset description reset value [1] table rbr ro 0x000 receiver buffer register. contains the next received character to be read . na 388 thr wo 0x000 transmit holding register. the next character to be transmitted is written here (dlab =0). na 389 dll r/w 0x000 divisor latch lsb. least significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider (dlab =1). 0x01 390 dlm r/w 0x004 divisor latch msb. most significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider (dlab =1). 0 391 ier r/w 0x004 interrupt enable register. contains individual interrupt enable bits for the 7 potential uart interrupts (dlab =0). 0 392 iir ro 0x008 interrupt id register. identifies which interrupt(s) are pending. 0x01 393 fcr wo 0x008 fifo control register. controls uart fifo usage and modes. 0 395 lcr r/w 0x00c line control register. contains controls for frame formatting and break generation. 0 396 - - 0x010 reserved. - - lsr ro 0x014 line status register. contains flags for transmit and receive status, including line errors. 0x60 397 - - 0x018 reserved. - - scr r/w 0x01c scratch pad register. 8- bit temporary storage for software. 0 398 acr r/w 0x020 auto-baud control register. contains controls for the auto-baud feature. 0 399 fdr r/w 0x028 fractional divider register. generates a clock input for the baud rate divider. 0x10 400 - - 0x02c reserved. - - ter r/w 0x030 transmit enable register. turns off uart transmitter for use with software flow control. 0x80 402 - - 0x034 to 0x048 reserved. - - rs485ctrl r/w 0x04c rs-485/eia-485 control. contains controls to configure various aspects of rs-485/eia-485 modes. 0 403 rs485 adrmatch r/w 0x050 rs-485/eia-485 address match. contains the address match value for rs-485/eia-485 mode. 0 404 rs485dly r/w 0x054 rs-485/eia-485 direction control delay. 0 405
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 491 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.1 uartn receiver buffer register the unrbr is the top byte of the uartn rx fi fo. the top byte of the rx fifo contains the oldest character received and can be read via the bus interface. the lsb (bit 0) represents the ?oldest? received data bit. if the character received is less than 8 bits, the unused msbs are padded with zeroes. the divisor latch access bit (dlab) in lcr must be zero in order to access the unrbr. the unrbr is always read-only. since pe, fe and bi bits correspond to the by te sitting on the top of the rbr fifo (i.e. the one that will be read in the next read from the rbr), t he right appr oach for fetching the valid pair of received byte and its status bits is first to read the content of the u0lsr register, and then to read a byte from the unrbr. 18.6.2 uartn transmit holding register the unthr is the top byte of the uartn tx fi fo. the top byte is the newest character in the tx fifo and can be written via the bus in terface. the lsb represents the first bit to transmit. the divisor latch access bit (dlab) in unl cr must be zero in order to access the unthr. the unthr is always write-only. table 388: uartn receiver buffer register when dlab = 0, read only (rbr - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 04009 c000 (uart3) ) bit description bit symbol description reset value 7:0 rbr the uartn receiver buffer register contai ns the oldest received byte in the uartn rx fifo. undefined 31:8 - reserved, the value read from a reserved bit is not defined. na table 389: uartn transmit holding register when dlab = 0, write only (thr - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 0x4009 c000 (uart3)) bit description bit symbol description 7:0 thr writing to the uartn transmit holding register causes the data to be stored in the uartn transmit fifo. the byte will be sent when it reaches the bottom of the fifo and the transmitter is available. 31:8 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 492 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.3 uartn divisor latch lsb register the uartn divisor latch is part of the uart n baud rate generator and holds the value used, along with the fractional divider, to divide the apb clock (pclk) in order to produce the baud rate clock, which must be 16 ? the desired baud rate. the undll and undlm registers together form a 16 -bit divisor where undll contains the lower 8 bits of the divisor and undlm contains the higher 8 bits of the divisor. a 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. the divisor latch access bit (dlab) in unlcr must be one in order to access th e uartn divisor latches. details on how to select the right value for undll and undlm can be found later in this chapter, see section 18.6.11 . table 390: uartn divi sor latch lsb register when dlab = 1 (dll - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 0x4009 c000 (uart3)) bit description bit symbol description reset value 7:0 dllsb the uartn divisor latch lsb register, along with the undlm register, determines the baud rate of the uartn. 0x01 31:8 - reserved. read value is undefined, only zero should be written. na table 391: uartn divisor latch msb register when dlab = 1 (dlm - address 0x4000 c004 (uart0), 0x4009 8004 (uart2), 0x4009 c004 (uart3)) bit description bit symbol description reset value 7:0 dlmsb the uartn divisor latch msb register, along with the u0dll register, determines the baud rate of the uartn. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 493 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.4 uartn interrupt enable register the unier is used to enable the three uartn interrupt sources. table 392: uartn interrupt enable register when dlab = 0 (ier - address 0x4000 c004 (uart0), 0x4009 8004 (uart2), 0x4009 c004 (uart3)) bit description bit symbol value description reset value 0 rbrie rbr interrupt enable. enables the receive data available interrupt for uartn. it also controls the character receive time-out interrupt. 0 0 disable the rda interrupts. 1 enable the rda interrupts. 1 threie thre interrupt enable. enables the thre interrupt for uartn. the status of this can be read from unlsr[5]. 0 0 disable the thre interrupts. 1 enable the thre interrupts. 2 rxie rx line status interrupt enable. enables the uartn rx line status interrupts. the status of this interrupt can be read from unlsr[4:1]. 0 0 disable the rx line status interrupts. 1 enable the rx line status interrupts. 7:3 - reserved. read value is undefined, only zero should be written. na 8 abeointen enables the end of auto-baud interrupt. 0 0 disable end of auto-baud interrupt. 1 enable end of auto-baud interrupt. 9 abtointen enables the auto-baud time-out interrupt. 0 0 disable auto-baud time-out interrupt. 1 enable auto-baud time-out interrupt. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 494 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.5 uartn interrupt id entification register the uniir provides a status code that denot es the priority and source of a pending interrupt. the interrupts are frozen during an un iir access. if an interrupt occurs during an uniir access, the interrupt is recorded for the next uniir access. bit uniir[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. the auto-baud interrupt conditions are cleared by setting the corresponding clear bits in the auto-baud control register. if the intstatus bit is 1 no interr upt is pending and the intid bits will be zero. if the intstatus is 0, a non auto-baud interrupt is pending in which case the intid bits identify the type of interrupt and handling as described in table 394 . given the status of uniir[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. the uniir must be read in order to clear the interrupt prior to exiting the interrupt service routine. the uartn rls interrupt (uniir[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the uartn rx input: overrun error (oe), parity error (pe), framing error (fe) and break interrupt (bi). the uartn rx error condition that set the interrupt can be observed via unlsr[4:1]. the interrupt is cleared upon an unlsr read. the uartn rda interrupt (uniir[3:1] = 010) shar es the second level priority with the cti interrupt (uniir[3:1] = 110). the rda is acti vated when the uartn rx fifo reaches the trigger level defined in unfcr[7:6] and is reset when the uartn rx fifo depth falls below the trigger level. when the rda interrupt goes active, the cpu can read a block of data defined by the trigger level. table 393: uartn interrupt identification register, read only (iir - address 0x4000 c008 (uart0), 0x4009 8008 (uart2), 0x4009 c008 (uart3)) bit description bit symbol value description reset value 0 intstatus interrupt status. note that uniir[0] is active low. the pending interrupt can be determined by evaluating uniir[3:1]. 1 0 at least one interrupt is pending. 1 no interrupt is pending. 3:1 intid interrupt identification. unier[3:1] identifies an interrupt corresponding to the uartn rx or tx fifo. all other combinations of unier[3:1] not listed below are reserved (000,100,101,111). 0 0x3 1 - receive line status (rls). 0x2 2a - receive data available (rda). 0x6 2b - character time-out indicator (cti). 0x1 3 - thre interrupt 5:4 - reserved. read value is undefined, only zero should be written. na 7:6 fifoenable copies of unfcr[0]. 0 8 abeoint end of auto-baud in terrupt. true if auto-baud has finished successfully and interrupt is enabled. 0 9 abtoint auto-baud time-out interrupt. true if auto-baud has timed out and interrupt is enabled. 0 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 495 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 the cti interrupt (uniir[3:1] = 11 0) is a second level interrup t and is set when the uartn rx fifo contains at least one character and no uartn rx fifo activity has occurred in 3.5 to 4.5 character times. an y uartn rx fifo activity (read or write of uartn rsr) will clear the interrupt. this interrupt is intended to flush the uartn rbr after a message has been received that is not a multiple of the tr igger level size. for example, if a peripheral wished to send a 105 character message an d the trigger level was 10 characters, the cpu would receive 10 rda interrupts resulting in the transfer of 100 characters and 1 to 5 cti interrupts (depending on the service routine) resulting in the tran sfer of the remaining 5 characters. [1] values "0000", ?0011?, ?0101?, ?0111?, ?1000?, ?100 1?, ?1010?, ?1011?,?1101?,?1110?,?1111? are reserved. [2] for details see section 18.6.8 ? uartn line status register ? [3] for details see section 18.6.1 ? uartn receiver buffer register ? [4] for details see section 18.6.5 ? uartn interrupt identification register ? and section 18.6.2 ? uartn transmit holding register ? the uartn thre interrupt (uni ir[3:1] = 001) is a third leve l interrupt and is activated when the uartn thr fifo is empty provided certain initialization conditions have been met. these initialization conditions are inten ded to give the uartn thr fifo a chance to fill up with data to eliminate many thre interr upts from occurring at system start-up. the initialization conditions implement a one c haracter delay minus the stop bit whenever thre = 1 and there have not been at least two characters in the unthr at one time since the last thre = 1 event. this delay is pr ovided to give the cpu time to write data to unthr without a thre interr upt to decode and service. a thre interrupt is set immediately if the uartn thr fifo has held two or more characters at one time and currently, the unthr is empty. the thre interrupt is reset when a unthr write occurs or a read of the uniir occurs and the thre is the highest interr upt (uniir[3:1] = 001). table 394: uartn interrupt handling u0iir[3:0] value [1] priority interrupt type interrupt source interrupt reset 0001 - none none - 0110 highest rx line status / error oe [2] or pe [2] or fe [2] or bi [2] unlsr read [2] 0100 second rx data available rx data available or trigger level reached in fifo (unfcr0=1) unrbr read [3] or uartn fifo drops below trigger level 1100 second character time-out indication minimum of one character in the rx fifo and no character input or removed during a time period depending on how many characters are in fifo and what the trigger level is set at (3.5 to 4.5 character times). the exact time will be: [(word length) ? 7 - 2] ? 8 + [(trigger level - number of characters) ? 8 + 1] rclks unrbr read [3] 0010 third thre thre [2] uniir read (if source of interrupt) or thr write [4]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 496 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.6 uartn fifo control register the write-only unfcr controls the oper ation of the uartn rx and tx fifos. 18.6.6.1 dma operation the user can optionally operate the uart tr ansmit and/or receive using dma. the dma mode is determined by the dma mode select bit in the fcr register. this bit only has an affect when the fifos are enabled via the fifo enable bit in the fcr register. uart receiver dma in dma mode, the receiver dm a request is asserted on the event of the receiver fifo level becoming equal to or greater than trigger level, or if a character timeout occurs. see the description of the rx trigger level above. the receiver dma request is cleared by the dma controller. uart transmitter dma in dma mode, the transmitter dma request is asserted on the event of the transmitter fifo transitioning to not full. the transmitter dma request is cleared by the dma controller. table 395: uartn fifo control register, write only (fcr - address 0x4000 c008 (uart0), 0x4009 8008 (uart2), 0x4007 c008 (uart3)) bit description bit symbol value description reset value 0 fifoen fifo enable. 0 0 uartn fifos are disabled. must not be used in the application. 1 active high enable for both uartn rx and tx fifos and unfcr[7:1] access. this bit must be set for proper uart operation. any transition on this bit will automatically clear the related uart fifos. 1 rxfifores rx fifo reset. 0 0 no impact on either of uartn fifos. 1 writing a logic 1 to unfcr[1] will clear all bytes in uartn rx fifo, reset the pointer logic. this bit is self-clearing. 2 txfifores tx fifo reset. 0 0 no impact on either of uartn fifos. 1 writing a logic 1 to unfcr[2] will clear all bytes in uartn tx fifo, reset the pointer logic. this bit is self-clearing. 3 dmamode dma mode select. when the fifo enable (bit 0 of this register) is set, this bit selects the dma mode. see section 18.6.6.1 . 0 5:4 - reserved. read value is undefined, only zero should be written. na 7:6 rxtriglvl rx trigger level. these two bits determine how many receiver uartn fifo characters must be written before an in terrupt or dma request is activated. 0 0x0 trigger level 0 (1 character or 0x01). 0x1 trigger level 1 (4 characters or 0x04). 0x2 trigger level 2 (8 characters or 0x08). 0x3 trigger level 3 (14 characters or 0x0e). 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 497 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.7 uartn line control register the unlcr determines the format of the data character that is to be transmitted or received. table 396: uartn line control register (lcr - address 0x4000 c00c (uart0), 0x4009 800c (uart2), 0x4009 c00c (uart3)) bit description bit symbol value description reset value 1:0 wls word length select. 0 0x0 5-bit character length 0x1 6-bit character length 0x2 7-bit character length 0x3 8-bit character length 2 sbs stop bit select 0 0 1 stop bit. 1 2 stop bits (1.5 if unlcr[1:0]=00). 3 pe parity enable. 0 0 disable parity generation and checking. 1 enable parity generation and checking. 5:4 ps parity select 0 0x0 odd parity. number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 even parity. number of 1s in the transmitted character and the attached parity bit will be even. 0x2 forced 1 stick parity. 0x3 forced 0 stick parity. 6 bc break control 0 0 disable break transmission. 1 enable break transmission. output pin uartn txd is forced to logic 0 when unlcr[6] is active high. 7 dlab divisor latch access bit 0 0 disable access to divisor latches. 1 enable access to divisor latches. 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 498 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.8 uartn line status register the unlsr is a read-only register that prov ides status information on the uartn tx and rx blocks. table 397: uartn line status register (lsr - address 0x4000 c014 (uart0), 0x4009 8014 (uart2), 0x4009 c014 (uart3)) bit description bit symbol value description reset value 0 rdr receiver data ready. unlsr[0] is set when the unrbr holds an unread character and is cleared when the uartn rbr fifo is empty. 0 0 the uartn receiver fifo is empty. 1 the uartn receiver fifo is not empty. 1 oe overrun error. the overrun error condition is set as soon as it occurs. an unlsr read clears unlsr[1]. unlsr[1] is set when uartn rsr has a new character assembled and the uartn rbr fifo is full. in this case, the uartn rbr fifo will not be overwritten and the character in the uartn rsr will be lost. 0 0 overrun error status is inactive. 1 overrun error stat us is active. 2 pe parity error. when the parity bit of a received character is in the wrong state, a parity error occurs. an unlsr read clears unlsr[2]. time of parity error detection is dependent on unfcr[0]. note: a parity error is associated with the character at the top of the uartn rbr fifo. 0 0 parity error status is inactive. 1 parity error status is active. 3 fe framing error. when the stop bit of a received character is a logic 0, a framing error occurs. an unlsr read clears unlsr[3]. the time of the framing error detection is dependent on unfcr[0]. upon detection of a framing error, the rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. however, it cannot be assumed that the next received byte will be correct even if there is no framing error. note: a framing error is associated with the character at the top of the uartn rbr fifo. 0 0 framing error status is inactive. 1 framing error status is active. 4 bi break interrupt. when rxdn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. once the break condition has been detected, the receiver goes idle until rxdn goes to marking state (all ones). an unlsr read clears this status bit. the time of break detection is dependent on unfcr[0]. note: the break interrupt is associated with the character at the top of the uartn rbr fifo. 0 0 break interrupt status is inactive. 1 break interrupt status is active. 5 thre transmitter holding register empty. thre is set immediately upon detection of an empty uartn thr and is cleared on a unthr write. 1 0 unthr contains valid data. 1 unthr is empty. 6 temt transmitter empty. temt is set when both unthr and untsr are empty; temt is cleared when either the untsr or the unthr contain valid data. 1 0 unthr and/or the untsr contains valid data. 1 unthr and the untsr are empty.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 499 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.9 uartn scratch pad register the unscr has no effect on the uartn operat ion. this register can be written and/or read at user?s discretion. there is no provision in the interrup t interface that would indicate to the host that a read or write of the unscr has occurred. 7 rxfe error in rx fifo . unlsr[7] is set when a character with a rx error such as framing error, parity error or break interrupt, is loaded into the unrbr. this bit is cleared when the unlsr register is read and there are no subsequent errors in the uartn fifo. 0 0 unrbr contains no uartn rx errors or unfcr[0]=0. 1 uartn rbr contains at least one uartn rx error. 31:8 - reserved. the value read from a reserved bit is not defined. na table 397: uartn line status register (lsr - address 0x4000 c014 (uart0), 0x4009 8014 (uart2), 0x4009 c014 (uart3)) bit description bit symbol value description reset value table 398: uartn scratch pad register (scr - address 0x4000 c01c (uart0), 0x4009 801c (uart2), 0x4009 c01c (uart3)) bit description bit symbol description reset value 7:0 pad a readable, writable byte. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 500 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.10 uartn auto-ba ud control register the uartn auto-baud control register (unacr) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user?s discretion. 18.6.10.1 auto-baud the uartn auto-baud function can be used to measure the incoming baud rate based on the ?at? protocol (hayes co mmand). if enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers undlm and undll accordingly. remark: the fractional rate divider is not conn ected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. auto-baud is started by setting the unacr st art bit. auto-baud can be stopped by clearing the unacr start bit. the start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pendi ng/finished). two auto-baud measuring modes are availa ble which can be selected by the unacr mode bit. in mode 0 the baud rate is meas ured on two subsequent falling edges of the uartn rx pin (the falling edge of the start bit and the falling edge of the least significant bit). in mode 1 the baud rate is measured betw een the falling edge and the subsequent rising edge of the uartn rx pin (the length of the start bit). table 399: uartn auto-baud control register (acr - address 0x4000 c020 (uart0), 0x4009 8020 (uart2), 0x4009 c020 (uart3)) bit description bit symbol value description reset value 0 start start bit. this bit is automatically cleared after auto-baud completion. 0 0 auto-baud stop (auto-baud is not running). 1 auto-baud start (auto-baud is running). auto-baud run bit. this bit is automatically cleared after auto-baud completion. 1 mode auto-baud mode select bit. 0 0 mode 0. 1 mode 1. 2 autorestart restart bit. 0 0 no restart. 1 restart in case of time-out (counter restarts at next uartn rx falling edge) 0 7:3 - reserved. read value is undefined, only zero should be written. na 8 abeointclr end of auto-baud interrupt clear bit (write-only accessible). writing a 1 will clear the corresponding interrupt in the uniir. writing a 0 has no impact. 0 0no impact. 1 clear the corresponding interrupt in the iir. 9 abtointclr auto-baud time-out interrupt clear bit (write-only accessible). writing a 1 will clear the corresponding interrupt in the uniir. writing a 0 has no impact. 0 0no impact. 1 clear the corresponding interrupt in the iir. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 501 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 the unacr autorestart bit can be used to automatically re start baud rate measurement if a time-out occurs (the rate measurement co unter overflows). if this bit is set the rate measurement will restart at the next falling edge of the uartn rx pin. the auto-baud function can generate two interrupts. ? the uniir abtoint inte rrupt will get set if the interrup t is enabled (unier abtointen is set and the auto-baud rate measurement counter overflows). ? the uniir abeoint interr upt will get set if the interrupt is enabled (unier abeointen is set and the auto-baud has completed successfully). the auto-baud interrupts have to be cleared by setting the corresponding unacr abtointclr and abeointen bits. typically the fractional baud rate generator is disabled (divaddval = 0) during auto-baud. however, if the fractional baud rate generator is enabled (divaddval > 0), it is going to impact the measuring of uartn rx pin baud rate, but the value of the unfdr register is not going to be modified after rate measurement. also, when auto-baud is used, any write to undlm and undll registers should be done before unacr register write. the minimum and the maximum baud rates su pported by uartn ar e function of pclk, number of data bits, stop bits and parity bits. (3) 18.6.10.2 auto-baud modes when the software is expecting an ?at? co mmand, it configures the uartn with the expected character format and sets the unacr start bit. the initial values in the divisor latches undlm and undlm don?t care. because of the ?a? or ?a? ascii coding (?a" = 0x41, ?a? = 0x61), the uartn rx pin sensed start bit and the lsb of the expected character are delim ited by two falling edges. when th e unacr start bit is set, the auto-baud protocol will ex ecute the follo wing phases: 1. on unacr start bit setting, the baud ra te measurement counter is reset and the uartn unrsr is reset. the unrsr baud rate is switch to the highest rate. 2. a falling edge on uartn rx pin triggers the beginning of the start bit. the rate measuring counter will start counting pc lk cycles optionally pre-scaled by the fractional baud rate generator. 3. during the receipt of the start bit, 16 pu lses are generated on the rsr baud input with the frequency of the (fractional baud rate pre-scaled) uartn input clock, guaranteeing the start bit is stored in the unrsr. 4. during the receipt of the start bit (and the character lsb for mode = 0) the rate counter will continue incrementing with the pre-scaled uartn input clock (pclk). 5. if mode = 0 then the rate counter will stop on next falling edge of t he uartn rx pin. if mode = 1 then the rate counte r will stop on the next risi ng edge of the uartn rx pin. ratemin 2p ? clk 16 2 15 ? ------------------------ - uart n baudrate pclk 16 2 databits paritybits stopbits ++ + ?? ? ------------------------------------------------------------------------------------------------------------ ?? ratemax ==
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 502 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 6. the rate counter is loaded into undlm/undll and the baud rate will be switched to normal operation. after setting the undlm/undll the end of auto-baud interrupt uniir abeoint will be set, if enabled. th e unrsr will now cont inue receiving the remaining bits of the ?a/a? character. a. mode 0 (start bit and lsb are used for auto-baud) b. mode 1 (only start bit is used for auto-baud) fig 74. auto-baud a) mode 0 and b) mode 1 waveform uartn rx start bit lsb of 'a' or 'a' unacr start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'a' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate uartn rx start bit lsb of 'a' or 'a' rate counter 'a' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop unacr start 16 cycles 16xbaud_rate
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 503 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.11 uartn fractional divider register the uartn fractional divider register (unfdr) controls the clock pre-scaler for the baud rate generation and can be read and writte n at the user?s discretion. this pre-scaler takes the apb clock and generates an output clock according to th e specified fractional requirements. important: if the fractional divider is active (divaddval > 0) and dlm = 0, the value of the dll register must be greater than 2. this register controls the clo ck pre-scaler for the baud rate generation. the reset value of the register keeps the fractional capabilities of the uart disabled, making sure that the uart is fully software and hardware compat ible with uarts not equipped with this feature. the uart baud rate can be calculated as (n = 0/2/3): (4) where pclk is the peripheral clock, undlm and undll are the standard uart baud rate divider registers, and divaddval and mulval are uart fractional baud rate generator specific parameters. the value of mulval and divaddval should comply to the following conditions: 1. 1 ? mulval ? 15 2. 0 ? divaddval ? 14 3. divaddval < mulval the value of the unfdr should not be modified while transmitting/receiving data or data may be lost or corrupted. if the unfdr register value does not comply to these two requests, then the fractional divider output is undefined. if divaddval is zero then the fractional divider is disabled, and the clock will not be divided. table 400: uartn fractional divider register (fdr - address 0x4000 c028 (uart0), 0x4009 8028 (uart2), 0x4009 c028 (uart3)) bit description bit function value description reset value 3:0 divaddval 0 baud rate generation pre-scaler divisor value. if this field is 0, fractional baud rate generator will not impact the uartn baud rate. 0 7:4 mulval 1 baud rate pre-scaler multiplier value. this field must be greater or equal 1 for uartn to operate properly, regardless of whether the fractional baud rate generator is used or not. 1 31:8 - reserved. read value is undefined, only zero should be written. 0 uartn baudrate pclk 16 256 undlm ? undll + ?? ? 1 divaddval mulval ----------------------------- + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------------- =
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 504 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.11.1 baud rate calculation uartn can operate with or without using the frac tional divider. in real-life applications it is likely that the desired baud rate can be achieved using several different fractional divider settings. the fo llowing algorithm illustra tes one way of finding a set of dlm, dll, mulval, and divaddval values. such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. fig 75. algorithm for setting uart dividers pclk, br calculating uart baudrate (br) dl est = pclk/(16 x br) dl est is an integer? divaddval = 0 mulval = 1 tr u e fr est = 1.5 dl est = int(pclk/(16 x br x fr est )) 1.1 < fr est < 1.9? pick another fr est from the range [1.1, 1.9] fr est = pclk/(16 x br x dl est ) divaddval = table(fr est ) mulval = table(fr est ) dlm = dl est [15:8] dll = dl est [7:0] end false tr u e false
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 505 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.11.1.1 example 1: pclk = 14.7456 mhz, br = 9600 according to the provided algorithm dl est = pclk/(16 x br) = 14.7456 mhz / (16 x 9600) = 96. since this dl est is an integer number, divaddval = 0, mulval = 1, dlm = 0, and dll = 96. 18.6.11.1.2 example 2: pclk = 12 mhz, br = 115200 according to the provided algorithm dl est = pclk/(16 x br) = 12 mhz / (16 x 115200) = 6.51. this dl est is not an integer number and the next step is to estimate the fr parameter. using an initial estimate of fr est = 1.5 a new dl est = 4 is calculated and fr est is recalculated as fr est = 1.628. since frest = 1.628 is within the specified range of 1.1 and 1.9, divaddval and mulval values can be obtained from the attached look-up table. the closest value for frest = 1.628 in the look-up table 401 is fr = 1.625. it is equivalent to divaddval = 5 and mulval = 8. based on these findings, the suggested uart setup would be: dlm = 0, dll = 4, divaddval = 5, and mulval = 8. according to equation 4 the uart rate is 115384. this rate has a relative error of 0.16% from the originally specified 115200. table 401. fractional divider setting look-up table fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11 1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6 1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13 1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7 1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15 1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8 1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9 1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10 1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11 1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12 1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13 1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14 1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 506 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.12 uartn transmit enable register the unter register enables implementation of software flow control. when txen=1, uartn transmitter will keep sending data as long as they are available. as soon as txen becomes 0, uartn tr ansmission will stop. table 402 describes how to use the txen bit in order to achieve software flow control. table 402: uartn transmit enable register (ter - address 0x4000 c030 (uart0), 0x4009 8030 (uart2), 0x4009 c030 (uart3)) bit description bit symbol description reset value 6:0 - reserved. read value is undefined, only zero should be written. na 7 txen when this bit is 1, as it is after a reset, data written to the thr is output on the txd pin as soon as any preceding data has been sent. if this bit is cl eared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. in other words, a 0 in this bit blocks the transfer of characters from the thr or tx fifo into the transmit shift register. software implementing software-handshaking can clear this bit when it receives an xoff character (dc3). software can se t this bit again when it receives an xon (dc1) character. 1 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 507 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.13 uartn rs485 control register the unrs485ctrl register controls conf iguration of the rs-485/eia-485 mode. 18.6.14 uartn rs-485 addr ess match register the unrs485adrmatch register contains th e address match value for rs-485/eia-485 mode. table 403: uartn rs485 control register (rs485ctrl - address 0x4000 c04c (uart0), 0x4009 804c (uart2), 0x4009 c04c (uart3)) bit description bit symbol value description reset value 0 nmmen nmm enable. 0 0 rs-485/eia-485 normal multidrop mode (nmm) is disabled. 1 rs-485/eia-485 normal multidrop mode (nmm) is enabled. in this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. see section 18.6.16 ? rs-485/eia-485 modes of operation ? . 1 rxdis receiver enable. 0 0 the receiver is enabled. 1 the receiver is disabled. 2 aaden aad enable. 0 0 auto address detect (aad) is disabled. 1 auto address detect (aad) is enabled. 3 - reserved. read value is undefined, only zero should be written. na 4 dctrl direction control enable. 0 0 disable auto direction control. 1 enable auto direction control. 5 oinv direction control pin polarity. this bit reverses the polarity of the direction control signal on the un_oe pin. 0 0 the direction control pin will be driven to logic ?0? when the transmitter has data to be sent. it will be driven to logic ?1? after the last bit of data has been transmitted. 1 the direction control pin will be driven to logic ?1? when the transmitter has data to be sent. it will be driven to logic ?0? after the last bit of data has been transmitted. 31:6 - reserved. read value is undefined, only zero should be written. na table 404. uartn rs-485 address match register (rs485adrmatch - address 0x4000 c050 (uart0), rs485adrmatch - 0x4009 8050 (uart2), rs485adrmatch - 0x4009 c050 (uart3)) bit description bit symbol description reset value 7:0 adrmatch contains the address match value. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 508 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 18.6.15 uartn rs-485 delay value register the user may program the 8-bit rs485dly regist er with a delay between the last stop bit leaving the txfifo and the de-assertion of un _oe. this delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. 18.6.16 rs-485/eia-485 modes of operation the rs-485/eia-485 feature allows the uart to be configured as an addressable slave. the addressable slave is one of multiple slaves controlled by a single master. the uart master tr ansmitter will identify an address character by se tting the parity bit to ?1?. for data characters, th e parity bit is set to ?0?. each uart slave receiver can be assigned a unique address. the slave can be programmed to either manually or automatically reject data following an address which is not theirs. rs-485/eia-485 normal multidrop mode (nmm) setting the rs485ctrl bit 0 enables this mode. in this mode, the parity bit is used for the alternative purpose of making a distinction between address and data in received data. if the receiver is disabled (rs485ctrl bit 1 = ?1?) any received data bytes will be ignored and will not be stored in the rxfifo. when an address byte is detected (parity bit = ?1?) it will be placed into the rxfifo and an rx data re ady interrupt w ill be generated. the processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. while the receiver is enabl ed (rs485ctrl bit 1 =?0?) all received bytes will be accepted and stored in the rxfifo regardless of whether they are data or address. rs-485/eia-485 auto address detection (aad) mode when both rs485ctrl register bits 0 (9-bit mode enable) and 2 (aad mode enable) are set, the uart is in auto address detect mode. in this mode, the receiver will compare any address by te received (p arity = ?1?) to the 8-bit value programmed into the rs485adrmatch register. if the receiver is disabled (rs 485ctrl bit 1 = ?1?) any received byte w ill be discarded if it is either a data byte or an address byte which fails to match the rs485adrmatch value. when a matching address char acter is detected it will be pushed onto the rxfifo along with the parity bit, and the receiver will be automatically en abled (rs485ctrl bit 1 will be cleared by hardware). the receiver will also generate n rx data ready interrupt. table 405. uartn rs-485 delay value register (rs485dly - address 0x4000 0054 (uart0), rs485dly - 0x4009 8054 (uart2), rs485dly - 0x4009 c054 (uart3)) bit description bit symbol description reset value 7:0 dly contains the direction control (unoe) delay value. this register works in conjunction with an 8-bit counter. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 509 of 942 nxp semiconductors UM10562 chapter 18: lpc408x/407x uart0/2/3 while the receiver is enabl ed (rs485ctrl bit 1 = ?0?) all bytes received will be accepted and stored in the rxfifo until an address byte which does not match the rs485adrmatch value is received. when this occurs, the receiver will be automatically disabled in hardware (rs485ctrl bit 1 will be set), the received non-matching address character will not be st ored in th e rxfifo. rs-485/eia-485 auto direction control rs485/eia-485 mode includes the option of allowing the transmitter to automatically control the state of the unoe pin as a direction control output signal. setting rs485ctrl bit 4 = ?1? enables this feature. when auto direction control is enabled, the unoe pin will be asserted (dri ven low) when the cpu writes data in to the txfifo. the pin will be de -asserted (driven high) once the last bit of data has been transmitted. see bits 4 and 5 in the rs485ctrl register. when auto direction control is enabled, the sele cted pin will be asse rted (driven low) when the cpu writes data into the txfifo. th e pin will be de-assert ed (driven high) once the last bit of data has been transmitted. see bits 4 and 5 in the rs485ctrl register. rs485/eia-485 driver delay time the driver delay time is the delay between th e last stop bit leaving the txfifo and the de-assertion of unoe. this delay time can be programmed in the 8-bit rs485dly register. the delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. rs485/eia-485 output inversion the polarity of the direction control sig nal on the unoe pin can be reversed by programming bit 5 in the unrs485ctrl register. when this bit is set, the direction control pin will be driven to logic 1 wh en the transmitter has data wait ing to be sent. the direction control pin will be driven to logic 0 after the last bit of data has been transmitted.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 510 of 942 19.1 how to read this chapter most lpc408x/407x family devices include 5 uarts. a few devices do not include uart4. refer to section 1.4 and specific device data sheets for details. uart4 is essentially the same as uarts 02/3, but with an added synchronous mode and smartcard mode. 19.2 basic configuration uart4 is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcuart4. remark: on reset, uart4 is disabled (pcuart4 = 0). 2. peripheral clock: this uart operates from the common pclk that clocks both the bus interface and functional porti on of most apb peripherals. see section 3.3.3.5 . 3. baud rate: in register u4lcr ( ta b l e 4 1 6 ), set bit dlab =1. this enables access to registers dll ( table 410 ) and dlm ( ta b l e 4 11 ) for setting the baud rate. also, if needed, set the fractional baud rate in the fractional divider register ( table 422 ). 4. uart fifo: use bit fifo enable (bit 0) in register u4fcr ( table 415 ) to enable the fifos. 5. pins: select uart pins and pin modes through the relevant iocon registers ( section 7.4.1 ). remark: uart receive pins should not have pull-down resistors enabled. 6. interrupts: to enable uart interrupts set bit dlab =0 in register u4lcr ( ta b l e 4 1 6 ). this enables acce ss to u4ier ( table 412 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 7. dma: uart4 transmit and receive functi ons can operate with the gpdma controller (see table 692 ). UM10562 chapter 19: lpc408x/407x uart4 rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 511 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.3 features ? data sizes of 5, 6, 7, and 8 bits. ? parity generation and checking: odd, even mark, space or none. ? one or two stop bits. ? 16 byte receive and transmit fifos. ? built-in baud rate generator, including a fractional rate divider for great versatility. ? supports dma for both transmit and receive. ? auto-baud capability ? break generation and detection. ? multiprocessor addressing mode. ? irda mode to support infrared communication. ? support for software flow control. ? rs-485/eia-485 9-bit mode support with output enable. ? optional synchronous send or receive mode. ? optional iso 7816-3 compliant smartcard interface. 19.4 architecture the architecture of uart4 is shown below in the block diagram. the apb interface provides a communicatio ns link between the cpu or host and the uart. the uart4 receiver block, u4rx, monitors the serial input line, rxdn, for valid input. the uart4 rx shift register (u4rsr) accepts valid characters via rxdn. after a valid character is assembled in u4rsr, it is passed to the uart4 rx buffer register fifo to await access by the cpu or host via the generic host interface. the uart4 transmitter block, u4tx, accepts dat a written by the cpu or host and buffers the data in the uart4 tx holding register fifo (u4thr). the uart4 tx shift register (u4tsr) reads the data stored in u4thr and assembles the data to transmit via the serial output pin, txdn. the uart4 baud rate generator block, u4brg, generates the timing enables used by the uart4 tx block. the u4brg clock input source is the apb clock (pclk). the main clock is divided down per the divisor specified in the u4dll and u4dlm registers. this divided down clock is the 16x oversample clock. the interrupt interface contains registers u4ier and u4iir. the interrupt interface receives several one clock wide enables from the u4tx and u4rx blocks. status information from the u4tx and u4rx is stored in the u4lsr. control information for the u4tx and u4rx is stored in u4lcr.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 512 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.5 pin description fig 76. uart 4 block diagram transmitter shift register transmitter holding register transmitter fifo transmitter receiver shift register receiver buffer register receiver fifo receiver tx_dma_req tx_dma_clr rx_dma_req rx_dma_clr transmitter dma interface receiver dma interface pclk line control & status fifo control & status u4_txd u4_rxd u4_oe rs485, irda, & auto-baud uart4 interrupt interrupt control & status sclk csrc baud rate/clock generator fractional rate divider main divider (dlm, dll) sclk out sclk in 120601 table 406: uart4 pin description pin type description u4_rxd input serial input. serial receive data. u4_txd output serial output. serial transmit data (input/output in smartcard mode). u4_oe output output enable. rs-485/eia-485 output enable. u4_sclk i/o serial clock. clock input or output in synchronous mode and smartcard mode.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 513 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6 register description the divisor latch access bit (dlab) is contained in u4lcr7 and enables access to the divisor latches. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 407. register overview: uart4 (base address: 0x400a 4000) name access address offset description reset value [1] table rbr ro 0x000 receiver buffer register. contains the next received character to be read (dlab =0). na 408 thr wo 0x000 transmit holding register. the next character to be transmitted is written here (dlab =0). na 409 dll r/w 0x000 divisor latch lsb. least significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider (dlab =1). 0x01 410 dlm r/w 0x004 divisor latch msb. most significant byte of the baud rate divisor value. the full divisor is used to generate a baud rate from the fractional rate divider (dlab =1). 0 411 ier r/w 0x004 interrupt enable register. contains individual interrupt enable bits for the 7 potential uart interrupts (dlab =0). 0 412 iir ro 0x008 interrupt id register. identifies which interrupt(s) are pending. 0x01 413 fcr wo 0x008 fifo control register. controls uart fifo usage and modes. 0 415 lcr r/w 0x00c line control register. contains controls for frame formatting and break generation. 0 416 lsr ro 0x014 line status register. contains flags for transmit and receive status, including line errors. 0x60 417 scr r/w 0x01c scratch pad register. 8-bit temporary storage for software. 0 418 acr r/w 0x020 auto-baud control register. contains controls for the auto-baud feature. 0 419 icr r/w 0x024 irda control register. enables and configures the irda mode. 0 420 fdr r/w 0x028 fractional divider register. generates a clock input for the baud rate divider. 0x10 422 osr r/w 0x02c oversampling register. controls the degree of oversampling during each bit time. 0xf0 424 scictrl r/w 0x048 smart card interface control register. enables and configures the smartcard interface feature. 0 425 rs485ctrl r/w 0x04c rs-485/eia-485 control. contains controls to configure various aspects of rs-485/eia-485 modes. 0 426 adrmatch r/w 0x050 rs-485/eia-485 address match. contains the address match value for rs-485/eia-485 mode. 0 427 rs485dly r/w 0x054 rs-485/eia-485 direction control delay. 0 428 syncctrl r/w 0x058 synchronous mode control register. 0 429
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 514 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.1 uart4 receiver buffer register the u4rbr is the top byte of the uart4 rx fi fo. the top byte of the rx fifo contains the oldest character received and can be read via the bus interface. the lsb (bit 0) represents the ?oldest? received data bit. if the character received is less than 8 bits, the unused msbs are padded with zeroes. the divisor latch access bit (dlab) in lcr must be zero in order to access the u4rbr. the u4rbr is always read-only. since pe, fe and bi bits correspond to the by te sitting on the top of the rbr fifo (i.e. the one that will be read in the next read from the rbr), t he right appr oach for fetching the valid pair of received byte and its status bits is first to read the content of the u0lsr register, and then to read a byte from the u4rbr. 19.6.2 uart4 transmit holding register the u4thr is the top byte of the uart4 tx fi fo. the top byte is the newest character in the tx fifo and can be written via the bus in terface. the lsb represents the first bit to transmit. the divisor latch access bit (dlab) in u4l cr must be zero in order to access the u4thr. the u4thr is always write-only. table 408: uart4 receiver buffer re gister when dlab = 0 (rbr - address 0x400a 4000 ) bit description bit symbol description reset value 7:0 rbr the uart4 receiver buffer register contai ns the oldest received byte in the uart4 rx fifo. undefined 31:8 - reserved, the value read from a reserved bit is not defined. na table 409: uart4 transmit holding register when dlab = 0 (thr -address 0x400a 4000 ) bit description bit symbol description 7:0 thr writing to the uart4 transmit holding register causes the data to be stored in the uart4 transmit fifo. the byte will be sent when it reaches the bottom of the fifo and the transmitter is available. 31:8 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 515 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.3 uart4 divisor latch lsb register the uart4 divisor latch is part of the uart 4 baud rate generator and holds the value used, along with the fractional divider, to divide the apb clock (pclk) in order to produce the baud rate clock, which must be 16 ? the desired baud rate. the u4dll and u4dlm registers together form a 16 -bit divisor where u4dll contains the lower 8 bits of the divisor and u4dlm contains the higher 8 bits of the divisor. a 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. the divisor latch access bit (dlab) in u4lcr must be one in order to access th e uart4 divisor latches. details on how to select the right value for u4dll and u4dlm can be found later in this chapter, see section 19.6.12 . table 410: uart4 divisor latch lsb register when dlab = 1 (dll - address 0x400a 4000 ) bit description bit symbol description reset value 7:0 dllsb the uart4 divisor latch lsb register, along with the u4dlm register, determines the baud rate of the uart4. 0x01 31:8 - reserved. read value is undefined, only zero should be written. na table 411: uart4 divisor latch msb register when dlab = 1 (dlm - address 0x400a 4004 ) bit description bit symbol description reset value 7:0 dlmsb the uart4 divisor latch msb register, along with the u0dll register, determines the baud rate of the uart4. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 516 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.4 uart4 interrupt enable register the u4ier is used to enable the three uart4 interrupt sources. table 412: uart4 interrupt enable register when dlab = 0 (ier - address 0x400a 4004 ) bit description bit symbol value description reset value 0 rbrie rbr interrupt enable. enables the receive data available interrupt for uartn. it also controls the character receive time-out interrupt. 0 0 disable the rda interrupts. 1 enable the rda interrupts. 1 threie thre interrupt enable. enables the thre interrupt for uartn. the status of this can be read from unlsr[5]. 0 0 disable the thre interrupts. 1 enable the thre interrupts. 2 rxie rx line status interrupt enable. enables the uartn rx line status interrupts. the status of this interrupt can be read from unlsr[4:1]. 0 0 disable the rx line status interrupts. 1 enable the rx line status interrupts. 7:3 - reserved. read value is undefined, only zero should be written. na 8 abeointen enables the end of auto-baud interrupt. 0 0 disable end of auto-baud interrupt. 1 enable end of auto-baud interrupt. 9 abtointen enables the auto-baud time-out interrupt. 0 0 disable auto-baud time-out interrupt. 1 enable auto-baud time-out interrupt. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 517 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.5 uart4 interrupt identification register the u4iir provides a status code that denot es the priority and source of a pending interrupt. the interrupts are frozen during an u4 iir access. if an interrupt occurs during an u4iir access, the interrupt is recorded for the next u4iir access. bit u4iir[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud condition. the auto-baud interrupt conditions are cleared by setting the corresponding clear bits in the auto-baud control register. if the intstatus bit is 1 no interr upt is pending and the intid bits will be zero. if the intstatus is 0, a non auto-baud interrupt is pending in which case the intid bits identify the type of interrupt and handling as described in table 414 . given the status of u4iir[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. the u4iir must be read in order to clear the interrupt prior to exiting the interrupt service routine. the uart4 rls interrupt (u4iir[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the uart4 rx input: overrun error (oe), parity error (pe), framing error (fe) and break interrupt (bi). the uart4 rx error condition that set the interrupt can be observed via u0lsr[4:1]. the interrupt is cleared upon an u4lsr read. table 413: uart4 interrupt identification register (iir - address 0x400a 4008) bit description bit symbol value description reset value 0 intstatus interrupt status. note that u4iir[0] is active low. the pending interrupt can be determined by evaluating u4iir[3:1]. 1 0 at least one interrupt is pending. 1 no interrupt is pending. 3:1 intid interrupt identification. u4ier[3:1] identifies an interrupt corresponding to the uart4 rx or tx fifo. all other combinations of u4ier[3:1] not listed below are reserved (000,100,101,111). 0 0x3 1 - receive line status (rls). 0x2 2a - receive data available (rda). 0x6 2b - character time-out indicator (cti). 0x1 3 - thre interrupt 5:4 - reserved. read value is undefined, only zero should be written. na 7:6 fifoenable copies of u4fcr[0]. 0 8 abeoint end of auto-baud interrupt. true if auto-baud has finished successfully and interrupt is enabled. 0 9 abtoint auto-baud time-out interrupt. true if auto-baud has timed out and interrupt is enabled. 0 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 518 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 the uart4 rda interrupt (u4iir[3:1] = 010) shar es the second level priority with the cti interrupt (u4iir[3:1] = 110). the rda is acti vated when the uart4 rx fifo reaches the trigger level defined in u4fcr[7:6] and is reset when the uart4 rx fifo depth falls below the trigger level. when the rda interrupt goes active, the cpu can read a block of data defined by the trigger level. the cti interrupt (u4iir[3:1] = 11 0) is a second level interrup t and is set when the uart4 rx fifo contains at least one character and no uart4 rx fifo activity has occurred in 3.5 to 4.5 character times. an y uart4 rx fifo activity (read or write of uart4 rsr) will clear the interrupt. this interrupt is intended to flush the uart4 rbr after a message has been received that is not a multiple of the tr igger level size. for example, if a peripheral wished to send a 105 character message an d the trigger level was 10 characters, the cpu would receive 10 rda interrupts resulting in the transfer of 100 characters and 1 to 5 cti interrupts (depending on the service routine) resulting in the tran sfer of the remaining 5 characters. [1] values "0000", ?0011?, ?0101?, ?0111?, ?1000?, ?100 1?, ?1010?, ?1011?,?1101?,?1110?,?1111? are reserved. [2] for details see section 19.6.8 ? uart4 line status register ? [3] for details see section 19.6.1 ? uart4 receiver buffer register ? [4] for details see section 19.6.5 ? uart4 interrupt identification register ? and section 19.6.2 ? uart4 transmit holding register ? the uart4 thre interrupt (u4i ir[3:1] = 001) is a third leve l interrupt and is activated when the uart4 thr fifo is empty provided certain initialization conditions have been met. these initialization conditions are inten ded to give the uart4 thr fifo a chance to fill up with data to eliminate many thre interr upts from occurring at system start-up. the initialization conditions implement a one c haracter delay minus the stop bit whenever thre = 1 and there have not been at least two characters in the u4thr at one time since the last thre = 1 event. this delay is pr ovided to give the cpu time to write data to u4thr without a thre interr upt to decode and service. a thre interrupt is set table 414: uart4 interrupt handling u0iir[3:0] value [1] priority interrupt type interrupt source interrupt reset 0001 - none none - 0110 highest rx line status / error oe [2] or pe [2] or fe [2] or bi [2] u4lsr read [2] 0100 second rx data available rx data available or trigger level reached in fifo (u4fcr0=1) u4rbr read [3] or uart4 fifo drops below trigger level 1100 second character time-out indication minimum of one character in the rx fifo and no character input or removed during a time period depending on how many characters are in fifo and what the trigger level is set at (3.5 to 4.5 character times). the exact time will be: [(word length) ? 7 - 2] ? 8 + [(trigger level - number of characters) ? 8 + 1] rclks u4rbr read [3] 0010 third thre thre [2] u4iir read (if source of interrupt) or thr write [4]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 519 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 immediately if the uart4 thr fifo has held two or more characters at one time and currently, the u4thr is empty. the thre interrupt is reset when a u4thr write occurs or a read of the u4iir occurs and the thre is the highest interr upt (u4iir[3:1] = 001).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 520 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.6 uart4 fifo control register the write-only u4fcr controls the oper ation of the uart4 rx and tx fifos. 19.6.6.1 dma operation the user can optionally operate the uart tr ansmit and/or receive using dma. the dma mode is determined by the dma mode select bit in the fcr register. this bit only has an affect when the fifos are enabled via the fifo enable bit in the fcr register. uart receiver dma in dma mode, the receiver dm a request is asserted on the event of the receiver fifo level becoming equal to or greater than trigger level, or if a character timeout occurs. see the description of the rx trigger level above. the receiver dma request is cleared by the dma controller. uart transmitter dma in dma mode, the transmitter dma request is asserted on the event of the transmitter fifo transitioning to not full. the transmitter dma request is cleared by the dma controller. table 415: uart4 fifo control register (fcr - address 0x400a 4008) bit description bit symbol value description reset value 0 fifoen fifo enable. 0 0 uartn fifos are disabled. must not be used in the application. 1 active high enable for both uartn rx and tx fifos and unfcr[7:1] access. this bit must be set for proper uart operation. any transition on this bit will automatically clear the related uart fifos. 1rxfifore s rx fifo reset. 0 0 no impact on either of uartn fifos. 1 writing a logic 1 to unfcr[1] will clear all bytes in uartn rx fifo, reset the pointer logic. this bit is self-clearing. 2 txfifores tx fifo reset. 0 0 no impact on either of uartn fifos. 1 writing a logic 1 to unfcr[2] will clear all bytes in uartn tx fifo, reset the pointer logic. this bit is self-clearing. 3 dmamode dma mode select. when the fifo enable (bit 0 of this register) is set, this bit selects the dma mode. see section 19.6.6.1 . 0 5:4 - reserved. read value is undefined, only zero should be written. na 7:6 rxtriglvl rx trigger level. these two bits determine how many receiver uartn fifo characters must be written before an interrupt or dma request is activated. 0 0x0 trigger level 0 (1 character or 0x01). 0x1 trigger level 1 (4 characters or 0x04). 0x2 trigger level 2 (8 characters or 0x08). 0x3 trigger level 3 (14 characters or 0x0e). 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 521 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.7 uart4 line control register the u4lcr determines the format of the data character that is to be transmitted or received. table 416: uart4 line control register (lcr - address 0x400a 400c) bit description bit symbol value description reset value 1:0 wls word length select. 0 0x0 5-bit character length 0x1 6-bit character length 0x2 7-bit character length 0x3 8-bit character length 2 sbs stop bit select 0 0 1 stop bit. 1 2 stop bits (1.5 if unlcr[1:0]=00). 3 pe parity enable. 0 0 disable parity generation and checking. 1 enable parity generation and checking. 5:4 ps parity select 0 0x0 odd parity. number of 1s in the transmitted character and the attached parity bit will be odd. 0x1 even parity. number of 1s in the transmitted character and the attached parity bit will be even. 0x2 forced 1 stick parity. 0x3 forced 0 stick parity. 6 bc break control 0 0 disable break transmission. 1 enable break transmission. output pin uartn txd is forced to logic 0 when unlcr[6] is active high. 7 dlab divisor latch access bit 0 0 disable access to divisor latches. 1 enable access to divisor latches. 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 522 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.8 uart4 line status register the u4lsr is a read-only register that prov ides status information on the uart4 tx and rx blocks. table 417: uart4 line status register (lsr - address 0x400a 4014) bit description bit symbol value description reset value 0 rdr receiver data ready. unlsr[0] is set when the unrbr holds an unread character and is cleared when the uartn rbr fifo is empty. 0 0 the uartn receiver fifo is empty. 1 the uartn receiver fifo is not empty. 1 oe overrun error. the overrun error condition is set as soon as it occurs. an unlsr read clears unlsr[1]. unlsr[1] is set when uartn rsr has a new character assembled and the uartn rbr fifo is full. in this case, the uartn rbr fifo will not be overwritten and the character in the uartn rsr will be lost. 0 0 overrun error status is inactive. 1 overrun error stat us is active. 2 pe parity error. when the parity bit of a received character is in the wrong state, a parity error occurs. an unlsr read clears unlsr[2]. time of parity error detection is dependent on unfcr[0]. note: a parity error is associated with the character at the top of the uartn rbr fifo. 0 0 parity error status is inactive. 1 parity error status is active. 3 fe framing error. when the stop bit of a received character is a logic 0, a framing error occurs. an unlsr read clears unlsr[3]. the time of the framing error detection is dependent on unfcr[0]. upon detection of a framing error, the rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. however, it cannot be assumed that the next received byte will be correct even if there is no framing error. note: a framing error is associated with the character at the top of the uartn rbr fifo. 0 0 framing error status is inactive. 1 framing error status is active. 4 bi break interrupt. when rxdn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. once the break condition has been detected, the receiver goes idle until rxdn goes to marking state (all ones). an unlsr read clears this status bit. the time of break detection is dependent on unfcr[0]. note: the break interrupt is associated with the character at the top of the uartn rbr fifo. 0 0 break interrupt status is inactive. 1 break interrupt status is active. 5 thre transmitter holding register empty. thre is set immediately upon detection of an empty uartn thr and is cleared on a unthr write. 1 0 unthr contains valid data. 1 unthr is empty. 6 temt transmitter empty. temt is set when both unthr and untsr are empty; temt is cleared when either the untsr or the unthr contain valid data. 1 0 unthr and/or the untsr contains valid data. 1 unthr and the untsr are empty.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 523 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.9 uart4 scratch pad register the u4scr has no effect on the uart4 operat ion. this register can be written and/or read at user?s discretion. there is no provision in the interrup t interface that would indicate to the host that a read or write of the u4scr has occurred. 7 rxfe error in rx fifo . unlsr[7] is set when a character with a rx error such as framing error, parity error or break interrupt, is loaded into the unrbr. this bit is cleared when the unlsr register is read and there are no subsequent errors in the uartn fifo. 0 0 unrbr contains no uartn rx errors or unfcr[0]=0. 1 uartn rbr contains at least one uartn rx error. 31:8 - reserved. the value read from a reserved bit is not defined. na table 417: uart4 line status register (lsr - address 0x400a 4014) bit description bit symbol value description reset value table 418: uart4 scratch pad register (scr - address 0x400a 401c) bit description bit symbol description reset value 7:0 pad a readable, writable byte. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 524 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.10 uart4 auto-ba ud control register the uart4 auto-baud control register (u4acr) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user?s discretion. 19.6.10.1 auto-baud the uart4 auto-baud function can be used to measure the incoming baud rate based on the ?at? protocol (hayes co mmand). if enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers u4dlm and u4dll accordingly. remark: the fractional rate divider is not conn ected during auto-baud operations, and therefore should not be used when the auto-baud feature is needed. auto-baud is started by setting the u4acr st art bit. auto-baud can be stopped by clearing the u4acr start bit. the start bit will clear once auto-baud has finished and reading the bit will return the status of auto-baud (pendi ng/finished). table 419: uart4 auto-baud control regi ster (acr - 0x400a 4020) bit description bit symbol value description reset value 0 start start bit. this bit is automatically cleared after auto-baud completion. 0 0 auto-baud stop (auto-baud is not running). 1 auto-baud start (auto-baud is running). auto-baud run bit. this bit is automatically cleared after auto-baud completion. 1 mode auto-baud mode select bit. 0 0 mode 0. 1 mode 1. 2 autorestart restart bit. 0 0no restart. 1 restart in case of time-out (counter restarts at next uartn rx falling edge) 0 7:3 - reserved. read value is undefined, only zero should be written. na 8 abeointclr end of auto-baud interrupt clear bit (write-only accessible). writing a 1 will clear the corresponding interrupt in the uniir. writing a 0 has no impact. 0 0no impact. 1 clear the corresponding interrupt in the iir. 9 abtointclr auto-baud time-out interrupt clear bit (write-only accessible). writing a 1 will clear the corresponding interrupt in the uniir. writing a 0 has no impact. 0 0no impact. 1 clear the corresponding interrupt in the iir. 31:10 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 525 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 two auto-baud measuring modes are availa ble which can be selected by the u4acr mode bit. in mode 0 the baud rate is meas ured on two subsequent falling edges of the uart4 rx pin (the falling edge of the start bit and the falling edge of the least significant bit). in mode 1 the baud rate is measured betw een the falling edge and the subsequent rising edge of the uart4 rx pin (the length of the start bit). the u4acr autorestart bit can be used to automatically re start baud rate measurement if a time-out occurs (the rate measurement co unter overflows). if this bit is set the rate measurement will restart at the next falling edge of the uart4 rx pin. the auto-baud function can generate two interrupts. ? the u4iir abtoint inte rrupt will get set if the interrup t is enabled (u4ier abtointen is set and the auto-baud rate measurement counter overflows). ? the u4iir abeoint interr upt will get set if the interrupt is enabled (u4ier abeointen is set and the auto-baud has completed successfully). the auto-baud interrupts have to be cleared by setting the corresponding u4acr abtointclr and abeointen bits. typically the fractional baud rate generator is disabled (divaddval = 0) during auto-baud. however, if the fractional baud rate generator is enabled (divaddval > 0), it is going to impact the measuring of uart4 rx pin baud rate, but the value of the u4fdr register is not going to be modified after rate measurement. also, when auto-baud is used, any write to u4dlm and u4dll registers should be done before u4acr register write. the minimum and the maximum baud rates su pported by uart4 ar e function of pclk, number of data bits, stop bits and parity bits. (5) 19.6.10.2 auto-baud modes when the software is expecting an ?at? co mmand, it configures the uart4 with the expected character format and sets the u4acr start bit. the initial values in the divisor latches u4dlm and u4dlm don?t care. because of the ?a? or ?a? ascii coding (?a" = 0x41, ?a? = 0x61), the uart4 rx pin sensed start bit and the lsb of the expected character are delim ited by two falling edges. when th e u4acr start bit is set, the auto-baud protocol will ex ecute the follo wing phases: 1. on u4acr start bit setting, the baud ra te measurement counter is reset and the uart4 u4rsr is reset. the u4rsr baud rate is switch to the highest rate. 2. a falling edge on uart4 rx pin triggers the beginning of the start bit. the rate measuring counter will start counting pc lk cycles optionally pre-scaled by the fractional baud rate generator. 3. during the receipt of the start bit, 16 pu lses are generated on the rsr baud input with the frequency of the (fractional baud rate pre-scaled) uart4 input clock, guaranteeing the start bit is stored in the u4rsr. ratemin 2p ? clk 16 2 15 ? ------------------------ - uart 4 baudrate pclk 16 2 databits paritybits stopbits ++ + ?? ? ------------------------------------------------------------------------------------------------------------ ?? ratemax ==
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 526 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 4. during the receipt of the start bit (and the character lsb for mode = 0) the rate counter will continue incrementing with the pre-scaled uart4 input clock (pclk). 5. if mode = 0 then the rate counter will stop on next falling edge of t he uart4 rx pin. if mode = 1 then the rate counte r will stop on the next risi ng edge of the uart4 rx pin. 6. the rate counter is loaded into u4dlm/u4dll and the baud rate will be switched to normal operation. after setting the u4dlm/u4dll the end of auto-baud interrupt u4iir abeoint will be set, if enabled. th e u4rsr will now cont inue receiving the remaining bits of the ?a/a? character. a. mode 0 (start bit and lsb are used for auto-baud) b. mode 1 (only start bit is used for auto-baud) fig 77. auto-baud a) mode 0 and b) mode 1 waveform uartn rx start bit lsb of 'a' or 'a' unacr start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop 'a' (0x41) or 'a' (0x61) 16 cycles 16 cycles 16xbaud_rate uartn rx start bit lsb of 'a' or 'a' rate counter 'a' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop unacr start 16 cycles 16xbaud_rate
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 527 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.11 uart4 irda control register the irda control register enables and configures the irda mode on each uart. the value of u4icr should not be changed while transmitting or receiving data, or data loss or corruption may occur. the pulsediv bits in u4icr are used to select the pulse width when the fixed pulse width mode is used in irda mode (irdaen = 1 and fixpulseen = 1). the value of these bits should be set so that the resulting pulse width is at least 1.63 s. ta b l e 4 2 1 shows the possible pulse widths. table 420: uart4 irda control register (icr - address 0x400a 4024) bit description bit symbol value description reset value 0 irdaen irda mode 0 0 disabled. irda mode on uart4 is disabled, uart4 acts as a standard uart. 1 enabled. irda mode on uart4 is enabled. 1 irdainv serial input direction. 0 0 not inverted. 1 inverted. this has no effect on the serial output. 2 fixpulseen irda fixed pulse width mode. 0 0 disabled. 1 enabled. 5:3 pulsediv configures the pulse when fixpulseen = 1. 0 0x0 2xtpclk 0x1 4xtpclk 0x2 8xtpclk 0x3 16xtpclk 0x4 32xtpclk 0x5 64xtpclk 0x6 128xtpclk 0x7 256xtpclk 31:6 - reserved. read value is undefined, only zero should be written. 0 table 421: irda pulse width fixpulseen pulsediv irda transmitter pulse width (s) 0 x 3 / (16 ? baud rate) 102 ? t pclk 114 ? t pclk 128 ? t pclk 131 6 ? t pclk 143 2 ? t pclk 156 4 ? t pclk 1 6 128 ? t pclk 1 7 256 ? t pclk
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 528 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.12 uart4 fractional divider register the uart4 fractional divider register (u4fdr) controls the clock pre-scaler for the baud rate generation and can be read and writte n at the user?s discretion. this pre-scaler takes the apb clock and generates an output clock according to th e specified fractional requirements. important: if the fractional divider is active (divaddval > 0) and dlm = 0, the value of the dll register must be greater than 2. this register controls the clo ck pre-scaler for the baud rate generation. the reset value of the register keeps the fractional capabilities of the uart disabled, making sure that the uart is fully software and hardware compat ible with uarts not equipped with this feature. the uart baud rate can be calculated as: (6) where pclk is the peripheral clock, u4dlm and u4dll are the standard uart baud rate divider registers, and divaddval and mulval are uart fractional baud rate generator specific parameters. the value of mulval and divaddval should comply to the following conditions: 1. 1 ? mulval ? 15 2. 0 ? divaddval ? 14 3. divaddval < mulval the value of the u4fdr should not be modified while transmitting/receiving data or data may be lost or corrupted. if the u4fdr register value does not comply to these two requests, then the fractional divider output is undefined. if divaddval is zero then the fractional divider is disabled, and the clock will not be divided. table 422: uart4 fractional divider register (fdr - address 0x400a 4028) bit description bit function value description reset value 3:0 divaddval 0 baud rate generation pre-scaler divisor value. if this field is 0, fractional baud rate generator will not impact the uart4 baud rate. 0 7:4 mulval 1 baud rate pre-scaler multiplier value. this field must be greater or equal 1 for uart4 to operate properly, regardless of whether the fractional baud rate generator is used or not. 1 31:8 - reserved. read value is undefined, only zero should be written. 0 uart4 baudrate pclk 16 256 u4dlm ? u4dll + ?? ? 1 divaddval mulval ----------------------------- + ?? ?? ? ---------------------------------------------------------------------------------------------------------------------------------- =
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 529 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.12.1 baud rate calculation uart4 can operate with or without using the frac tional divider. in real-life applications it is likely that the desired baud rate can be achieved using several different fractional divider settings. the fo llowing algorithm illustra tes one way of finding a set of dlm, dll, mulval, and divaddval values. such set of parameters yields a baud rate with a relative error of less than 1.1% from the desired one. fig 78. algorithm for setting uart dividers pclk, br calculating uart baudrate (br) dl est = pclk/(16 x br) dl est is an integer? divaddval = 0 mulval = 1 tr u e fr est = 1.5 dl est = int(pclk/(16 x br x fr est )) 1.1 < fr est < 1.9? pick another fr est from the range [1.1, 1.9] fr est = pclk/(16 x br x dl est ) divaddval = table(fr est ) mulval = table(fr est ) dlm = dl est [15:8] dll = dl est [7:0] end false tr u e false
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 530 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.12.1.1 example 1: pclk = 14.7456 mhz, br = 9600 according to the provided algorithm dl est = pclk/(16 x br) = 14.7456 mhz / (16 x 9600) = 96. since this dl est is an integer number, divaddval = 0, mulval = 1, dlm = 0, and dll = 96. 19.6.12.1.2 example 2: pclk = 12 mhz, br = 115200 according to the provided algorithm dl est = pclk/(16 x br) = 12 mhz / (16 x 115200) = 6.51. this dl est is not an integer number and the next step is to estimate the fr parameter. using an initial estimate of fr est = 1.5 a new dl est = 4 is calculated and fr est is recalculated as fr est = 1.628. since frest = 1.628 is within the specified range of 1.1 and 1.9, divaddval and mulval values can be obtained from the attached look-up table. the closest value for frest = 1.628 in the look-up table 423 is fr = 1.625. it is equivalent to divaddval = 5 and mulval = 8. based on these findings, the suggested uart setup would be: dlm = 0, dll = 4, divaddval = 5, and mulval = 8. according to equation 6 the uart rate is 115384. this rate has a relative error of 0.16% from the originally specified 115200. table 423. fractional divider setting look-up table fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval fr divaddval/ mulval 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11 1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6 1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13 1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7 1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15 1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8 1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9 1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10 1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11 1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12 1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13 1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14 1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 531 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.13 uart4 oversampling register in most applications, the uart samples received data 16 times in each nominal bit time, and sends bits that are 16 input clocks wide. this register allows so ftware to control the ratio between the input clock and bit clock. this is required for smartcard mode, and provides an alternative to fractional division for other modes. example: for a baud rate of 3.25mbps with a 24 mhz uart clock frequency, the ideal oversampling ratio is 24/3.25 or 7.3846. setting osint to 0110 for 7 clocks/bit and osfrac to 011 for 0.375 clocks/bit, results in an oversampling ratio of 7.375. in smartcard mode, osint is extended by fd int. this extends the possible ov ersampling to 2048, as required to support iso 7816-3. note that this value can be exceeded when d<0, but this is not supported by the uart. when smartcard mode is enabled, the initial value of osint and fdint should be program med as ?00101110011? (372 minus one). table 424. uart4 oversampling register (osr - address 0x400a 402c) bit description bit symbol description reset value 0 - reserved. read value is undefined, only zero should be written. na 3:1 osfrac fractional part of the oversampling ratio, in units of 1/8th of an input clock period. (001 = 0.125, ?, 111 = 0.875) 0 7:4 osint integer part of the oversampling ratio, minus 1. the reset values equate to the normal operating mode of 16 input clocks per bit time. 0xf 14:8 fdint in smartcard mode, these bits act as a more-significant extension of the osint field, allowing an oversampling ratio up to 2048 as required by iso7816-3. in smartcard mode, bits 14:4 should initially be set to 371, yielding an oversampling ratio of 372. 0 31:15 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 532 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.14 uart4 smart card interface cont rol register this register allows the uart to be us ed in iso7816-3 compliant asynchronous smartcard applications. 19.6.14.1 smartcard connection when the scien bit in the u4scictrl regist er is set as described above, the uart provides bidirectional serial data on the txd pin. no rxd pin is used when scien is 1. if the uart sclk function is enabled in the i/o configuration block, a serial clock is output on the pin: use of such a clock is optional for smartcards. software must use timers to implement character and block waiting times (no hardware support vi a trigger signals is provided in the uart). gpio pins can be us ed to control the smartcard reset and power pins. 19.6.14.2 smartcard setup the following must be set up in smartcard applications: ? if necessary, reset the uart as described in section 3.5 . ? program one iocon register to enable a uart txd function. ? if the smartcard to be communi cated with requires (or may require) a clock, program one iocon register fo r the uart sclk function. the ua rt will use it as an output. ? enable the uart clock and set up uart clocking for an initial uart frequency of 3.58 mhz. ? program the osr ( section 19.6.13 ) for 372x oversampling. ? program the lcr ( section 19.6.7 ) for 8-bit characters, parity enabled, even parity. table 425. uart4 smart card interface control register (scictrl - address 0x400a 4048) bit description bit symbol value description reset value 0 scien smart card interface enable. 0 0 smart card interface disabled. 1 asynchronous half duplex smart card interface is enabled. 1 nackdis nack response disable. only applicable in t=0. 0 0 a nack response is enabled. 1 a nack response is inhibited. 2 protsel protocol selection as defined in the iso7816-3 standard. 0 0t = 0 1t = 1 7:5 txretry maximum number of retransmissions in case of a negative acknowledge (protocol t=0). when the retry counter is exceeded, the usart will be locked until the fifo is cleared. a tx error interrupt is generated when enabled. - 15:8 guardtime extra guard time. no extra guard time (0x0) results in a standard guard time as defined in iso 7816-3, depending on the protocol type. a guard time of 0xff indicates a minimal guard time as defined for the selected protocol. 31:16 - - reserved, user software should not writ e ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 533 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 ? program the gpio signals associated with the smartcard so th at (in this order): ? reset is low. ? vcc is provided to the card (gpio pins do not have the required 200 ma drive). ? vpp (if provided to the card) is at ?idle? state. ? program scictrl ( section 19.6.14 ) to enable the smartcar d feature with the desired options. ? set up one or more timer(s) to provide timing as needed for iso 7816 startup. thereafter, software should monitor the uart and timer status so as to interact with the smartcard as described in iso 7816 3.2.b and subsequently. 19.6.15 uart4 rs485 control register the u4rs485ctrl register controls conf iguration of the rs-485/eia-485 mode. table 426: uart4 rs485 control register (rs485ctrl - address 0x400a 404c) bit description bit symbol value description reset value 0 nmmen nmm enable. 0 0 rs-485/eia-485 normal multidrop mode (nmm) is disabled. 1 rs-485/eia-485 normal multidrop mode (nmm) is enabled. in this mode, an address is detected when a received byte causes the usart to set the parity error and generate an interrupt. see section 19.6.18 ? rs-485/eia-485 modes of operation ? . 1 rxdis receiver enable. 0 0 enabled. 1 disabled. 2 aaden aad enable 0 0 disabled. 1 enabled. 3 - - reserved. - 4 dctrl direction control for dir pin. 0 0 disable auto direction control. 1 enable auto direction control. 5 oinv direction control pin polarity. this bit reverses the polarity of the direction control signal on the dir pin. 0 0 low. the direction control pin will be driven to logic ?0? when the transmitter has data to be sent. it will be driven to logic ?1? after the last bit of data has been transmitted. 1 high. the direction control pin will be driv en to logic ?1? when th e transmitter has data to be sent. it will be driven to logic ?0? after the last bit of data has been transmitted. 31:6 - - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 534 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.16 uart4 rs-485 ad dress match register the u4rs485adrmatch register contains th e address match value for rs-485/eia-485 mode. 19.6.17 uart4 rs-485 delay value register the user may program the 8-bit rs485dly regist er with a delay between the last stop bit leaving the txfifo and the de-assertion of u4 _oe. this delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. 19.6.18 rs-485/eia-485 modes of operation the rs-485/eia-485 feature allows the uart to be configured as an addressable slave. the addressable slave is one of multiple slaves controlled by a single master. the uart master tr ansmitter will identify an address character by se tting the parity bit to ?1?. for data characters, th e parity bit is set to ?0?. each uart slave receiver can be assigned a unique address. the slave can be programmed to either manually or automatically reject data following an address which is not theirs. rs-485/eia-485 normal multidrop mode (nmm) setting the rs485ctrl bit 0 enables this mode. in this mode, the parity bit is used for the alternative purpose of making a distinction between address and data in received data. if the receiver is disabled (rs485ctrl bit 1 = ?1?) any received data bytes will be ignored and will not be stored in the rxfifo. when an address byte is detected (parity bit = ?1?) it will be placed into the rxfifo and an rx data re ady interrupt w ill be generated. the processor can then read the address byte and decide whether or not to enable the receiver to accept the following data. while the receiver is enabl ed (rs485ctrl bit 1 =?0?) all received bytes will be accepted and stored in the rxfifo regardless of whether they are data or address. rs-485/eia-485 auto address detection (aad) mode when both rs485ctrl register bits 0 (9-bit mode enable) and 2 (aad mode enable) are set, the uart is in auto address detect mode. table 427. uart4 rs-485 address match register (rs485adrmatch - address 0x400a 4050) bit description bit symbol description reset value 7:0 adrmatch contains the address match value. 0 31:8 - reserved. read value is undefined, only zero should be written. na table 428. uart4 rs-485 delay value register (rs485dly - address 0x400a 4054) bit description bit symbol description reset value 7:0 dly contains the direction control (u4oe) delay value. this register works in conjunction with an 8-bit counter. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 535 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 in this mode, the receiver will compare any address by te received (p arity = ?1?) to the 8-bit value programmed into the rs485adrmatch register. if the receiver is disabled (rs 485ctrl bit 1 = ?1?) any received byte w ill be discarded if it is either a data byte or an address byte which fails to match the rs485adrmatch value. when a matching address char acter is detected it will be pushed onto the rxfifo along with the parity bit, and the receiver will be automatically en abled (rs485ctrl bit 1 will be cleared by hardware). the receiver will also generate n rx data ready interrupt. while the receiver is enabl ed (rs485ctrl bit 1 = ?0?) all bytes received will be accepted and stored in the rxfifo until an address byte which does not match the rs485adrmatch value is received. when this occurs, the receiver will be automatically disabled in hardware (rs485ctrl bit 1 will be set), the received non-matching address character will not be st ored in th e rxfifo. rs-485/eia-485 auto direction control rs485/eia-485 mode includes the option of allowing the transmitter to automatically control the state of the u4oe pin as a direction control output signal. setting rs485ctrl bit 4 = ?1? enables this feature. when auto direction control is enabled, the u4oe pin will be asserted (dri ven low) when the cpu writes data in to the txfifo. the pin will be de -asserted (driven high) once the last bit of data has been transmitted. see bits 4 and 5 in the rs485ctrl register. when auto direction control is enabled, the sele cted pin will be asse rted (driven low) when the cpu writes data into the txfifo. th e pin will be de-assert ed (driven high) once the last bit of data has been transmitted. see bits 4 and 5 in the rs485ctrl register. rs485/eia-485 driver delay time the driver delay time is the delay between th e last stop bit leaving the txfifo and the de-assertion of u4oe. this delay time can be programmed in the 8-bit rs485dly register. the delay time is in periods of the baud clock. any delay time from 0 to 255 bit times may be programmed. rs485/eia-485 output inversion the polarity of the direction control sig nal on the u4oe pin can be reversed by programming bit 5 in the u4rs485ctrl register. when this bit is set, the direction control pin will be driven to logic 1 wh en the transmitter has data wait ing to be sent. the direction control pin will be driven to logic 0 after the last bit of data has been transmitted.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 536 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 19.6.19 uart4 synchronous mode control register syncctrl register controls the synchronous mode. when this mode is in effect, the uart generates or receives a bit clock on the sclk pin and applies it to the transmit and receive shift registers. after reset, synchronous mode is disabled. synchronous mode is enabled by setting the sync bit. when sync is 1, the uart operates as follows: 1. the csrc bit controls whether the uart sends (master mode) or receives (slave mode) a serial bit clock on the sclk pin. 2. when csrc is 1 selecting master mode, the cscen bit selects whether the uart produces clocks on sclk continuously (csc en=1) or only when transmit data is being sent on txd (cscen=0). table 429. uart4 synchronous mode control register (syncctrl - address 0x400a 4058) bit description bit symbol value description reset value 0 sync enables synchronous mode. 0 0 disabled 1 enabled 1 csrc clock source select. 0 0 synchronous slave mode (sclk in) 1 synchronous master mode (sclk out) 2 fes falling edge sampling. 0 0 rxd is sampled on the rising edge of sclk 1 rxd is sampled on t he falling edge of sclk 3 tsbypass transmit synchronization bypass in synchronous slave mode. 0 0 the input clock is synchronized prior to being used in clock edge detection logic. 1 the input clock is not synchronized prior to being used in clock edge detection logic. this allows for a high er input clock rate at the expense of potential metastability. 4 cscen continuous master clock enable (used only when csrc is 1) 0 0 sclk cycles only when characters are being sent on txd 1 sclk runs continuously (characters can be received on rxd independently from transmission on txd) 5 sssdis start/stop bits 0 0 send start and stop bits as in other modes. 1 do not send start/stop bits. 6 ccclr continuous clock clear 0 0 cscen is under software control. 1 hardware clears cscen after each character is received. 31:6 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 537 of 942 nxp semiconductors UM10562 chapter 19: lpc408x/407x uart4 3. the ssdis bit controls whether start and st op bits are used. when ssdis is 0, the uart sends and samples for start and stop bits as in other modes. when ssdis is 1, the uart neither sends nor samples for star t or stop bits, and each falling edge on sclk samples a data bit on rxd into the receive shift register, as well as shifting the transmit shift register. the rest of this section provides furt her details of operation when sync is 1. data changes on txd from falling edges on sc lk. when ssdis is 0, the fes bit controls whether the uart samples serial data on rxd on rising edges or falling edges on sclk. when ssdis is 1, the uart ignores fes and always samples rxd on falling edges on sclk. the combination sync=1, csrc=1, cscen=1, and ssdis=1 is a difficult operating mode, because sclk applies to both directio ns of data flow and there is no defined mechanism to signal the receivers when valid data is present on txd or rxd. lacking such a mechanism, ssdis=1 can be used with cscen=0 or csrc=0 in a mode similar to the spi protocol, in which charac ters are (at least c onceptually) ?exchanged? between the uart and remote device for ea ch set of 8 clock cycles on sclk. such operation can be called full-duplex, but the same hardware mode can be used in a half-duplex way under control of a higher-layer protocol, in which the source of sclk toggles it in groups of n cycles whenever data is to be sent in either direction. (n being the number of bits/character.) when the uart4 is the clock source (csrc=1), such half-duplex operation can lead to the requirement of writing a dummy character to the transmitter holdin g register in order to generate 8 clocks so that a character can be received. the ccclr bit provides a more natural way of programming half-duplex reception. when the higher-layer protocol dictates that the uart should receive a character, software should write the syncctrl register with cscen=1 and ccclr=1. after the uart has sent n clock cycles and thus received a character, it clears the cscen bit. if more characters need to be received thereafter, software can repeat setting cscen and ccclr. aside from such half-duplex operation, the pr imary use of cscen=1 is with ssdis=0, so that start bits indicate the transmission of each character in each direction.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 538 of 942 20.1 basic configuration the can1/2 peripherals are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bits pcan1/2. remark: on reset, the can1/2 blocks are disabled (pcan1/2 = 0). 2. peripheral clock: the can interfaces op erate from the common pclk that clocks both the bus interface and functional portion of most apb peripherals. see section 3.3.3.5 . remark: if can baud rates above 100 kbit/s (see table 442 ) are needed, do not select the irc as the clock source (see section 3.11 ). 3. wake-up: can controllers are able to wake up the microcontroller from power-down mode, see section 3.12.8 . 4. pins: select can1/2 pins through and their pin modes through the relevant iocon registers ( section 7.4.1 ). 5. interrupts: can interrupts are enabled using the can1/2ier registers ( table 441 ). interrupts are enabled in the nvic using the appropriate interrupt set enable register. 6. can controller initializatio n: see canmod register ( section 20.7.1 ). 20.2 can controllers controller area network (can) is the definition of a high performance communication protocol for serial data communication. the can controller is designed to provide a full implementation of the can-protocol accord ing to the can specification version 2.0b. microcontrollers with this on-chip can controlle r are used to build powerful local networks by supporting distributed real-time contro l with a very high level of security. the applications are automotive, industrial enviro nments, and high speed networks as well as low cost multiplex wiri ng. the result is a strongly r educed wiring harness and enhanced diagnostic and superv isory capabilities. the can block is intended to support multiple can buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of can buses in various applications. the can module consists of two elements: the controller and the acceptance filter. all registers and the ram are ac cessed as 32-bit words. 20.3 features 20.3.1 general can features ? compatible with can specification 2.0b, iso 11898-1 . ? multi-master architecture with non destructive bit-wise arbitration. ? bus access priority determined by th e message identifier (11-bit or 29-bit). UM10562 chapter 20: lpc408x/407x can controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 539 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? guaranteed latency time for high priority messages. ? programmable transfer ra te (up to 1 mbit/s). ? multicast and broadc ast message facility. ? data length from 0 up to 8 bytes. ? powerful error ha ndling capability. ? non-return-to-zero (nrz) encoding/decoding with bit stuffing. 20.3.2 can controller features ? 2 can controllers and buses. ? supports 11-bit identifier as well as 29-bit identifier. ? double receive buffer and triple transmit buffer. ? programmable error warning limit and error counters with read/write access. ? arbitration lost capture and error code capture with detailed bit position. ? single shot transmission (no re-transmission). ? listen only mode (no acknowle dge, no active error flags). ? reception of "own" messages (self reception request). 20.3.3 acceptance filter features ? fast hardware implemented search algorithm supporting a large number of can identifiers. ? global acceptance filter recognizes 11-bit and 29-bit rx identifiers for all can buses. ? allows definition of explicit and groups for 11-bit and 29-b it can identifiers. ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. 20.4 pin description 20.5 can controller architecture the can controller is a complete serial interface with both transmit and receive buffers but without acceptance filter. can identifier filtering is done for all can channels in a separate block (acceptance filter). except fo r message buffering and acceptance filtering the functionality is simila r to the pelican concept. the can controller block includes interfaces to the following blocks: ? apb interface ? acceptance filter table 430. can pin descriptions pin name type description can_rd1, can_rd2 input serial inputs. from can transceivers. can_td1, can_td2 output serial outputs. to can transceivers.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 540 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? nested vectored interrupt controller (nvic) ? can transceiver ? common status registers 20.5.1 apb interface block (aib) the apb interface block provides acce ss to all can controller registers. 20.5.2 interface management logic (iml) the interface management logic interprets commands from the cpu, controls internal addressing of the can registers and provides interrupts and status information to the cpu. 20.5.3 transmit buffers (txb) the txb represents a triple transmit buffer, which is the interface between the interface management logic (iml) and the bit stream pr ocessor (bsp). each transmit buffer is able to store a complete message which can be transmitted over the can network. this buffer is written by the cpu and read out by the bsp. fig 79. can controller block diagram interface management logic transmit buffers 1,2 and 3 receive buffers 1 and 2 bit timing logic bit stream processor error management logic can core block nvic apb bus acceptance filter common status register can transceiver tx rx
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 541 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.5.4 receive buffer (rxb) the receive buffer (rxb) represents a cpu accessible double receive buffer. it is located between the can controller core bloc k and apb interface block and stores all received messages from the can bus line. with the help of this double receive buffer concept the cpu is able to process one message while another message is being received. the global layout of the receive buffer is ve ry similar to the transmit buffer described earlier. identifier, frame format, remote transmission request bit and data length code have the same meaning as described for the transmit buffer. in addition, the receive buffer includes an id index field (see section 20.7.9.1 ? id index field ? ). the received data length code represents the real transmitted data length code, which may be greater than 8 depending on transmitting can node. nevertheless, the maximum number of received data bytes is 8. this should be taken into account by reading a message from the receive buffer. if there is not enough space for a new message within the receive buffer, the can controller generates a data overrun condition when this message becomes valid and the acceptance test was positive. a message that is partly written into the receive buffer (when the data overrun situation occurs) is deleted. this situation is signalled to the cpu via the status register and the data overrun interrupt, if enabled. fig 80. transmit buffer layout for standard and extended frame format configurations tx frame info unused tx priority 0 . . . 0 id.28 ... id.18 tx data 4 tx data 3 tx data 2 tx data 1 tx data 8 tx data 7 tx data 6 tx data 5 unused 31 24 23 16 15 8 7 0 tfs tid tda tdb descriptor field data field standard frame format (11-bit identifier) frame info unused tx dlc tx priority 0 0 0 id.28 ... id.00 tx data 4 tx data 3 tx data 2 tx data 1 tx data 8 tx data 7 tx data 6 tx data 5 unused 31 24 23 16 15 8 7 0 tfs tid tda tdb descriptor field data field extended frame format (29-bit identifier) tx dlc tx
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 542 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.5.5 error management logic (eml) the eml is responsible for the error confinement. it gets error announcements from the bsp and then informs the bsp an d iml about error statistics. 20.5.6 bit timing logic (btl) the bit timing logic monitors the serial can bus line and handles the bus line related bit timing. it synchronizes to the bit stream on the can bus on a "recessive" to "dominant" bus line transition at the beginning of a message (hard synchronization) and re-synchronizes on further transitions during the reception of a message (soft synchronization). the btl also provides programmable time segments to compensate for the propagation delay times and phase shifts (e .g. due to oscillator dr ifts) and to define the sample point and the number of samples to be taken within a bit time. 20.5.7 bit stream processor (bsp) the bit stream processor is a sequencer, controlling the data stream between the transmit buffer, receive buffers and the can bus. it also performs the error detection, arbitration, stuffing and error handling on the can bus. 20.5.8 can controller self-tests the can controller supports two di fferent options for self-tests: ? global self-test (setting the self reception request bit in normal operating mode) ? local self-test (setting the self rece ption request bit in self test mode) fig 81. receive buffer layout for standard and extended frame format configurations rx frame info unused id index id.28 ... id.18 rx data 4 rx data 3 rx data 2 rx data 1 rx data 8 rx data 7 rx data 6 rx data 5 unused 31 24 23 16 15 10 9 8 7 0 rfs rid rda rdb descriptor field data field standard frame format (11-bit identifier) frame info unused rx dlc id.28 ... id.00 rx data 4 rx data 3 rx data 2 rx data 1 rx data 8 rx data 7 rx data 6 rx data 5 31 24 23 16 15 rfs rid rda rdb descriptor field data field extended frame format (29-bit identifier) rx dlc rx unused unused id index unused 10 9 8 7 0 bpm=bypass message
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 543 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller both self-tests are using the ?self reception? feature of the can controller. with the self reception request, the transmitted message is also received and stored in the receive buffer. therefore the acceptance filter has to be configured accordingly. as soon as the can message is transmitted, a transmit and a receive interrupt are generated, if enabled. global self test a global self-test can for example be used to verify the chosen configuration of the can controller in a given can system. as shown in figure 82 , at least one other can node, which is acknowledging each can message has to be connected to the can bus. initiating a global self-test is similar to a normal can transmission. in this case the transmission of a can message(s) is initiate d by setting self reception request bit (srr) in conjunction with the selected message buffer bits (stb3, stb2, stb1) in the can controller command register (cancmr). local self test the local self-test perfectly fits for single n ode tests. in this case an acknowledge from other nodes is not needed. as shown in t he figure below, a can transceiver with an appropriate can bus termination has to be connected to the device. the can controller has to be put into the 'self test mode' by setting the stm bit in the can controller mode register (canmod). hint: setting the self test mode bit (stm) is possible only when the can controller is in reset mode. a message transmission is initiated by se tting self reception request bit (srr) in conjunction with the selected message buffer(s) (stb 3, stb2, stb1). fig 82. global self-test (high-speed can bus example) transceiver rx buffer ack tx buffer can bus microcontroller fig 83. local self test (high-speed can bus example) transceiver rx buffer tx buffer microcontroller
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 544 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.6 memory map of the can block the can controllers and acceptance filter occupy a number of apb slots, as follows: 20.7 register description can block implements the registers at several base addresses. table 431. memory map of the can block address range used for 0x4003 8000 - 0x4003 87ff acceptance filter ram. 0x4003 c000 - 0x4003 c017 acceptance filter registers. 0x4004 0000 - 0x4004 000b central can registers. 0x4004 4000 - 0x4004 405f can controller 1 registers. 0x4004 8000 - 0x4004 805f can controller 2 registers. 0x400f c110 - 0x400f c114 can wake and sleep registers. table 432. register overview: can acceptance filter (base address 0x4003 c000) name access address offset description reset value table afmr r/w 0x000 acceptance filter register 1 460 sff_sa r/w 0x004 standard frame individual start address register 0 461 sff_grp_sa r/w 0x008 standard frame group start address register 0 462 eff_sa r/w 0x00c extended frame start address register 0 463 eff_grp_sa r/w 0x010 extended frame group start address register 0 464 endoftable r/w 0x014 end of af tables register 0 465 luterrad ro 0x018 lut error address register 0 466 luterr ro 0x01c lut error register 0 467 fcanie r/w 0x020 fullcan interrupt enable register 0 468 fcanic0 r/w 0x024 fullcan interrupt and capture register0 0 469 fcanic1 r/w 0x028 fullcan interrupt and capture register1 0 470 table 433. register overview: central can (base address 0x4004 0000) name access address offset description reset value table txsr ro 0x000 can central transmit status register 0x0003 0300 455 rxsr ro 0x004 can central receive status register 0 456 msr ro 0x008 can central miscellaneous register 0 457 table 434. register overview: can (base address 0x4004 4000 (can1) and 0x4004 8000 (can2)) generic name access address offset description reset value table mod r/w 0x000 controls the operating mode of the can controller. 1 437 cmr wo 0x004 command bits that affect the state of the can controller 0 438 gsr ro 0x008 global controller status and error counters. the error counters can only be written when rm in canmod is 1. 0x3c 439
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 545 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller the internal registers of each can controller appear to the cpu as on-chip memory mapped peripheral registers. because the can controller can operate in different modes (operating/reset, see also section 20.7.1 ? can mode register ? ), one has to distinguish between different internal address definitions. no te that write access to some registers is only allowed in reset mode. icr ro 0x00c interrupt status, arbitration lost capture, error code capture 0 440 ier r/w 0x010 interrupt enable 0 441 btr r/w 0x014 bus timing. can only be written when rm in canmod is 1. 0x1c0000 442 ewl r/w 0x018 error warning limit. can only be written when rm in canmod is 1. 0x60 443 sr ro 0x01c status register 0x3c3c3c 444 rfs r/w 0x020 receive frame status. can only be written when rm in canmod is 1. 0 445 rid r/w 0x024 received identifier. can only be written when rm in canmod is 1. 0 446 rda r/w 0x028 received data bytes 1-4. can only be written when rm in canmod is 1. 0 448 rdb r/w 0x02c received data bytes 5-8. can only be written when rm in canmod is 1. 0 449 tfi1 r/w 0x030 transmit frame info (tx buffer 1) 0 450 tid1 r/w 0x034 transmit identifier (tx buffer 1) 0 451 tda1 r/w 0x038 transmit data bytes 1-4 (tx buffer 1) 0 453 tdb1 r/w 0x03c transmit data bytes 5-8 (tx buffer 1) 0 454 tfi2 r/w 0x040 transmit frame info (tx buffer 2) 0 450 tid2 r/w 0x044 transmit identifier (tx buffer 2) 0 451 tda2 r/w 0x048 transmit data bytes 1-4 (tx buffer 2) 0 453 tdb2 r/w 0x04c transmit data bytes 5-8 (tx buffer 2) 0 454 tfi3 r/w 0x050 transmit frame info (tx buffer 3) 0 450 tid3 r/w 0x054 transmit identifier (tx buffer 3) 0 451 tda3 r/w 0x058 transmit data bytes 1-4 (tx buffer 3) 0 453 tdb3 r/w 0x05c transmit data bytes 5-8 (tx buffer 3) 0 454 table 434. register overview: can (base address 0x4004 4000 (can1) and 0x4004 8000 (can2)) generic name access address offset description reset value table table 435. can1 and can2 cont roller register summary generic name operating mode reset mode read write read write mod mode mode mode mode cmr 0x00 command 0x00 command gsr global status and error counters - global status and error counters error counters only icr interrupt and capture - interrupt and capture - ier interrupt enable interrupt enable interrupt enable interrupt enable btr bus timing - bus timing bus timing ewl error warning limit - error warning limit error warning limit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 546 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller in the following register tables, the column ?reset value? shows how a hardware reset affects each bit or field, wh ile the column ?rm set? indica tes how each bit or field is affected if software sets the rm bit, or rm is set because of a bus-off condition. note that while hardware reset sets rm, in this case th e setting noted in the ?reset value? column prevails over that shown in the ?rm set? column , in the few bits where they differ. in both columns, x indicates the bit or field is unchanged. 20.7.1 can mode register the contents of the mode register are us ed to change the behavior of the can controller. bits may be set or reset by th e cpu that uses the mode register as a read/write memory. the following restrictions apply to using the bits in this register: ? during a hardware reset or when the bus status bit is set '1' (bus-off), the reset mode bit is set '1' (present). after the reset mode bit is set '0' the can controller will wait for: - one occurrence of bus-free signal (11 re cessive bits), if the preceding reset has been caused by a hardware reset or a cpu-initiated reset. - 128 occurrences of bus-free, if the preceding reset has been caused by a can controller initiated bus-off, before re-entering the bus-on mode. ? this mode of operation forces the can controller to be error passive. message transmission is not possible. the listen only mode can be used e.g. for software driven bit rate detection and "hot plugging". ? a write access to the bits mod.1 and mod.2 is possible only if the reset mode is entered previously. sr status - status - rfs rx info and index - rx info and index rx info and index rid rx identifier - rx identifier rx identifier rda rx data - rx data rx data rdb rx info and index - rx info and index rx info and index tfi1 tx info1 tx info tx info tx info tid1 tx identifier tx identifier tx identifier tx identifier tda1 tx data tx data tx data tx data tdb1 tx data tx data tx data tx data table 435. can1 and can2 cont roller register summary generic name operating mode reset mode read write read write table 436. register overview: can wake and sleep (base address 0x400f c000) name access address offset description reset value table cansleepclr r/w 0x110 allows clearing the current can channe l sleep state as well as reading that state. 0 35 canwakeflags r/w 0x114 allows reading the wake-up state of the can channels. 0 36
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 547 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? transmit priority mode is explained in more detail in section 20.5.3 ? transmit buffers (txb) ? . ? the can controller will enter sleep mode, if the sleep mo de bit is set '1' (sleep), there is no bus activity, and none of the can interrupts is pending. setting of sm with at least one of the previous ly mentioned exceptions valid will result in a wake-up interrupt. the can controller w ill wake up if sm is set lo w (wake-up) or there is bus activity. on wake-up, a wake-up interrupt is generated. a sleeping can controller which wakes up due to bus acti vity will not be able to receive this message until it detects 11 consecutive recessive bits (bus-f ree sequence). note that setting of sm is not possible in rese t mode. after clearing of reset m ode, setting of sm is possible only when bus-free is detected again. ? the lom and stm bits can only be written if the rm bit is 1 prior to the write operation. table 437. can mode register (can1mod - address 0x40 04 4000, can2mod - address 0x4004 8000) bit description bit symbol value function reset value rm set 0 rm reset mode. 1 1 0 normal.the can controller is in the operating mode, and certain registers can not be written. 1 reset. can operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted. 1 lom listen only mode. 0 x 0 normal. the can controller acknowledges a successfully received message on the can bus. the error counters are stopped at the current value. 1 listen only. the controller gives no acknowledgment, even if a message is successfully received. messages cannot be sent, and the controller operates in ?error passive? mode. this mode is intended for software bit rate detection and ?hot plugging?. 2 stm self test mode. 0 x 0 normal. a transmitted message must be acknowledged to be considered successful. 1 self test. the controller will consider a tx message successful even if there is no acknowledgment received. in this mode a full node test is possible without any other active node on the bus using the srr bit in canxcmr. 3 tpm transmit priority mode. 0 x 0 can id. the transmit priority for 3 transmit buffers depends on the can identifier. 1 local priority. the transmit priority for 3 transmit buffers depends on the contents of the tx priority register within the transmit buffer. 4 sm sleep mode. 0 0 0 wake-up. normal operation. 1 sleep. the can controller enters sleep mode if no can interrupt is pending and there is no bus activity. see the sleep mode description section 20.8.2 on page 565 . 5 rpm receive polarity mode. 0 x 0 low active. rd input is active low (dominant bit = 0). 1 high active. rd input is active high (dominant bit = 1) -- reverse polarity.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 548 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.2 can command register writing to this write-only regist er initiates an action within the transfer layer of the can controller. reading this register yields zeroes. at least one internal clock cycle is ne eded for processing between two commands. the following restrictions apply to using the bits in this register: ? setting the command bits tr and at simultaneously results in transmitting a message once. no re-transmissio n will be performed in case of an error or arbitration lost (single shot transmission). ? setting the command bits srr and tr simultaneously results in sending the transmit message once using the self -reception feature. no re-t ransmission will be performed in case of an error or arbitration lost. ? setting the command bits tr, at and srr simultaneously results in transmitting a message once as described for tr and at. th e moment the transmit status bit is set within the status register, the internal transmission request bit is cleared automatically. ? setting tr and srr simultaneous ly will ignore the set srr bit. ? if the transmission request or the self-r eception request bit was set '1' in a previous command, it cannot be cance lled by resetting the bits. the requested transmission may only be cancelled by setting the abort transmission bit. ? the abort transmission bit is used when the cpu requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before. a transmission already in progress is not stopped. in order to see if the original message has been either transmitted succe ssfully or aborted, the transmission complete status bit should be checked. this should be done after the transmit buffer status bit has been set to '1' or a transmit interrupt has been generated. ? after reading the contents of the receive buffer, the cpu can release this memory space by setting the release receive buffer bit '1'. this may result in another message becoming immediately available. if there is no other message available, the receive interrupt bit is reset. if the rrb command is given, it will take at least 2 internal clock cycles before a new interrupt is generated. ? this command bit is used to clear the data overrun condition signalled by the data overrun status bit. as long as the data ov errun status bit is set no further data overrun interrupt is generated. 6 - reserved. read value is undefined, only zero should be written. 0 0 7 tm test mode. 0x 0 disabled. normal operation. 1 enabled. the td pin will reflect the bit, detected on rd pin, with the next positive edge of the system clock. 31:8 - reserved. read value is undefined, only zero should be written. na table 437. can mode register (can1mod - address 0x40 04 4000, can2mod - address 0x4004 8000) bit description bit symbol value function reset value rm set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 549 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? upon self reception request, a message is transmitted and simultaneously received if the acceptance filter is set to the corresponding identifier. a receive and a transmit interrupt will indicate corr ect self reception (see al so self test mode in section 20.7.1 ? can mode register ? ). table 438. can command register (can1cmr - address 0x4004 4004, can2cmr - address 0x4004 8004) bit description bit symbol value function reset value rm set 0 tr transmission request. 0 0 0 absent.no transmission request. 1 present. the message, previously written to the canxtfi, canxtid, and optionally the canxtda and canxtdb registers, is queued for transmission from the selected transmit buffer. if at two or all three of stb1, stb2 and stb3 bits are selected when tr=1 is written, transmit buffer will be selected based on the chosen priority scheme (for details see section 20.5.3 ? transmit buffers (txb) ? ) 1 at abort transmission. 0 0 0 no action. do not abort the transmission. 1 present. if not already in progress, a pending transmission request for the selected transmit buffer is cancelled. 2 rrb release receive buffer. 0 0 0 no action. do not release the receive buffer. 1 released. the information in the receive buffer (consisting of canxrfs, canxrid, and if applicable the canxrda and canxrdb registers) is released, and becomes eligible for replacement by the next received frame. if the next received frame is not available, writing this command clears the rbs bit in the status register(s). 3 cdo clear data overrun. 0 0 0 no action. do not clear the data overrun bit. 1 clear. the data overrun bit in status register(s) is cleared. 4 srr self reception request. 0 0 0 absent. no self reception request. 1 present. the message, previously written to the canxtfs, canxtid, and optionally the canxtda and canxtdb registers, is queued for transmission from the selected transmit buffer and received simultaneously. this differs from the tr bit above in that the receiver is not disabled during the transmission, so that it receives the message if its identifier is recognized by the acceptance filter. 5 stb1 select tx buffer 1. 0 0 0 not selected. tx buffer 1 is not selected for transmission. 1 selected. tx buffer 1 is selected for transmission. 6 stb2 select tx buffer 2. 0 0 0 not selected. tx buffer 2 is not selected for transmission. 1 selected. tx buffer 2 is selected for transmission. 7 stb3 select tx buffer 3. 0 0 0 not selected. tx buffer 3 is not selected for transmission. 1 selected. tx buffer 3 is selected for transmission. 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 550 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.3 can global status register the content of the global status register refl ects the status of the can controller. this register is read-only, except t hat the error counters can be written when the rm bit in the canmod register is 1. bits not listed read as 0 and should be written as 0. table 439. can global status register (can1gsr - address 0x4004 4008, can2gsr - address 0x4004 8008) bit description bit symbol value function reset value rm set 0 rbs receive buffer status. after reading all messages and releasing their memory space with the command 'release receive buffer,' this bit is cleared. 00 0 empty. no message is available. 1 full. at least one complete message is received by the double receive buffer and available in the canxrfs, canxrid, and if applicable the canxrda and canxrdb registers. this bit is cleared by the release receive buffer command in canxcmr, if no subsequent received message is available. 1 dos data overrun status. if there is not enough space to store the message within the receive buffer, that message is dropped and the data overrun condition is signalled to the cpu in the moment this message becomes valid. if this message is not completed successfully (e.g. because of an error), no overrun condition is signalled. 00 0 absent. no data overrun has occurred since the last clear data overrun command was given/written to canxcmr (or since reset). 1 overrun. a message was lost because the preceding message to this can controller was not read and released quickly enough (there was not enough space for a new message in the double receive buffer). 2 tbs transmit buffer status. 1 1 0 locked. at least one of the transmit buffers is not available for the cpu, i.e. at least one previously queued message for this can controller has not yet been sent, and therefore software should not write to the canxtfi, canxtid, canxtda, nor canxtdb registers of that (those) tx buffer(s). 1 released. all three transmit buffers are available for the cpu. no transmit message is pending for this can controller (in any of the 3 tx buffers), and software may write to any of the canxtfi, canxtid, canxtda, and canxtdb registers. 3 tcs transmit complete status. the transmission complete status bit is set '0' (incomplete) whenever the transmission request bit or the self reception request bit is set '1' at least for one of the three transmit buffers. the transmission complete status bit will remain '0' unt il all messages are transmitted successfully. 1x 0 incomplete. at least one requested transmission has not been successfully completed yet. 1 complete. all requested transmission(s) has (have) been successfully completed. 4 rs receive status. if both the receive status and the transmit status bits are '0' (idle), the can-bus is idle. if both bits are set, the controller is waiting to become idle again. after hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. after bus-off this will take 128 times of 11 consecutive recessive bits. 10 0 idle. the can co ntroller is idle. 1 receive. the can controller is receiving a message.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 551 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller rx error counter the rx error counter register, which is part of the status register, reflects the current value of the receive error counte r. after hardware reset this re gister is initialized to 0. in operating mode this register appears to t he cpu as a read-only memory. a write access to this register is possible only in reset mode. if a bus off event occurs, the rx error counter is initialized to 0. as long as bus off is valid, writing to this register has no effect.the rx error counter is determined as follows: rx error counter = (canxgsr and 0x00ff0000) / 0x00010000 note that a cpu-forced content change of t he rx error counter is possible only if the reset mode was entered previously. an error status change (status register), an error warning or an error passive interrupt forced by the new register content will not occur until the reset mode is cancelled again. 5 ts transmit status. if both the receive status and the transmit status bits are '0' (idle), the can-bus is idle. if both bits are set, the controller is waiting to become idle again. after hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. after bus-off this will take 128 times of 11 consecutive recessive bits. 10 0 idle. the can co ntroller is idle. 1 transmit. the can controller is sending a message. 6 es error status. errors detected during rec eption or transmission will effect the error counters according to the can specification. the error status bit is set when at least one of the error counters has reached or exceeded the error warning limit. an error warning interrupt is generated, if enabled. the default value of the error warning limit after hardware reset is 96 decimal, see also section 20.7.7 ? can error warning limit register ? . 00 0 ok. both error counters are below the error warning limit. 1 error. one or both of the transmit and receive error counters has reached the limit set in the error warning limit register. 7 bs bus status. mode bit '1' (present) and an error warning interrupt is generated, if enabled. afterwards the transmit error counter is set to '127', and the receive error counter is cleared. it will stay in this mode until the cpu clears the reset mode bit. once this is completed the can controller will wait the minimum protocol-defined time (128 occurrences of the bus-free signal) counting down the transmit error counter. after that, the bus status bit is cleared (bus-on), the error status bit is set '0' (ok), the error counters are reset, and an error warning interrupt is generated, if enabled. reading the tx error counter during this time gives information about the status of the bus-off recovery. 00 0 bus-on. the can controller is involved in bus activities 1 bus-off. the can controller is currently not involved/prohibited from bus activity because the transmit error counter reached its limiting value of 255. 15:8 - reserved. read value is undefined, only zero should be written. na 23:16 rxerr - the current value of the rx error counter (an 8-bit value). 0 x 31:24 txerr - the current value of the tx error counter (an 8-bit value). 0 x table 439. can global status register (can1gsr - address 0x4004 4008, can2gsr - address 0x4004 8008) bit description bit symbol value function reset value rm set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 552 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller tx error counter the tx error counter register, which is part of the status register, reflects the current value of the transmit error counter. in operating mode this register appears to the cpu as a read-only memory. after hardware reset this register is initialized to 0. a write access to this register is possible only in reset mode. if a bus-o ff event occurs, the tx error counter is initialized to 127 to count the minimum protocol-defined time (128 occurrences of the bus-free signal). reading the tx erro r counter during this ti me gives information about the status of the bus-off recovery. if bu s off is active, a write access to txerr in the range of 0 to 254 clears th e bus off flag and the controlle r will wait for one occurrence of 11 consecutive recessive bi ts (bus free) after clearing of reset mode. the tx error counter is determined as follows: tx error counter = (canxgsr and 0xff000000) / 0x01000000 writing 255 to txerr allows initiation of a cpu-driven bus off event. note that a cpu-forced content change of the tx error counter is possible only if the reset mode was entered previously. an error or bus status change (status register), an error warning, or an error passive interrupt forced by the new register content will not occur until the reset mode is cancelled again. after leaving the reset mode, the new tx counter content is interpreted and the bus off event is performed in the same way as if it was forced by a bus error event. that means, that the reset mode is entered again, the tx error counter is initialized to 127, the rx counter is cleared, and all concerned status and interrupt register bits ar e set. clearing of reset mode now will perform the protocol defined bus off recovery sequence (waiting for 128 occurrences of the bus-free signal). if the reset mode is entered again before t he end of bus off recovery (txerr>0), bus off keeps active and txerr is frozen. 20.7.4 can interrupt and capture register bits in this register indicate information ab out events on the can bus. this register is read-only. the interrupt flags of the interrupt and capture register allow the identification of an interrupt source. when one or more bits are set, a can interrupt will be indicated to the cpu. after this register is read from the cpu all interrupt bits are reset except of the receive interrupt bit. the interrupt register appears to the cpu as a read-only memory. bits 1 through 10 clear when they are read. bits 16-23 are captured when a bus error occurs. at the same time, if the beie bit in canier is 1, the bei bit in this regist er is set, and a can interrupt can occur. bits 24-31 are captured when can arbitration is lost. at the same time, if the alie bit in canier is 1, the ali bit in this register is set, and a can in terrupt can occur. once either of these bytes is captured, its va lue will remain the same until it is read, at which time it is released to capture a new value. the clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read from canxicr, regardless of whether part or all of the register is read. this means that software should always read canxicr as a word, and process and deal with all bits of the register as appropriate for the application.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 553 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller table 440. can interrupt and capture register (can1icr - address 0x4004 400c, can2icr - address 0x4004 800c) bit description bit symbol value function reset value rm set 0 ri receive interrupt. this bit is set whenever the rbs bit in canxsr and the rie bit in canxier are both 1, indicating that a new message was received and stored in the receive buffer. the receive interrupt bit is not cleared upon a read access to the interrupt register. giving the command ?release receive buffer? will clear ri temporarily. if there is another message available within the receive buffer after the release command, ri is set again. otherwise ri remains cleared. 00 0 reset 1set 1 ti1 transmit interrupt 1. this bit is set when the tbs1 bit in canxsr goes from 0 to 1 (whenever a message out of txb1 was successfully transmitted or aborted), indicating that transmit buffer 1 is avai lable, and the tie1 bit in canxier is 1. 00 0 reset 1set 2 ei error warning interrupt. this bit is set on every change (set or clear) of either the error status or bus status bit in canxsr and the eie bit is set within the interrupt enable register at the time of the change. 0x 0 reset 1set 3 doi data overrun interrupt. this bit is set when the dos bit in canxsr goes from 0 to 1 and the doie bit in canxier is 1. 00 0 reset 1set 4 wui wake-up interrupt. this bit is set if the can controller is sleeping and bus activity is detected and the wuie bit in canxier is 1. a wake-up interrupt is also generated if the cpu tries to set the sleep bit while the can controller is involved in bus acti vities or a can interrupt is pending. the wui flag can also get asserted when the according enable bit wuie is not set. in this case a wake-up inte rrupt does not get asserted. 00 0 reset 1set 5 epi error passive interrupt. this bit is set if the epie bit in canxier is 1, and the can controller switches between error passive and error active mode in either direction. this is the case when the can controller has reached the error passive status (at least one error counter exceeds the can protocol defined level of 127) or if the can controller is in error passive status and enters the error active status again. 00 0 reset 1set 6 ali arbitration lost interrupt. this bit is set if the alie bit in canxier is 1, and the can controller loses arbitration while attempting to transmit. in this case the can node becomes a receiver. 00 0 reset 1set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 554 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 7 bei bus error interrupt -- this bit is set if the beie bit in canxier is 1, and the can controller detects an error on the bus. 0x 0 reset 1set 8 idi id ready interrupt -- this bit is set if the idie bit in canxier is 1, and a can identifier has been received (a message was successfully transmitted or aborted). this bit is set whenever a message was successfully transmitted or aborted and the idie bit is set in the ier register. 00 0 reset 1set 9 ti2 transmit interrupt 2. this bit is set when the tbs2 bit in canxsr goes from 0 to 1 (whenever a message out of txb2 was successfully transmitted or aborted), indicating that transmit buffer 2 is avai lable, and the tie2 bit in canxier is 1. 00 0 reset 1set 10 ti3 transmit interrupt 3. this bit is set when the tbs3 bit in canxsr goes from 0 to 1 (whenever a message out of txb3 was successfully transmitted or aborted), indicating that transmit buffer 3 is avai lable, and the tie3 bit in canxier is 1. 00 0 reset 1set 15:11 - reserved. the value read from a reserved bit is not defined. 0 0 table 440. can interrupt and capture register (can1icr - address 0x4004 400c, can2icr - address 0x4004 800c) bit description ?continued bit symbol value function reset value rm set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 555 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20:16 errbit4_0 error code capture: when the can controller detects a bus error, the location of the error within the frame is captured in th is field. the value reflects an internal state variable, and as a result is not very linear: 00011 = start of frame 00010 = id28 ... id21 00110 = id20 ... id18 00100 = srtr bit 00101 = ide bit 00111 = id17 ... 13 01111 = id12 ... id5 01110 = id4 ... id0 01100 = rtr bit 01101 = reserved bit 1 01001 = reserved bit 0 01011 = data length code 01010 = data field 01000 = crc sequence 11000 = crc delimiter 11001 = acknowledge slot 11011 = acknowledge delimiter 11010 = end of frame 10010 = intermission whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. at the same time, the current position of the bit stream processor is captured into the error code capture register. the content within this register is fixed until the user software has read out its content once. from now on, the capture mechanism is activated again, i.e. reading the canxicr enables another bus error interrupt. 0x 21 errdir when the can controller detects a bus error, the direction of the current bit is captured in this bit. 0x 0 error occurred during transmitting. 1 error occurred du ring receiving. table 440. can interrupt and capture register (can1icr - address 0x4004 400c, can2icr - address 0x4004 800c) bit description ?continued bit symbol value function reset value rm set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 556 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.5 can interrupt enable register this read/write register contro ls whether various ev ents on the can cont roller will result in an interrupt or not. bits 10:0 in this regi ster correspond 1-to-1 with bits 10:0 in the canxicr register. if a bit in the canxier regi ster is 0 the corresponding interrupt is disabled; if a bit in the canxier register is 1 the corresponding source is enabled to trigger an interrupt. 23:22 errc1:0 when the can controller detects a bus error, the type of error is captured in this field: 0x 0x0 bit error 0x1 form error 0x2 stuff error 0x3 other error 31:24 alcbit - each time arbitration is lost while trying to send on the can, the bit number within the frame is captured into this field. after the content of alcbit is read, the ali bit is cleared and a new arbitration lost interrupt can occur. 00 = arbitration lost in the first bit (ms) of identifier ... 11 = arbitration lost in srts bit (rtr bit for standard frame messages) 12 = arbitration lost in ide bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in rtr bit (extended frame only) on arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. at that time, the current bit position of the bit stream processor is captured into the arbitration lost capture register. the content within this register is fixed until the user application has read out its contents once. from now on, the capture mechanism is activated again. 0x table 440. can interrupt and capture register (can1icr - address 0x4004 400c, can2icr - address 0x4004 800c) bit description ?continued bit symbol value function reset value rm set table 441. can interrupt enable register (can1ier - address 0x4004 4010, can2ier - address 0x4004 8010) bit description bit symbol function reset value rm set 0 rie receiver interrupt enable. when the receive buffer status is 'full', the can controller requests the respective interrupt. 0x 1 tie1 transmit interrupt enable for buffer1. when a message has been successfully transmitted out of txb1 or transmit buffer 1 is accessible again (e.g. after an abort transmission command), the can controller requests the respective interrupt. 0x 2 eie error warning interrupt enable. if the error or bus status change (see status register), the can controller requests the respective interrupt. 0x 3 doie data overrun interrupt enable. if the data overrun status bit is set (see status register), the can controller requests the respective interrupt. 0x 4 wuie wake-up interrupt enable. if the sleeping can controller wakes up, the respective interrupt is requested. 0x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 557 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.6 can bus timing register this register controls how various can timings are derived from the apb clock. it defines the values of the baud rate prescaler (brp) and the synchronization jump width (sjw). furthermore, it defines the length of the bit period, the location of the sample point and the number of samples to be taken at each sample point. it can be read at any time but can only be written if the rm bit in canmod is 1. baud rate prescaler the period of the can system clock t scl is programmable and determines the individual bit timing. the can system clock t scl is calculated using the following equation: 5 epie error passive interrupt enable. if the error status of the can controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0x 6 alie arbitration lost interrupt enable. if the can controller has lost arbitration, the respective interrupt is requested. 0x 7 beie bus error interrupt enable. if a bus error has been detected, the can controller requests the respective interrupt. 0x 8 idie id ready interrupt enable. when a can identifier has been received, the can controller requests the respective interrupt. 0x 9 tie2 transmit interrupt enable for buffer2. when a message has been successfully transmitted out of txb2 or transmit buffer 2 is accessible again (e.g. after an abort transmission command), the can controller requests the respective interrupt. 0x 10 tie3 transmit interrupt enable for buffer3. when a message has been successfully transmitted out of txb3 or transmit buffer 3 is accessible again (e.g. after an abort transmission command), the can controller requests the respective interrupt. 0x 31:11 - reserved. read value is undefined, only zero should be written. na table 441. can interrupt enable register (can1ier - address 0x4004 4010, can2ier - address 0x4004 8010) bit description bit symbol function reset value rm set table 442. can bus timing register (can1btr - address 0x4004 4014, can2btr - address 0x4004 8014) bit description bit symbol value function reset value rm set 9:0 brp baud rate prescaler. the apb clock is divi ded by (this value plus one) to produce the can clock. 0x 13:10 - reserved. read value is undefined, only zero should be written. na 15:14 sjw the synchronization jump width is (this value plus one) can clocks. 0 x 19:16 tesg1 the delay from the nominal sync point to the sample point is (this value plus one) can clocks. 1100 x 22:20 tesg2 the delay from the sample point to the next nominal sync point is (this value plus one) can clocks. the nominal can bi t time is (this value plus the value in tseg1 plus 3) can clocks. 001 x 23 sam sampling 0 the bus is sampled once (recommended for high speed buses) 0 x 1 the bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line) 31:24 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 558 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller (7) synchronization jump width to compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width t sjw defines the maximum number of clock cycles a certain bit period may be shortened or lengthened by one re-synchronization: (8) time segment 1 and time segment 2 time segments tseg1 and tseg2 determine the number of clock cycles per bit period and the location of the sample point: (9) (10) (11) 20.7.7 can error warn ing limit register this register sets a limit on tx or rx errors at which an interrupt can occur. it can be read at any time but can only be written if the rm bit in canmod is 1. note that a content change of the error warning limit register is possible only if the reset mode was entered previously. an erro r status change (status register) and an error warning interrupt forced by the new re gister content will not occur until the reset mode is cancelled again. 20.7.8 can status register this read-only register contains three status bytes in which the bits not related to transmission are identical to the corresponding bits in the global status register, while those relating to transmission reflect the status of each of the 3 tx buffers. t scl t cansuppliedclk brp 1 + ?? ? = t sjw t scl sjw 1 + ?? ? = t syncseg t scl = t tseg1 t scl tseg1 1 + ?? ? = t tseg2 t scl tseg2 1 + ?? ? = table 443. can error warning limit register (can1ew l - address 0x4004 4018, can2ewl - address 0x4004 8018) bit description bit symbol function reset value rm set 7:0 ewl during can operation, this value is compared to both the tx and rx error counters. if either of these counter matches this value, the error status (es) bit in cansr is set. 96 10 =0x60 x 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 559 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller the following restriction apply to using the bits in this register: ? if the cpu tries to write to this transmit buffer when the transmit buffer status bit is '0' (locked), the written byte is not accepted and is lost without this being signalled. ? the transmission complete status bit is set '0' (incomplete) whenever the transmission request bit or the self reception request bit is set '1' for this tx buffer. the transmission complete status bit remains '0' until a message is transmitted successfully. table 444. can status register (can1sr - address 0x4 004 401c, can2sr - address 0x4004 801c) bit description bit symbol value function reset value rm set 0 rbs_1 receive buffer status. this bit is identical to the rbs bit in the canxgsr. 0 0 1 dos_1 data overrun status. this bit is identical to the dos bit in the canxgsr. 0 0 2 tbs1_1 transmit buffer status 1. 1 1 0 locked. software cannot access the tx buffer 1 nor write to the corresponding canxtfi, canxtid, canxtda, and canx tdb registers because a message is either waiting for transmission or is in transmitting process. 1 released. software may write a message into the transmit buffer 1 and its canxtfi, canxtid, canxtda, and canxtdb registers. 3 tcs1_1 transmission complete status. 1 x 0 incomplete. the previously requested tran smission for tx buffer 1 is not complete. 1 complete. the previously requested transmission for tx buffer 1 has been successfully completed. 4 rs_1 receive status. this bit is identical to the rs bit in the gsr. 1 0 5 ts1_1 transmit status 1. 1 0 0 idle. there is no transmission from tx buffer 1. 1 transmit. the can controller is transmitting a message from tx buffer 1. 6 es_1 error status. this bit is identical to the es bit in the canxgsr. 0 0 7 bs_1 bus status. this bit is identical to the bs bit in the canxgsr. 0 0 8 rbs_2 receive buffer status. this bit is identical to the rbs bit in the canxgsr. 0 0 9 dos_2 data overrun status. this bit is identical to the dos bit in the canxgsr. 0 0 10 tbs2_2 transmit buffer status 2. 1 1 0 locked. software cannot access the tx buffer 2 nor write to the corresponding canxtfi, canxtid, canxtda, and canx tdb registers because a message is either waiting for transmission or is in transmitting process. 1 released. software may write a message into the transmit buffer 2 and its canxtfi, canxtid, canxtda, and canxtdb registers. 11 tcs2_2 transmission complete status. 1 x 0 incomplete. the previously requested tran smission for tx buffer 2 is not complete. 1 complete. the previously requested transmission for tx buffer 2 has been successfully completed. 12 rs_2 receive status. this bit is identical to the rs bit in the gsr. 1 0 13 ts2_2 transmit status 2. 1 0 0 idle. there is no transmission from tx buffer 2. 1 transmit. the can controller is transmitting a message from tx buffer 2. 14 es_2 error status. this bit is identical to the es bit in the canxgsr. 0 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 560 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.9 can receive frame status register this register defines the characteristics of the current received message. it is read-only in normal operation but can be written for testi ng purposes if the rm bit in canxmod is 1. 15 bs_2 bus status. this bit is identical to the bs bit in the canxgsr. 0 0 16 rbs_3 receive buffer status. this bit is identical to the rbs bit in the canxgsr. 0 0 17 dos_3 data overrun status. this bit is identical to the dos bit in the canxgsr. 0 0 18 tbs3_3 transmit buffer status 3. 1 1 0 locked. software cannot access the tx buffer 3 nor write to the corresponding canxtfi, canxtid, canxtda, and canx tdb registers because a message is either waiting for transmission or is in transmitting process. 1 released. software may write a message into the transmit buffer 3 and its canxtfi, canxtid, canxtda, and canxtdb registers. 19 tcs3_3 transmission complete status. 1 x 0 incomplete. the previously requested transmission for tx buffer 3 is not complete. 1 complete. the previously requested transmission for tx buffer 3 has been successfully completed. 20 rs_3 receive status. this bit is identical to the rs bit in the gsr. 1 0 21 ts3_3 transmit status 3. 1 0 0 idle. there is no transmission from tx buffer 3. 1 transmit. the can controller is transmitting a message from tx buffer 3. 22 es_3 error status. this bit is identical to the es bit in the canxgsr. 0 0 23 bs_3 bus status. this bit is identical to the bs bit in the canxgsr. 0 0 31:24 - reserved, the value read from a reserved bit is not defined. na table 444. can status register (can1sr - address 0x4 004 401c, can2sr - address 0x4004 801c) bit description bit symbol value function reset value rm set table 445. can receive frame status register (can1rfs - address 0x4004 4020, can2rfs - address 0x4004 8020) bit description bit symbol function reset value rm set 9:0 idindex id index. if the bp bit (below) is 0, this value is the zero-based number of the lookup table ram entry at which the acceptance filter matched the received identifier. disabled entries in the standard tables are included in this numbering, but will not be matched. see section 20.17 ? examples of acceptance filter tables and id index values ? on page 588 for examples of id index values. 0x 10 bp if this bit is 1, the current message was received in af bypass mode, and the id index field (above) is meaningless. 0x 15:11 - reserved. the value read from a reserved bit is not defined. na 19:16 dlc the field contains the data length code (dlc) field of the current received message. when rtr = 0, this is related to the number of data bytes available in the canrda and canrdb registers as follows: 0000-0111 = 0 to 7 bytes1000- 1111 = 8 bytes with rtr = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding. 0x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 561 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.9.1 id index field the id index is a 10-bit field in the info regist er that contains the table position of the id look-up table if the currently received message was accepted. the software can use this index to simplify message transfers from t he receive buffer into the shared message memory. whenever bit 10 (bp) of the id index in the canrfs register is 1, the current can message was received in acceptance filter bypass mode. 20.7.10 can receive id entifier register this register contains the identifier field of the current received message. it is read-only in normal operation but can be written for testing purposes if the rm bit in canmod is 1. it has two different formats depending on the ff bit in canrfs. 20.7.11 can receive data register a this register contains the first 1-4 data bytes of the current received message. it is read-only in normal operation, but can be wri tten for testing purposes if the rm bit in canmod is 1. 29:20 - reserved. read value is undefined, only zero should be written. na 30 rtr this bit contains the remote transmission request bit of the current received message. 0 indicates a data frame, in which (if dlc is non-zero) data can be read from the canrda and possibly the canrdb registers. 1 indicates a remote frame, in which case the dlc value identifies the number of data bytes requested to be sent using the same identifier. 0x 31 ff a 0 in this bit indicates that the current received message included an 11-bit identifier, while a 1 indicates a 29-bit identifier. this affects the contents of the canid register described below. 0x table 445. can receive frame status register (can1rfs - address 0x4004 4020, can2rfs - address 0x4004 8020) bit description bit symbol function reset value rm set table 446. can receive identifier register (can1rid - address 0x4004 4024, can2rid - address 0x4004 8024) bit description bit symbol function reset value rm set 10:0 id the 11-bit identifier field of the current received message. in can 2.0a, these bits are called id10-0, while in can 2.0b they?re called id29-18. 0x 31:11 - reserved. the value read from a reserved bit is not defined. na table 447. rx identifier register when ff = 1 bit symbol function reset value rm set 28:0 id the 29-bit identifier field of the current received message. in can 2.0b these bits are called id29-0. 0x 31:29 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 562 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.12 can receive data register b this register contains the 5th through 8th data bytes of the current received message. it is read-only in normal operation, but can be wri tten for testing purposes if the rm bit in canmod is 1. 20.7.13 can transmit fr ame information register when the corresponding tbs bit in cansr is 1, software can write to one of these registers to define the format of the next transm it message for that tx buffer. bits not listed read as 0 and should be written as 0. the values for the reserved bits of the canx tfi register in the transmit buffer should be set to the values expected in the receive buffer for an easy comparison, when using the self reception facility (self test ), otherwise they are not defined. the can controller consist of three transmit buffers. each of them has a length of 4 words and is able to store one complete can message as shown in figure 80 . the buffer layout is subdivided into descript or and data field where the first word of the descriptor field includes the tx frame info that describes the frame format, the data length and whether it is a remote or data fram e. in addition, a tx priority register allows the definition of a certain priority for each transmit message. depending on the chosen frame format, an 11-bit identifier for standard frame format (sff) or an 29-bit identifier for extended frame format (eff) follows. note that unused bits in the tid field have to be defined as 0. the data field in tda and tdb contains up to eight data bytes. table 448. can receive data register a (can1rda - ad dress 0x4004 4028, can2rda - address 0x4004 8028) bit description bit symbol function reset value rm set 7:0 data1 data 1. if the dlc field in canrfs ? 0001, this contains the first data byte of the current received message. 0x 15:8 data2 data 2. if the dlc field in canrfs ? 0010, this contains the first data byte of the current received message. 0x 23:16 data3 data 3. if the dlc field in canrfs ? 0011, this contains the first data byte of the current received message. 0x 31:24 data4 data 4. if the dlc field in canrfs ? 0100, this contains the first data byte of the current received message. 0x table 449. can receive data register b (can1rdb - address 0x4004 402c, can2rdb - address 0x4004 802c) bit description bit symbol function reset value rm set 7:0 data5 data 5. if the dlc field in canrfs ? 0101, this contains the first data byte of the current received message. 0x 15:8 data6 data 6. if the dlc field in canrfs ? 0110, this contains the first data byte of the current received message. 0x 23:16 data7 data 7. if the dlc field in canrfs ? 0111, this contains the first data byte of the current received message. 0x 31:24 data8 data 8. if the dlc field in canrfs ? 1000, this contains the first data byte of the current received message. 0x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 563 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller automatic transmit priority detection to allow uninterrupted streams of transmit messages, the can controller provides automatic transmit priority detection for all transmit buffers. depending on the selected transmit priority mode, internal prioritization is based on the can identifier or a user defined "local priority". if more than one message is enabled for transmission (tr=1) the internal transmit message queue is organized such as that the transmit buffer with the lowest can identifier (tid) or the lowest "local priority" (tx priority) wins the prioritization and is sent first. the result of the internal scheduling process is taken into account short before a new can message is sent on the bus. this is also true after the occurrence of a transmission error and right before a re-transmission. tx dlc the number of bytes in the data field of a message is coded with the data length code (dlc). at the start of a remote frame transmission the dlc is not considered due to the rtr bit being '1 ' (remote). this forces the number of transmitted/received data bytes to be 0. nevertheless, the dlc must be specifie d correctly to avoid bus errors, if two can controllers start a remote frame transmission with the same identifier simultaneously. for reasons of compatibility no dlc > 8 should be used. if a value greater than 8 is selected, 8 bytes are transmitted in the data fr ame with the data length code specified in dlc. the range of the data byte count is 0 to 8 bytes and is coded as follows: (12) table 450. can transmit frame informat ion register (can1tfi[1/2/ 3] - address 0x4004 40[30/40/50], can2tfi[1/2/3] - 0x4004 80[30/40/50]) bit description bit symbol function reset value rm set 7:0 prio if the tpm (transmit priority mode) bit in the canxmod register is set to 1, enabled tx buffers contend for the right to send their messages based on this field. the buffer with the lowest tx priority value wins the prioritization and is sent first. 0x 15:8 - reserved. read value is undefined, only zero should be written. 0 19:16 dlc data length code. this value is sent in the dlc field of the next transmit message. in addition, if rtr = 0, this value controls the number of data bytes sent in the next transmit message, from the canxtda and canxtdb registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes 0x 29:20 - reserved. read value is undefined, only zero should be written. 0 30 rtr this value is sent in the rtr bit of the next transmit message. if this bit is 0, the number of data bytes called out by the dlc field are s ent from the canxtda and canxtdb registers. if this bit is 1, a remote frame is sent, containing a request for that number of bytes. 0x 31 ff if this bit is 0, the next transmit message will be sent with an 11-bit identifier (s tandard frame format), while if it?s 1, the message will be sent with a 29-bit identifier (extended frame format). 0x databytecount dlc =
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 564 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.7.14 can transmit identifier register when the corresponding tbs bit in canxsr is 1, software can write to one of these registers to define the identifier field of the ne xt transmit message. bits not listed read as 0 and should be written as 0. the register assumes two different formats depending on the ff bit in cantfi. in standard frame format messages, the can i dentifier consists of 11 bits (id.28 to id.18), and in extended frame format messages , the can identifier consists of 29 bits (id.28 to id.0). id.28 is the most significant bi t, and it is transmitted first on the bus during the arbitration process. the identifier acts as the message's name, used in a receiver for acceptance filtering, and also determines the bus access priority during the arbitration process. 20.7.15 can transmit data register a when the corresponding tbs bit in cansr is 1, software can write to one of these registers to define the first 1 - 4 data bytes of the next transmit message. the data length code defines the number of transferred data bytes. the first bit transmitted is the most significant bit of tx data byte 1. 20.7.16 can transmit data register b when the corresponding tbs bit in cansr is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. the data length code defines the number of transferred data bytes. the first bit transmitted is the most significant bit of tx data byte 1. table 451. can transfer identifier register (can1tid[1/2 /3] - address 0x4004 40[34/44/54], can2tid[1/2/3] - address 0x4004 80[34/44/54]) bit description bit symbol function reset value rm set 10:0 id the 11-bit identifier to be sent in the next transmit message. 0 x 31:11 - reserved. read value is undefined, only zero should be written. na table 452. transfer identifier register when ff = 1 bit symbol function reset value rm set 28:0 id the 29-bit identifier to be sent in the next transmit message. 0 x 31:29 - reserved. read value is undefined, only zero should be written. na table 453. can transmit data register a (can1tda[1/2/3] - address 0x4004 4 0[38/48/58], can2tda[ 1/2/3] - address 0x4004 80[38/48/58]) bit description bit symbol function reset value rm set 7:0 data1 data 1. if rtr = 0 and dlc ? 0001 in the corresponding canxtfi, this byte is sent as the first data byte of the next transmit message. 0x 15;8 data2 data 2. if rtr = 0 and dlc ? 0010 in the corresponding canxtfi, this byte is sent as the 2nd data byte of the next transmit message. 0x 23:16 data3 data 3. if rtr = 0 and dlc ? 0011 in the corresponding canxtfi, this byte is sent as the 3rd data byte of the next transmit message. 0x 31:24 data4 data 4. if rtr = 0 and dlc ? 0100 in the corresponding canxtfi, this byte is sent as the 4th data byte of the next transmit message. 0x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 565 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.8 can controller operation 20.8.1 error handling the can controllers count and handle transmit and receive errors as specified in can spec 2.0b. the transmit and receive error c ounters are incriminated for each detected error and are decremented when operation is error-free. if the transmit error counter contains 255 and another error occurs, the can controller is forced into a state called bus-off. in this state, the following register bits are set: bs in canxsr, bei and ei in canxir if these are enabled, and rm in canxmod. rm resets and disables much of the can controller. also at this time the transmit error counter is set to 127 and the receive error counter is cleared. software must next clear the rm bit. thereafter the transmit error counter will count down 128 occurrences of the bus free condit ion (11 consecutive recessive bits). software can monitor this countdown by reading the tx error counter. when this countdown is complete, the can c ontroller clears bs and es in canxsr, and sets ei in canxsr if eie in ier is 1. the tx and rx error counters can be written if rm in canxmod is 1. writing 255 to the tx error counter forces the can controller to bus-off state. if bus-off (bs in canxsr) is 1, writing any value 0 through 254 to the tx error counter clears bus-off. when software clears rm in canxmod thereafter, only one bus free condition (11 consecutive recessive bits) is needed before operation resumes. 20.8.2 sleep mode the can controller will enter slee p mode if the sm bit in the can mode regist er is 1, no can interrupt is pending, and there is no ac tivity on the can bus. software can only set sm when rm in the can mode register is 0; it can also set the wuie bit in the can interrupt enable register to enable an interrupt on any wake-up condition. the can controller wakes up (and sets wui in the can interrupt regist er if wuie in the can interrupt enable register is 1) in response to a) a dominant bit on the can bus, or b) software clearing sm in the can mode register. a sleeping can controller that wakes up in response to bus activity is not able to receive an initial message until after it detects bus_free (11 consecutive recessive bits). if an interrupt is pending or the can bus is active when software sets sm, the wake-up is immediate. upon wake-up, software needs to do the following things: 1. write a 1 to the relevant bit(s) in the cansleepclr register. table 454. can transmit data register b (can1tdb[1/2/3] - address 0x4004 40[3c/4c/5c], can2tdb[1/2/3] - address 0x4004 80[3c/4c/5c]) bit description bit symbol function reset value rm set 7:0 data5 data 5. if rtr = 0 and dlc ? 0101 in the corresponding cantfi, this byte is sent as the 5th data byte of the next transmit message. 0x 15;8 data6 data 6. if rtr = 0 and dlc ? 0110 in the corresponding cantfi, this byte is sent as the 6th data byte of the next transmit message. 0x 23:16 data7 data 7. if rtr = 0 and dlc ? 0111 in the corresponding cantfi, this byte is sent as the 7th data byte of the next transmit message. 0x 31:24 data8 data 8. if rtr = 0 and dlc ? 1000 in the corresponding cantfi, this byte is sent as the 8th data byte of the next transmit message. 0x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 566 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 2. write a 0 to the sm bit in the can1mod and/or can2mod register. 3. write a 1 to the relevant bit(s) in t he canwakeflags register. failure to perform this step will preven t subsequent entry into power-down mode. if the device is in deep sleep or power-down mode, can activity will wake up the device if the can activity interrupt is enabled. see section 3.12 ? power control ? . 20.8.3 interrupts each can controller produces 3 interrupt requ ests, receive, transmit, and ?other status?. the transmit interrupt is the or of the transmit interrupts from the three tx buffers. all of the interrupts share one nvic channel. a se parate interrupt is provided for the can activity interrupt. 20.8.4 transmit priority if the tpm bit in the canxmod register is 0, multiple enabled tx buffers contend for the right to send their messages based on the value of their can identifier (tid). if tpm is 1, they contend based on the prio fields in bi ts 7:0 of their canxtfs registers. in both cases the smallest binary value has priority. if two (or three) transmit-enabled buffers have the same smallest value, the lowest-numbered buffer sends first. the can controller selects among multiple enabled tx buffers dynamically, just before it sends each message. 20.9 centralized can registers for easy and fast access, all can controller status bits from each can controller status register are bundled together. each defined byte of the following registers contains one particular status bit from each of the can controllers, in its ls bits. all status registers are read-only and allow byte, half word and word access. 20.9.1 central transmit status register table 455. central transit status register (txsr - address 0x4004 0000) bit description bit symbol description reset value 0 ts1 when 1, the can controller 1 is sendi ng a message (same as ts in the can1gsr). 0 1 ts2 when 1, the can controller 2 is sendi ng a message (same as ts in the can2gsr) 0 7:2 - reserved, the value read from a reserved bit is not defined. na 8 tbs1 when 1, all 3 tx buffers of the can1 controller are available to the cpu (same as tbs in can1gsr). 1 9 tbs2 when 1, all 3 tx buffers of the can2 controller are available to the cpu (same as tbs in can2gsr). 1 15:10 - reserved, the value read from a reserved bit is not defined. na 16 tcs1 when 1, all requested transmissions have been completed successfully by the can1 controller (same as tcs in can1gsr). 1 17 tcs2 when 1, all requested transmissions have been completed successfully by the can2 controller (same as tcs in can2gsr). 1 31:18 - reserved, the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 567 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.9.2 central receive status register 20.9.3 central miscellane ous status register 20.10 global acceptance filter this block provides lookup for received ident ifiers (called acceptance filtering in can terminology) for all the can controllers. it includes a 512 ? 32 (2 kb) ram in which software maintains one to five tables of identifiers. this ram can contain up to 1024 standard identifiers or 512 extended iden tifiers, or a mixture of both types. 20.11 acceptance filter modes the acceptance filter can be put into different modes by setting the according accoff, accbp, and efcan bits in the acceptance filter mode register ( section 20.14.1 ? acceptance filter mode register ? ). during each mode the access to the configuration register and the id look-up table is handled differently. table 456. central receive status register (rxsr - address 0x4004 0004) bit description bit symbol description reset value 0 rs1 when 1, can1 is receiving a message (same as rs in can1gsr). 0 1 rs2 when 1, can2 is receiving a message (same as rs in can2gsr). 0 7:2 - reserved, the value read from a reserved bit is not defined. na 8 rb1 when 1, a received message is available in the can1 controller (same as rbs in can1gsr). 0 9 rb2 when 1, a received message is available in the can2 controller (same as rbs in can2gsr). 0 15:10 - reserved, the value read from a reserved bit is not defined. na 16 dos1 when 1, a message was lost because the preceding message to can1 controller was not read out quickly enough (same as dos in can1gsr). 0 17 dos2 when 1, a message was lost because the preceding message to can2 controller was not read out quickly enough (same as dos in can2gsr). 0 31:18 - reserved, the value read from a reserved bit is not defined. na table 457. central miscellaneous status register (msr - address 0x4004 0008) bit description bit symbol description reset value 0 e1 when 1, one or both of the can1 tx and rx error counters has reached the limit set in the can1ewl register (sam e as es in can1gsr) 0 1 e2 when 1, one or both of the can2 tx and rx error counters has reached the limit set in the can2ewl register (sam e as es in can2gsr) 0 7:2 - reserved, the value read from a reserved bit is not defined. na 8 bs1 when 1, the can1 controller is currently involved in bus activities (same as bs in can1gsr). 0 9 bs2 when 1, the can2 controller is currently involved in bus activities (same as bs in can2gsr). 0 31:10 - reserved, the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 568 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller [1] the whole id look-up table ra m is only word accessible. [2] during the operating mode of the acceptance filter the look-up table can be ac cessed only to disable or enable messages. a write access to all section co nfiguration registers is only possible during the acceptance filter off and bypass mode. read access is allowed in all acceptance filter modes. 20.11.1 acceptance filter off mode the acceptance filter off mode is typically us ed during initialization. during this mode an unconditional access to all registers and to the look-up table ram is possible. with the acceptance filter off mode, can messages ar e not accepted and ther efore not stored in the receive buffers of active can controllers. 20.11.2 acceptance filter bypass mode the acceptance filter bypass mode can be used for example to change the acceptance filter configuration during a running system, e.g. change of identifiers in the id-look-up table memory. during this re-configuration, so ftware acceptance filtering has to be used. it is recommended to use the id ready interrup t (id index) and the receive interrupt (ri). in this mode all can message are accepted a nd stored in the receive buffers of active can controllers. 20.11.3 acceptance filt er operating mode the acceptance filter is in operating mode when neither the accoff nor the accbp in the configuration register is set and the efcan = 0. 20.11.4 fullcan mode the acceptance filter is in operating mode when neither the accoff nor the accbp in the configuration register is set and the efca n = 1. more details on fullcan mode are available in section 20.16 ? fullcan mode ? . 20.12 sections of the id look-up table ram four 12-bit section configuration re gisters (sff_sa, sff_grp_sa, eff_sa, eff_grp_sa) are used to define the boundaries of the different identifier sections in the id-look-up table memory. the fifth 12-bit section configuration register, the end of table address register (endoftable) is used to defin e the end of all identifier sections. the end of table address is also used to assign th e start address of the section where fullcan message objects, if enabled are stored. table 458. acceptance filter modes and access control acceptance filter mode bit accoff bit accbp acceptance filter state id look-up table ram [1] acceptance filter config. registers can controller message receive interrupt off mode 1 0 reset & halted r/w access from cpu r/w access from cpu no messages accepted bypass mode x 1 reset & halted r/w access from cpu r/w access from cpu all messages accepted operating mode and fullcan mode 0 0 running read-only from cpu [2] access from acceptance filter only hardware acceptance filtering
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 569 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.13 id look-up table ram the whole id look-up table ram is only word a ccessible. a write access is only possible during the acceptance filter off or bypa ss mode. read access is allowed in all acceptance filter modes. if standard (11-bit) identifiers are used in the application, at least one of 3 tables in acceptance filter ram must not be empty. if the optional ?fullcan mode? is enabled, the first table contains standard identifiers for which reception is to be handled in this mode. the next table contains individual standard identifiers and the third contains ranges of standard identifiers, for which messages are to be received via the can controllers. the tables of fullcan and individual standard identifiers must be arranged in ascending numerical order, one per halfword, two per word. since each can bus has its own address map, each entry also contains the number of the can controller (scc = 000 (can1) -or scc = 001 (can2)) to which it applies. the table of standard identifier ranges contains paired upper and lower (inclusive) bounds, one pair per word. these must also be arranged in ascending numerical order. table 459. section configuration register settings id-look up table section register value section status fullcan (standard frame format) identifier section sff_sa = 0x000 disabled > 0x000 enabled explicit standard frame format identifier section sff_grp_sa = sff_sa disabled > sff_sa enabled group of standard frame format identifier section eff_sa = sff_grp_sa disabled > sff_grp_sa enabled explicit extended frame format identi fier section eff_grp_sa = eff_sa disabled > eff_sa enabled group of extended frame format identifier section endoftable = eff_grp_sa disabled > eff_grp_sa enabled fig 84. entry in fullcan and indivi dual standard id entifier tables controller # identifier dis able not used 31 15 29 13 26 10 16 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 570 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller the disable bits in standard entries provide a means to turn response to particular can identifiers or ranges of identifiers on and off dynamically. when the acceptance filter function is enabled, only the disable bits in acceptance filter ram can be changed by software. response to a range of standard addresses can be enabled by writing 32 zero bits to its word in ram, and turned off by writing 32 one bits (0xffff ffff) to its word in ram. only the disable bits are actually ch anged. disabled entries must maintain the ascending sequence of identifiers. if extended (29-bit) identifiers are used in th e application, at least one of the other two tables in acceptance filter ram must not be em pty, one for individual extended identifiers and one for ranges of extended identifiers. the table of individual extended identifiers must be arranged in ascending numerical order. the table of ranges of extended identifiers must contain an even number of entries, of the same form as in the individual extended identifier table. like the individual extended table, the extended range must be arranged in ascending numerical order. the first and second (3rd and 4th ?) entries in the table ar e implicitly paired as an inclusive range of extended addresses, such that any received address that falls in the inclusive range is received (accepted). software must maintain the table to consist of such word pairs. there is no facility to receive messages to ex tended identifiers using the fullcan method. five address registers point to the boundarie s between the tables in acceptance filter ram: fullcan standard addresses, standard individual addresses, standard address ranges, extended individual addresses, a nd extended address ranges. these tables must be consecutive in memory. the start of each of the latter four tables is implicitly the end of the preceding table. the end of the extended range table is given in an end of tables register. if the start address of a tabl e equals the start of the next table or the end of tables register, that table is empty. when the receive side of a can controller has received a complete identifier, it signals the acceptance filter of this fact. the acceptance filter responds to this signal, and reads the controller number, the size of the identifier, and the identifier itself from the controller. it then proceeds to search its ram to determi ne whether the message should be received or ignored. fig 85. entry in standard identifier range table fig 86. entry in either extended identifier table controller # lower identifier bound dis able not us ed upper identifier bound dis able not us ed controller # 31 29 26 16 10 0 controller # identifier 31 29 28 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 571 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller if fullcan mode is enabled and the can controller signals that the current message contains a standard identifier, the acceptance f ilter first searches the table of identifiers for which reception is to be done in fullcan mode. otherwise, or if the af doesn?t find a match in the fullcan table, it searches its individual identifier table for the size of identifier signalled by the can controller. if it finds an equal match, the af signals the can controller to retain the message, and provides it with an id index value to store in its receive frame status register. if the acceptance filter does not find a match in the appropriate individual identifier table, it then searches the identifier range table fo r the size of identifier signalled by the can controller. if the af finds a match to a range in the table, it similarly signals the can controller to retain the message, and provides it with an id index value to store in its receive frame status register. if the acceptance filter does not find a match in either the individual or range table for the size of identifier received, it signals the can controller to discard/ignore the received message. 20.14 acceptance filter registers 20.14.1 acceptance filt er mode register the accbp and accoff bits of the acceptance filter mode register are used for putting the acceptance filter into the bypass and off mode. the efcan bit of the mode register can be used to activate a fullcan mode enhanc ement for received 11-bit can id messages. the following restrictions apply to using the bits in this register: ? acceptance filter bypass mode (accbp): by setting the accbp bit in the acceptance filter mode register, the acceptance filter is put into the acceptance filter bypass mode. during bypass mode, the internal state machine of the acceptance filter is reset and halted. all received can messages are accepted, and acceptance filtering can be done by software. ? acceptance filter off mode (accoff): after power-up or hardware reset, the acceptance filter will be in off mode, the accoff bit in the acce ptance filter mode register 0 will be set to 1. t he internal state machine of th e acceptance filter is reset and halted. if not in off mode, setting the accoff bit, either by hardware or by software, will force the accept ance filter into off mode. ? fullcan mode enhancements: a fullcan mo de for received can messages can be enabled by setting the efcan bit in the acceptance filter mode register. table 460. acceptance filter mode register (afmr - address 0x4003 c000) bit description bit symbol value description reset value 0 accoff if accbp is 0, the acceptance filter is not operational. all rx messages on all can buses are ignored. 1 1 accbp all rx messages are accepted on enabled can controllers. software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of lookup table ram in any way other than setting or clearing disable bits in standard identifier entries. when both this bit and accoff are 0, the acceptance filter operates to screen received can identifiers. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 572 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.14.2 section confi guration registers the 10-bit section configuration registers are used for the id look-up table ram to indicate the boundaries of the different sections for explicit and group of can identifiers for 11-bit can and 29-bit can identifiers, respectively. the 10-bit wide section configuration registers allow the use of a 512x 32 (2 kb) look-up table ram. the whole id look-up table ram is only word accessible. a ll five section configuration registers contain apb addresses for the acceptance filter ra m and do not include the apb base address. a write access to all section co nfiguration registers is only possible during the acceptance filter off and bypass modes. read access is allowed in all acceptance filter modes. 20.14.3 standard frame indivi dual start address register write access to the look-up table section configuration registers are possible only during the acceptance filter bypass mode or the acceptance filter off mode. 20.14.4 standard frame gr oup start address register write access to the look-up table section configuration registers are possible only during the acceptance filter bypass mode or the acceptance filter off mode. 2 efcan fullcan mode 0 0 software must read all messages for all enabled ids on all enabled can buses, from the receiving can controllers. 1 the acceptance filter itself will take care of receiving and storing messages for selected standard id values on selected can buses. see section 20.16 ? fullcan mode ? on page 577 . 31:3 - reserved. read value is undefined, only zero should be written. na table 460. acceptance filter mode register (afmr - address 0x4003 c000) bit description bit symbol value description reset value table 461. standard frame individual start address register (sff_sa - address 0x4003 c004) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 10:2 sff_sa the start address of the table of individual standard identifiers in af lookup ram. if the table is empty, write the same value in this register and the sff_grp_sa register described below. for compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. if the efcan bit in the afmr is 1, this value also indicates the size of the table of standard ids which the acce ptance filter will sear ch and (if found) automatically store received messages in acceptance filter ram. 0 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 573 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.14.5 extended frame start address register write access to the look-up table section configuration registers are possible only during the acceptance filter bypass mode or the acceptance filter off mode. 20.14.6 extended frame gr oup start address register write access to the look-up table section configuration registers are possible only during the acceptance filter bypass mode or the acceptance filter off mode. 20.14.7 end of af tables register write access to the look-up table section configuration registers are possible only during the acceptance filter bypass mode or the acceptance filter off mode. table 462. standard frame group start address register (sff_grp_sa - address 0x4003 c008) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 11:2 sff_grp_sa the start address of the table of grouped standard identifiers in af lookup ram. if the table is empty, write the same value in this register and the eff_sa register described below. the largest value that shoul d be written to this register is 0x800, when only the standard individual table is used, and the last word (address 0x7fc) in af lookup table ram is used. for compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. 0 31:12 - reserved. read value is undefined, only zero should be written. na table 463. extended frame start address register (eff_sa - address 0x4003 c00c) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 10:2 eff_sa the start address of the table of individual extended identifiers in af lookup ram. if the table is empty, write the same value in this register and the eff_grp_sa register described below. the largest value that should be written to this register is 0x800, when both extended tables are empty and the last word (address 0x7fc) in af lookup table ram is used. for compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register. 0 31:11 - reserved. read value is undefined, only zero should be written. na table 464. extended frame group start address register (eff_grp_sa - address 0x4003 c010) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 11:2 eff_grp_sa the start address of the table of grouped extended identifiers in af lookup ram. if the table is empty, write the same value in this register and the endoftable register described below. the largest value that shoul d be written to this register is 0x800, when this table is empty and the last word (address 0x7fc) in af lookup table ram is used. for compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. 0 31:12 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 574 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.14.8 status registers the look-up table error status registers, the error addresses, and the flag register provide information if a programming error in the lo ok-up table ram during the id screening was encountered. the look-up table error address and flag register have only read access. if an error is detected, the luterror flag is se t, and the luterroraddr register provides the information under which address during an id screening an error in the look-up table was encountered. any read of the luterroraddr filter block can be used for a look-up table interrupt. 20.14.9 lut error address register 20.14.10 lut error register table 465. end of af tables register (endoftable - address 0x4003 c014) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 11:2 endoftable the address above the la st active address in t he last active af t able. for compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. if the efcan bit in the afmr is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7fc) in af lookup table ram to be used. if the efcan bit in the afmr is 1, this value marks the start of the area of acceptance filter ram, into which the acceptance filter will automatically receive messages for selected ids on selected can buses. in this case, the maximum value that should be written to this register is 0x800 minus 6 time s the value in sff_sa. this allows 12 bytes of message storage between this address and the end of acceptance filter ram, for each standard id that is specified between the start of acceptance filter ram, and the next active af table. 0 31:12 - reserved. read value is undefined, only zero should be written. na table 466. lut error address register (luterrad - addre ss 0x4003 c018) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 10:2 luterrad it the lut error bit (below) is 1, this read-only field contains the address in af lookup table ram, at which the acceptance filter encountered an error in the content of the tables. 0 31:11 - reserved. read value is undefined, only zero should be written. na table 467. lut error register (luterr - address 0x4003 c01c) bit description bit symbol description reset value 0 luterr this read-only bit is set to 1 if the accept ance filter encounters an error in the content of the tables in af ram. it is cleared when software reads the luterrad register. this condition is ored with the other can interrupts from the can controllers, to produce the request that is connected to the nvic. 0 31:1 - reserved, the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 575 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.14.11 global fullcaninterr upt enable register a write access to the global fullcan interrup t enable register is only possible when the acceptance filter is in the off mode. 20.14.12 fullcan interrupt and capture registers for detailed description on these two registers, see section 20.16.2 ? fullcan interrupts ? . 20.15 configuration and search algorithm the can identifier look-up table memory can contain explicit identifiers and groups of can identifiers for standard and extended ca n frame formats. they are organized as a sorted list or table with an increasing orde r of the source can channel (scc) together with can identifier in each section. scc value equals can_controller - 1, i.e., scc = 0 matches can1 and scc = 1 matches can2. every can identifier is linked to an id index number. in case of a can identifier match, the matching id index is stored in the identifier index of the frame status register (canrfs) of the according can controller. 20.15.1 acceptance filter search algorithm the identifier screening process of the acceptance filter starts in the following order: 1. fullcan (standard frame format) identifier section 2. explicit standard frame format identifier section table 468. global fullcan enable register (fcanie - address 0x4003 c020) bit description bit symbol description reset value 0 fcanie global fullcan interrupt enable. when 1, this interrupt is enabled. 0 31:1 - reserved. read value is undefined, only zero should be written. na table 469. fullcan interrupt and capture register 0 (fcanic0 - address 0x4 003 c024) bit description bit symbol description reset value 31:0 intpnd fullcan interrupt pending 0 = fullcan interrupt pending bit 0. 1 = fullcan interrupt pending bit 1. ... 31 = fullcan interrupt pending bit 31. 0 table 470. fullcan interrupt and capture register 1 (fcanic1 - address 0x4 003 c028) bit description bit symbol description reset value 31:0 intpnd32 fullcan interrupt pending bit 32. 0 = fullcan interrupt pending bit 32. 1 = fullcan interrupt pending bit 33. ... 31 = fullcan interrupt pending bit 63. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 576 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 3. group of standard frame format identifier section 4. explicit extended frame fo rmat identifier section 5. group of extended frame format identifier section note: only activated sections will ta ke part in the screening process. in cases where equal message identifiers of same frame format are defined in more than one section, the firs t match will end the screening process for this identifier. for example, if the same source can channel in conjunction with the identifier is defined in the fullcan, the explicit standard frame format and the group of standard frame format identifier sections, th e screening will alread y be finished with the match in the fullcan section. in the example of figure 87 , identifiers with their source can channel have been defined in the fullcan, explicit and group of standard frame format identifier sections. the identifier 0x5a of the can controller 1 with the source can channel scc = 0, is defined in all three sections. with this configuration incoming can messages on can controller 1 with a 0x5a identifier will find a match in the fullcan section. it is possible to disable the ?0x5a identifier? in the fullcan section. with that, the screening process would be finished with the match in the explicit identifier section. the first group in the group identifier section has been defined such that incoming can messages with identifiers of 0x5a up to 0x 5f are accepted on can controller 1 with the source can channel scc = 0. as stated above, the identifier 0x5a would find a match fig 87. id look-up table example explaining the search algorithm scc = 0 scc scc = 0 scc scc scc scc scc = 0 scc scc 0 fullcan explicit standard frame format identifier section explicit standard frame format identifier section group of standard frame format identifier section id = 0x5a ... ... ... ... ... ... id = 0x5a id = 0x5a ... scc scc scc scc scc = 0 scc scc ... scc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 message disable bit id = 0x5a ... ... ... ... ... id = 0x5f ... message disable bit index 0, 1 index 2, 3 index 4, 5 index 6, 7 index 8, 9 index 10, 11 index 12, 13 index 14 index 15
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 577 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller already in the fullcan or in the explicit id entifier section if enabled. the rest of the defined identifiers of this grou p (0x5b to 0x5f) will find a ma tch in this gr oup identifier section. this way the user can switch dynamically between different filter modes for same identifiers. 20.16 fullcan mode the fullcan mode is based on capabilities provided by the can gateway module. this block uses the acceptance filter to provide filtering for both can channels. the concept of the can gateway block is mainly based on a basiccan functionality. this concept fits perfectly in systems where a gateway is used to transfer messages or message data between different can channel s. a basiccan device is generating a receive interrupt whenever a can message is accepted and received. software has to move the received message out of the receive buffer from the according can controller into the user ram. to cover dashboard like applications where t he controller typically receives data from several can channels for further processing, the can gateway block was extended by a so-called fullcan receive function. this ad ditional feature uses an internal message handler to move received fu llcan messages from the receive buffer of the according can controller into the fullcan message object data space of look-up table ram. when fullcan mode is enabled, the acceptance filter itself takes care of receiving and storing messages for selected standard id valu es on selected can buses, in the style of ?fullcan? controllers. in order to set this bit and use this mode, tw o other conditions must be met with respect to the contents of acceptance filter ram and the pointers into it: ? the standard frame individual start address register (sff_sa) must be greater than or equal to the number of ids for which automatic receive storage is to be done, times two. sff_sa must be rounded up to a multiple of 4 if necessary. ? the endoftable register must be less than or equal to 0x800 minus 6 times the sff_sa value, to allow 12 bytes of message storage for each id for which automatic receive storage will be done. when these conditions ar e met and efcan is set: ? the area between the start of acceptance filter ram and the sff_sa address, is used for a table of individual standard ids and can controller/bus identification, sorted in ascending order and in the same format as in the individual standard id table (see figure 84 ? entry in fullcan and individual standard identifier tables ? on page 569 ). entries can be marked as ?disabled? as in the other standard tables. if there are an odd number of ?fullcan? id?s, at least one entry in this table must be so marked. ? the first (sff_sa)/2 idindex values are a ssigned to these automatically-stored id?s. that is, idindex values stored in the rx fr ame status register, for ids not handled in this way, are increased by (sff_sa)/2 compar ed to the values they would have when efcan is 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 578 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? when a standard id is received, the acceptan ce filter searches this table before the standard individual and group tables. ? when a message is received for a controller and id in this table, the acceptance filter reads the received message out of the can controller and stores it in acceptance filter ram, starting at (endoftable) + its idindex*12. ? the format of such messages is shown in table 471 . 20.16.1 fullcan message layout the ff, rtr, and dlc fields are as described in table 445 . since the fullcan message object section of the look-up table ram can be accessed both by the acceptance filter and the cpu, there is a method for insuring that no cpu reads from fullcan message object occurs while the acceptance filter hardware is writing to that object. for this purpose the acceptance filter uses a 3-state semaphore, encoded with the two semaphore bits sem1 and sem0 (see table 471 ? format of automatically stored rx messages ? ) for each message object. this mechanism provides the cpu with information about the current state of the acceptance filter activity in the fullcan message object section. the semaphore operates in the following manner: prior to writing the first data byte into a message object, th e acceptance filter will write the frameinfo byte into the according buffer location with sem[1:0] = 01. after having written the last data byte into the message object, the accept ance filter will update the semaphore bits by setting sem[1:0] = 11. before reading a message object, the cpu should read sem[1:0] to determine the current state of the acceptance filter activity therei n. if sem[1:0] = 01, then the acceptance filter is currently active in this message object. if sem[1:0] = 11, then the message object is available to be read. before the cpu begins reading from the message object, it should clear sem[1:0] = 00. table 471. format of automatically stored rx messages address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0f f r t r 0000 sem [1:0] 0000 dlc 00000 id.28 ... id.18 +4 rx data 4 rx data 3 rx data 2 rx data 1 +8 rx data 8 rx data 7 rx data 6 rx data 5 table 472. fullcan semaphore operation sem1 sem0 activity 0 1 acceptance filter is updating the content 1 1 acceptance filter has finished updating the content 0 0 cpu is in process of reading from the acceptance filter
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 579 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller when the cpu is finished reading, it can check sem[1:0] again. at the time of this final check, if sem[1:0] = 01 or 11, then the acceptance filter has updated the message object during the time when the cpu reads were taking place, and the cpu should discard the data. if, on the other hand, sem[1:0] = 00 as expected, then valid data has been successfully read by the cpu. figure 88 shows how software should use the sem field to ensure that all three words read from the message are all from the same received message.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 580 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller fig 88. semaphore procedure for reading an auto-stored message read 1st word sem == 01? sem == 11? clear sem, write back 1st word read 2nd and 3rd words read 1st word sem == 00? start most recently read 1st, 2nd, and 3rd words are from the same message this message has not been received since last check
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 581 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.2 fullcan interrupts the can gateway block contains a 2 kb id look-up table ram. with this size a maximum number of 146 fullcan objects can be defined if the whole look-up table ram is used for fullcan objects only. only the first 64 fullcan objects can be configured to participate in the interrupt sc heme. it is still poss ible to define more than 64 fullcan objects. the only difference is, that the remaining fullcan objects will not provide a fullcan interrupt. the fullcan interrupt register -set contains interrupt flags (intpndx) for (pending) fullcan receive interr upts. as soon as a fullcan message is received, the according interrupt bit (intpndx) in the fc an interrupt register gets asserted. in case that the global fullcan interrupt enable bit is set, the fullcan receive interrupt is passed to the vectored interrupt controller. application software has to solve the following: 1. index/object number calculation based on the bit position in the fcanic interrupt register for more than one pending interrupt. 2. interrupt priority handling if more than one fullcan receive interrupt is pending. the software that covers the interrupt priority handling has to assign a receive interrupt priority to every fullcan object . if more than one interrupt is pending, then the software has to decide, which received fullcan object has to be served next. to each fullcan object a new fullcan interr upt enable bit (fcanintxen) is added, so that it is possible to enable or disable fullcan interrupts for each object individually. the new message lost flag (msglstx) is introd uced to indicate whether more than one fullcan message has been received since last time this message object was read by the cpu. the interrupt enable and the message lost bits reside in the existing look-up table ram. 20.16.2.1 fullcan message interrupt enable bit in figure 89 8 fullcan identifiers with their source can channel are defined in the fullcan, section. the new introduced fullcan message interrupt enable bit can be used to enable for each fullcan message an interrupt.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 582 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.2.2 message lost bit and can channel number figure 90 is the detailed layout structure of on e fullcan message stored in the fullcan message object section of the look-up table. the new message lost bit (msglst) is introd uced to indicate whether more than one fullcan message has been received since last time this message object was read. for more information the can source channel (scc) of the received fullcan message is added to message object. fig 89. fullcan section example of the id look-up table 0 fullcan explicit standard frame format identifier section 11-bit can id scc 0 message disable bit message disable bit index 0, 1 index 2, 3 index 4, 5 index 6, 7 0 scc 11-bit can id 1234567890 1 11 2345678901234567890 2 3 0 11-bit can id scc 0 scc 11-bit can id 0 11-bit can id scc 0 scc 11-bit can id 0 11-bit can id scc 0 scc 11-bit can id new: fullcan message interrupt enable bit new: fullcan message interrupt enable bit fig 90. fullcan message object layout 31 0 rx data 4 rx data 3 rx data 2 rx data 1 rx data 8 rx data 7 rx data 6 rx data 5 9 7 8 15 16 10 23 24 msg_objaddr + 0 apb base + f f rx dlc r t r s e m 0 id.2 8 id.1 8 ............................ msg_objaddr + 4 msg_objaddr + 8 s e m 1 new: fullcan message lost bit scc new: can source channel un- used unused unused
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 583 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.2.3 setting the interrupt pending bits (intpnd 63 to 0) the interrupt pending bit (intpndx) gets asserted in case of an accepted fullcan message and if the interrupt of the accord ing fullcan object is enabled (enable bit fcanintxen) is set). during the last write access from the data storage of a fullcan message object the interrupt pending bit of a fullcan object (intpndx) gets asserted. 20.16.2.4 clearing the interrupt pending bits (intpnd 63 to 0) each of the fullcan interrupt pending reques ts gets cleared when the semaphore bits of a message object are cleared by software (arm cpu). 20.16.2.5 setting the message lost bit of a fullcan message object (msglost 63 to 0) the message lost bit of a fullcan message objec t gets asserted in ca se of an accepted fullcan message and when the fullcan interrupt of the same object is asserted already. during the first write access from the data storage of a fullcan message object the message lost bit of a fullcan object (msglostx) gets asserted if the interrupt pending bit is set already. 20.16.2.6 clearing the message lost bit of a fullcan message object (msglost 63 to 0) the message lost bit of a fullcan message object gets cleared when the fullcan interrupt of the same object is not asserted. during the first write access from the data storage of a fullcan message object the message lost bit of a fullcan object (msglostx) gets cleared if the interrupt pending bit is not set. 20.16.3 set and cl ear mechanism of the fullcan interrupt special precaution is needed for the built-in set and clear mechanism of the fullcan interrupts. the following text illustrates how the already ex isting semaphore bits (see section 20.16.1 ? fullcan message layout ? for more details) and how the new introduced features (intpndx, msglst x) will behave. 20.16.3.1 scenario 1: normal case, no message lost figure 91 below shows a typical ?normal? sce nario in which an accepted fullcan message is stored in the fullcan message ob ject section. after storage the message is read out by software (arm cpu).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 584 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.3.2 scenario 2: message lost in this scenario a first fullcan message is stored and read out by software (1 st object write and read). in a second course a second message is stored (2 nd object write) but not read out before a third message gets stored (3 rd object write). since the fullcan interrupt of that object (intpndx) is already assert ed, the message lost signal gets asserted. fig 91. normal case, no messages lost 01 11 intpndx semaphore bits look-up table access 00 msglostx message handler access arm processor access read sem read d2 read d1 clear sem read sem write sem write d2 write d1 write id, sem fig 92. message lost 01 11 01 11 11 00 1st object write 2nd object write 1st object read 3rd object write intpndx semaphore bits look-up table access msglostx message handler access arm processor access read sem read d2 read d1 clear sem read sem write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 585 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.3.3 scenario 3: message gets overwritten indicated by semaphore bits this scenario is a special case in which the lost message is indicated by the existing semaphore bits. the scenario is entered, if during a software read of a message object another new message gets stored by the message handler. in this case, the fullcan interrupt bit gets set for a second time with the 2 nd object write. 20.16.3.4 scenario 3.1: message gets overwritten indicated by semaphore bits and message lost this scenario is a sub-case to scenario 3 in which the lost message is indicated by the existing semaphore bits and by message lost. fig 93. message gets overwritten 01 11 01 11 00 00 1st object write 2nd object write 2nd object read 1st object read interrupt service routine intpndx semaphore bits look-up table access msglostx message handler access arm processor access read sem read d2 read d1 clear sem read sem write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem read sem read d2 read d1 clear sem
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 586 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.3.5 scenario 3.2: message gets overwritten indicated by message lost this scenario is a sub-case to scenario 3 in which the lost message is indicated by message lost. fig 94. message overwritten indicated by semaphore bits and message lost 01 11 01 11 00 00 1st object write 2nd object write 2nd object read interrupt service routine intpndx semaphore bits look-up table access msglostx message handler access arm processor access clear sem write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem read sem read d2 clear sem read sem read d1 read sem read d2 read d1 1st object read
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 587 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.16.3.6 scenario 4: clearing message lost bit this scenario is a special case in which the lost message bit of an object gets set during an overwrite of a none read message object (2 nd object write). the subsequent read out of that object by software (1 st object read) clears the pending interrupt. the 3 rd object write clears the message lost bit. every ?wri te id, sem? clears message lost bit if no pending interrupt of that object is set. fig 95. message overwritten indicated by message lost intpndx semaphore bits look-up table access msglostx message handler access arm processor access write sem write d2 write d1 write id, sem 01 11 01 11 00 1st object write 2nd object write 1st object read interrupt service routine 01 11 3rd object write write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem read sem read d2 read d1 read sem clear sem
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 588 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.17 examples of ac ceptance filter tables and id index values 20.17.1 example 1: only one section is used sff_sa < endoftable or sff_grp_sa < endoftable or eff_sa < endoftable or eff_grp_sa < endoftable the start address of a section is lower than the end address of all programmed can identifiers. 20.17.2 example 2: al l sections are used sff_sa < sff_grp_sa and sff_grp_sa < eff_sa and eff_sa < eff_grp_sa and eff_grp_sa < endoftable in cases of a section not being used, the start address has to be set onto the value of the next section start address. 20.17.3 example 3: more than one but not all sections are used if the sff group is not used, the start addr ess of the sff group section (sff_grp_sa register) has to be set to the same value of th e next section start address, in this case the start address of the explicit sff section (sff_sa register). fig 96. clearing message lost message handler access arm processor access 01 11 01 11 11 00 1st object write 2nd object write 1st object read 3rd object write write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem write sem write d2 write d1 write id, sem read sem read d2 read d1 read sem clear sem intpndx semaphore bits look-up table access msglostx
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 589 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller in cases where explicit identif iers as well as groups of the identifiers are programmed, a can identifier search has to start in the explicit identifier sectio n first. if no match is found, it continues the search in the group of identifi er section. by this order it can be guaranteed that in case where an explicit identifier match is found, the succeeding software can directly proceed on this certain message wher eas in case of a group of identifier match the succeeding soft ware needs more steps to identify the message. 20.17.4 configur ation example 4 suppose that the five acceptance filter addre ss registers contain the values shown in the third column below. in this case each table contains the decimal number of words and entries shown in the next two columns, and the id index field of the canrfs register can return the decimal values shown in the co lumn id indexes for can messages whose identifiers match the entries in that table. 20.17.5 configur ation example 5 figure 97 below is a more detailed and graphic example of the address registers, table layout, and id index values. it shows: ? a standard individual table starting at the start of acceptance filter ram and containing 26 identifiers, followed by: ? a standard group table containing 12 ranges of identifiers, followed by: ? an extended individual table containing 3 identifiers, followed by: ? an extended group table containi ng 2 ranges of identifiers. table 473. example of acceptance filter tables and id index values table register value # words # entire id indexes standard individual sff_sa 0x040 8 10 16 10 0-15 10 standard group sff_grp_sa 0x060 4 10 4 10 16-19 10 extended individual eff_sa 0x070 8 10 16 10 20-55 10 extended group eff_grp_sa 0x100 8 10 16 10 56-57 10 endoftable 0x110
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 590 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.17.6 configur ation example 6 the table below shows which sections and t herefore which types of can identifiers are used and activated. the id-look-up table configuration of this example is shown in figure 98 . fig 97. detailed example of acceptance filter tables and id index values sff_sa 000 d := 000 h := 0 0000 0000 b expli cit sff table lower_boundary 3 4 upper_boundary lower_boundary 3 lower_boundary 3 5 upper_boundary 6 upper_boundary 01 3 2 0 1 2 3 22 23 24 25 26 d 22 23 25 24 2 6 34 d 35 d 36 d 38 d 39 d 38 39 lower_boundary 41 upper_boundary lower_boundary 42 upper_boundary 41 d 42 d group sff tab le explicit eff table g roup eff table sff_grp_sa 52 d := 034 h := 0 0011 0100 b eff_sa 100 d := 064 h := 0 0110 0100 b eff_grp_sa 112 d := 070 h := 0 0111 0000 b endoftable 128 d := 080 h := 0 1000 0000 b apb base + address 00d = 00h 04d = 04h 44d = 2ch 48d = 30h 52d = 34h 84d = 54h 88d = 58h 92d = 5ch 100d = 64h 104d = 68h 112d = 70h 116d = 74h 120d = 78h 124d = 7ch column_lower column_upper look-up table ram id index #
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 591 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller explicit standard frame format identifier section (11-bit can id): the start address of the explicit standard fr ame format section is defined in the sff_sa register with the value of 0x00. the end of this section is defined in the sff_grp_sa register. in the explicit standard frame form at section of the id look-up table two can identifiers with their source can channels (scc) share one 32-bit word. not used or disabled can identifiers can be marked by setting the message disable bit. group of standard frame format identifier section (11-bit can id): the start address of the group of standard frame format section is defined with the sff_grp_sa register with the value of 0x10. the end of this section is defined with the eff_sa register. in the group of standard frame format section two can identifiers with the same source can channel (scc) share one 32-bit word and represent a range of can identifiers to be accepted. bit 31 down to 16 represents the lower boundary and bit 15 down to 0 represents the upper boundary of the range of can identifiers. all identifiers within this range (including the boundary iden tifiers) will be accepted. a whole group can be disabled and not used by the acceptance filter by setting the message disable bit in the upper and lower boundary identifier. to provide memory space for four groups of standard frame format identifiers, the eff_sa register value is set to 0x20. the identifier group with the index 9 of this secti on is not used and therefore disabled. explicit extended frame format identifier section (29-bit can id, figure 98 ) the start address of the explicit extended frame format section is defined with the eff_sa register with the value of 0x20. the end of this section is defined with the eff_grp_sa register. in the explicit exte nded frame format section only one can identifier with its source can channel (scc) is programmed per address line. to provide memory space for four explicit extended fr ame format identifiers, the eff_grp_sa register value is set to 0x30. group of extended frame format identifier section (29-bit can id, figure 98 ) the start address of the gr oup of extended frame format is defined with the eff_grp_sa register with the value of 0x30. the end of this section is defined with the end of table address register (endoftable) . in the group of extended frame format section the boundaries are programmed with a pair of address lines; the first is the lower boundary, the second the upper boundary. to provide memory space for two groups of extended frame format identifiers, the endo ftable register value is set to 0x40. table 474. used id-look-up table sections id-look-up table section status fullcan not activated explicit standard frame format activated group of standard frame format activated explicit extended frame format activated group of extended frame format activated
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 592 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.17.7 configur ation example 7 the table below shows which sections and t herefore which types of can identifiers are used and activated. the id-look-up table configuration of this example is shown in figure 99 . this example uses a typical configuration in which fullcan as well as explicit standard frame format messages are defined. as described in section 20.15.1 ? acceptance filter search algorithm ? , acceptance filtering takes place in a certain order. with the enabled fullcan section, the identifier screening proces s of the acceptance filter starts always in the fullcan section first, before it continues with the rest of enabled sections.e disabled. fig 98. id look-up table conf iguration example (no fullcan) 11 0 scc 11 0 scc 0 scc 0 1 scc 8 0 scc 6 0 scc 0 scc ... ... 1 explicit standard frame format identifier section group of standard frame format identifier section sff_grp_sa = 0x10 sff_sa = 0x00 2 0 scc 3 0 scc disabled, 7 8 0 scc disabled, 9 disabled, 9 1 scc 1 scc message disable bit message disable bit 12 scc endoftable = 0x40 explicit extended frame format identifier section eff_sa = 0x20 group of extended frame format identifier section eff_grp_sa = 0x30 13 scc 15 scc 16 scc 16 scc 17 scc 17 scc group 8 disabled group 9 group 11 group 16 group 17 msb id28 lsb id18 0 scc 4 0 scc 5 10 10 1 scc 1 scc 14 scc group 10 index msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 lsb id0 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 lsb id0 lsb id0 lsb id0 lsb id0 lsb id0 lsb id0 lsb id0 lsb id18 table 475. used id-look-up table sections id-look-up table section status fullcan activated and enabled explicit standard frame format activated group of standard frame format not activated explicit extended frame format not activated group of extended frame format not activated
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 593 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller fullcan explicit standard frame format identifier section (11-bit can id) the start address of the fullcan explicit standard frame format identifier section is (automatically) set to 0x00. the end of this sect ion is defined in the sff_sa register. in the fullcan id section only identifi ers of fullcan object are stor ed for acceptance filtering. in this section two can identifiers with their source can channels (scc) share one 32-bit word. not used or disabled can ident ifiers can be marked by setting the message disable bit. the fullcan object data for each defined identifier can be found in the fullcan message object section. in case of an identifier match during the acceptance filter process, the received fullcan message object data is moved from the receive buffer of the appropriate can controller into the fullcan message object section. to provide memory space for eight fullcan, exp licit standard frame format identifiers, the sff_sa register value is set to 0x10. the identifier with the index 1 of this section is not used and therefore disabled. explicit standard frame format identifier section (11-bit can id) the start address of the explicit standard fr ame format section is defined in the sff_sa register with the value of 0x10. the end of this section is defined in the end of table address register (endoftable). in the explic it standard frame format section of the id look-up table two can identifiers with their source can channel (scc) share one 32-bit word. not used or disabled can identifiers can be marked by setting the message disable bit. to provide memory space for eight explicit standard frame format identifiers, the endoftable register value is set to 0x20. fullcan message object data section the start address of the fullcan message object data section is defined with the endoftable register. the number of enabled fu llcan identifiers is limited to the available memory space in the fullcan message object data section. each defined fullcan message needs three address lines for the me ssage data in the fullcan message object data section. the fullcan message object section is organized in that way, that each index number of the fullcan identifier section corresponds to a message object number in the fullcan message object section.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 594 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller 20.17.8 look-up table pr ogramming guidelines all identifier sections of the id look-up tabl e have to be programmed in such a way, that each active section is organized as a sorted list or table with an increasing order of the source can channel (scc) together with can identifier in each section. scc value equals can_controller - 1, i.e., scc = 0 matches can1 and scc = 1 matches can2. in cases, where a syntax error in the id lo ok-up table is encountered, the look-up table address of the incorrect line is made ava ilable in the look-up table error address register (luterrad). the reporting process in the look-up table error address register (luterrad) is a ?run-time? process. only those address lines with syntax error are reported, which were passed through the accept ance filtering process. the following general rules for programming the look-up table apply: fig 99. id look-up table configuration example (fullcan activated and enabled) 15 0 scc 0 14 0 scc 0 ... ... fullcan explicit standard frame format identifier section explicit standard frame format identifier section sff_sa = 0x10 ff rtr sem dlc can-id fullcan message object section section endoftable = sff_grp_sa = eff_sa = eff_grp_sa = 0x20 rxdata 4, 3, 2, 1 rxdata 8, 7, 6, 5 no message data, disabled. no message data, disabled. no message data, disabled. ff rtr sem dlc can-id rxdata 4, 3, 2, 1 rxdata 8, 7, 6, 5 message object data 0 message object data 1 message object data 2 index fullcan interrupt enable bit fullcan interrupt enable bit 0 0 scc 0 disabled, 1 1 scc 1 2 0 scc 1 4 0 scc 1 6 0 scc 1 3 0 scc 0 5 0 scc 0 7 0 scc 0 12 0 scc 0 11 0 scc 0 13 0 scc 0 10 0 scc 0 8 0 scc 0 9 0 scc 0 message disable bit message disable bit msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 msb id28 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18 lsb id18
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 595 of 942 nxp semiconductors UM10562 chapter 20: lpc408x/407x can controller ? each section has to be organized as a sorted list or table with an increasing order of the source can channel (scc) in conjunction with the can identifier (there is no exception for disabled identifiers). ? the upper and lower bound in a group of id entifiers definition has to be from the same source can channel. ? to disable a group of identifiers the mess age disable bit has to be set for both, the upper and lower bound.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 596 of 942 21.1 basic configuration the three ssp interfaces, ssp0, ssp1, and ssp2 are configur ed using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcssp0 to enable ssp0 and bit pcssp1 to enable ssp1. remark: on reset, ssp interfaces 0 and 1 are enabled (pcssp0/1 = 1), while ssp2 is disabled (pcssp2 = 0). 2. peripheral clock: the ssps operate from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . in master mode, the clock must be scaled down (see section 21.6.5 ). 3. pins: select the ssp pins and pin mode s through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: interrupts are enabled in the ssp0imsc register for ssp0 and ssp1imsc register for ssp1 table 483 . interrupts are enabled in th e nvic using the appropriate interrupt set enab le register, see ta b l e 5 0 . 5. initialization: there are two control r egisters for each of the ssp ports to be configured: ssp0cr0 and ssp0cr1 fo r ssp0, ssp1cr0 and ssp1cr1 for ssp1, ssp2cr0 and ssp2cr1 for ssp2. see section 21.6.1 and section 21.6.2 . 6. dma: the rx and tx fifos of the ssp in terfaces can be connected to the gpdma controller (see section 21.6.10 ). for gpdma system connections, see table 692 . 21.2 features ? compatible with motorola spi, 4-wire ti ssi, and national semiconductor microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8 frame fifos for both transmit and receive. ? 4 to 16 bit data frame. ? dma transfers supported by gpdma. 21.3 description the ssp is a synchronous serial port (ssp) controller capable of operation on a spi, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. data transfers are in principle full duplex, with frames of 4 to 16 bits of data flowing from the master to the slave and from th e slave to the master. in practice it is often the case that only one of these data flows carries meaningful data. three synchronous serial port controlle rs are provided -- ssp0, ssp1, and ssp2. UM10562 chapter 21: lpc408x/4 07x ssp interfaces rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 597 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.4 pin descriptions table 476. ssp pi n descriptions pin name type interface pin name/function pin description spi ssi microwire sck0/1/2 i/o sck clk sk serial clock. sck/clk/sk is a clock signal used to synchronize the transfer of data. it is driven by the master and received by the slave. when the spi interface is used, the clock is programmable to be active-high or active-low, otherwise it is always active-high. sck only switches during a data transfer. any other time, the sspn interface either hol ds it in its inacti ve state, or does not drive it (leaves it in high-impedance state). when this pin is an input, each level on this pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. ssel0/1/2 i/o ssel fs cs frame sync/slave select. when the sspn interface is a bus master, it drives this signal to an active state before the start of serial data, and then releases it to an inactive state after the serial data has been sent. the active state of this signal can be high or low depending upon the selected bus and mode. when the sspn is a bus slave, this signal qualifies the presence of data from the master, according to the protocol in use. when there is just one bus master and one bus slave, the frame sync or slave select signal from the master can be connected directly to the slave's corresponding input. when there is more than one slave on the bus, further qualification of their frame select/slave select inputs will typically be necessary to prevent more than one slave from responding to a transfer. miso0/1/2 i/o miso dr(m) dx(s) si(m) so(s) master in slave out. the miso signal transfers serial data from the slave to the master. when the sspn is a slave, serial data is output on this signal. when the sspn is a master, it clocks in serial data from this signal. when the sspn is a slave and is not selected by fs/ssel, it does not drive this signal (leaves it in high-impedance state). mosi0/1/2 i/o mosi dx(m) dr(s) so(m) si(s) master out slave in. the mosi signal transfers serial data from the master to the slave. when the sspn is a master, it outputs serial data on this signal. when the sspn is a slave, it clocks in serial data from this signal.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 598 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.5 bus description 21.5.1 texas instruments sy nchronous serial frame format figure 100 shows the 4-wire texas instruments synchronous serial frame format supported by the ssp module. for device configured as a master in this mode, clk and fs are forced low, and the transmit data line dx is tri-stated whenever the ssp is idle. once the bottom entry of the transmit fifo contains data, fs is pulsed high for one clk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of clk, the msb of the 4-bit to 16-bit data frame is shifted out on the dx pin. likewise, the msb of the received data is shifted onto the dr pin by the off-chip serial slave device. both the ssp and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each clk. the rece ived data is transfer red from the serial shifter to the receive fifo on the first rising edge of clk after the lsb has been latched. 21.5.2 spi frame format the spi interface is a four-wire interfac e where the ssel signal behaves as a slave select. the main feature of the spi format is that the inactive state and phase of the sck signal are programmable thro ugh the cpol and cpha bits within the sspcr0 control register. a. single frame transfer b. continuous/back-to-back frames transfer fig 100. texas instruments synchronous serial frame format: a) single and b) continuous/back-to-back two frames transfer clk fs dx/dr 4 to 16 bits msb lsb clk fs dx/dr lsb msb lsb msb 4 to 16 bits 4 to 16 bits
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 599 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.5.2.1 clock polarity (cpol) and phase (cpha) control when the cpol clock polarity control bit is 0, it produces a steady state low value on the sck pin. if the cpol clock polarity control bit is 1, a steady state high value is placed on the clk pin when data is not being transferred. the cpha control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit tr ansmitted by either allowing or not allowing a clock transition before the first data capture edge. when the cpha phase control bit is 0, data is captured on the first clock edge transition. if the cpha clock phase control bit is 1, data is captured on the second clock edge transition. 21.5.2.2 spi format with cpol=0,cpha=0 single and continuous transmission signal sequences for spi format with cpol = 0, cpha = 0 are shown in figure 101 . in this configuration, during idle periods: ? the clk signal is forced low. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the ssp is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssel master signal being driven low. this causes slave data to be enabled onto the miso input line of the master. master?s mosi is enabled. a. single transfer with cpol=0 and cpha=0 b. continuous transfer with cpol=0 and cpha=0 fig 101. spi frame format with cpol=0 and cpha=0 (a) single and b) continuous transfer) sck ssel mosi msb lsb q msb lsb 4 to 16 bits miso sck ssel mosi miso 4 to 16 bits 4 to 16 bits msb lsb msb lsb q msb lsb q msb lsb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 600 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces one half sck period later, valid master data is transferred to the mosi pin. now that both the master and slave data have been set, the sck master clock pin goes high after one further half sck period. the data is now captured on the rising and propagated on the falling edges of the sck signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. however, in the case of continuous back-to- back transmissions, the ssel signal must be pulsed high between each data word transfe r. this is because the slave select pin freezes the data in its serial peripheral regist er and does not allow it to be altered if the cpha bit is logic zero. theref ore the master device must raise the ssel pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssel pin is retur ned to its idle state one sck period after the last bit has been captured. 21.5.2.3 spi format with cpol=0,cpha=1 the transfer signal sequence for spi format with cpol = 0, cpha = 1 is shown in figure 102 , which covers both single and continuous transfers. in this configuration, during idle periods: ? the clk signal is forced low. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the ssp is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssel master signal being driven low. master?s mosi pin is enabled. after a further one half sck period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the sck is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the sck signal. in the case of a single word transfer, after all bits have be en transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. fig 102. spi frame format with cpol=0 and cpha=1 sck ssel mosi q 4 to 16 bits miso q msb msb lsb lsb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 601 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces for continuous back-to-back transfers, the ssel pin is held low between successive data words and termination is the same as that of the single word transfer. 21.5.2.4 spi format with cpol = 1,cpha = 0 single and continuous transmission signal sequences for spi format with cpol=1, cpha=0 are shown in figure 103 . in this configuration, during idle periods: ? the clk signal is forced high. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the ssp is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssel master signal being driven low, which causes slave data to be immediately transferred onto the miso line of the master. master?s mosi pin is enabled. one half period later, valid master data is tr ansferred to the mosi line. now that both the master and slave data have been set, the sck master clock pin becomes low after one further half sck period. this means that data is captured on the falling edges and be propagated on the rising edges of the sck signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssel line is returned to its idle high state one sck period after the last bit has been captured. a. single transfer with cpol=1 and cpha=0 b. continuous transfer with cpol=1 and cpha=0 fig 103. spi frame format with cpol = 1 and cpha = 0 (a) single and b) continuous transfer) sck ssel q msb lsb 4 to 16 bits miso mosi msb lsb sck ssel mosi miso 4 to 16 bits 4 to 16 bits msb lsb msb lsb q msb lsb q msb lsb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 602 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces however, in the case of continuous back-to- back transmissions, the ssel signal must be pulsed high between each data word transfe r. this is because the slave select pin freezes the data in its serial peripheral regist er and does not allow it to be altered if the cpha bit is logic zero. theref ore the master device must raise the ssel pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer, the ssel pin is retur ned to its idle state one sck period after the last bit has been captured. 21.5.2.5 spi format with cpol = 1,cpha = 1 the transfer signal sequence for spi format with cpol = 1, cpha = 1 is shown in figure 104 , which covers both single and continuous transfers. in this configuration, during idle periods: ? the clk signal is forced high. ? ssel is forced high. ? the transmit mosi/miso pad is in high impedance. if the ssp is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssel master si gnal being driven low. master?s mosi is enabled. after a further one half sck period, both master and slave data are enabled onto their respective transmi ssion lines. at the same time, th e sck is enabled with a falling edge transition. data is then captured on t he rising edges and propagated on the falling edges of the sck signal. after all bits have been transf erred, in the case of a singl e word transmission, the ssel line is returned to its idle high state one sck period after the last bit has been captured. for continuous back-to-back transmissions, th e ssel pins remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. in general, for continuous back-to-back transfers the ssel pin is held low between successive data words and termination is the same as that of the single word transfer. 21.5.3 national semiconducto r microwire frame format figure 105 shows the microwire frame format for a single frame. figure 106 shows the same format when back-to-b ack frames are transmitted. fig 104. spi frame format with cpol = 1 and cpha = 1 sck ssel mosi q 4 to 16 bits miso q msb msb lsb lsb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 603 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces microwire format is very sim ilar to spi format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssp to the off-chip slave device. during this transmission, no incoming data is received by the ssp. after the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ? the sk signal is forced low. ? cs is forced high. ? the transmit data line so is arbitrarily forced low. a transmission is trig gered by writing a cont rol byte to the transm it fifo.the falling edge of cs causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the so pin. cs remains low for the duration of the frame transmission. the si pin remains tri-stated during this transmission. the off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each sk. after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssp. each bit is driven onto si lin e on the falling edge of sk. the ssp in turn latches each bit on the rising edge of sk. at t he end of the frame, for single transfers, the cs signal is pulled high one clock period afte r the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive fifo. note: the off-chip slave device can tri-state the receive line either on the falling edge of sk after the lsb has been latched by the receiv e shiftier, or when the cs pin goes high. for continuous transfers, data transmission b egins and ends in the same manner as a single transfer. however, the cs line is continuously asserted (held low) and transmission of data occurs back to back. the control byte of the next frame follows directly after the lsb of the received data fr om the current frame. each of the received values is transferred from the receive shifter on the falling edge sk, after the lsb of the frame has been latched into the ssp. fig 105. microwire frame format (single transfer) sk cs so 4 to 16 bits output data si 8-bit control msb lsb 0 msb lsb
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 604 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.5.3.1 setup and hold time requirements on cs with respect to sk in microwire mode in the microwire mode, the ssp slave samples the first bit of receive data on the rising edge of sk after cs has gone low. masters that drive a free-running sk must ensure that the cs signal has sufficient setup and hold margins with respect to the rising edge of sk. figure 107 illustrates these setup and hold time requirements. with respect to the sk rising edge on which the first bit of receive data is to be sampled by the ssp slave, cs must have a setup of at least two times the period of sk on which the ssp operates. with respect to the sk rising edge pr evious to this edge, cs must have a hold of at least one sk period. fig 106. microwire frame format (continuos transfers) sk cs so si msb lsb 4 to 16 bits output data 8-bit control 4 to 16 bits output data msb lsb 0 msb lsb lsb fig 107. microwire frame format setup and hold details sk cs si t hold = t sk t setup =2*t sk
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 605 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6 register description [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 477. register overview: ssp (b ase address 0x4008 8000 (ssp0), 0x4003 0000 (ssp1), 0x400a c000 (ssp2)) generic name access address offset description reset value [1] table cr0 r/w 0x000 control register 0. selects the serial clock rate, bus type, and data size. 0 478 cr1 r/w 0x004 control register 1. selects master/slave and other modes. 0 479 dr r/w 0x008 data register. writes fill the transmit fifo, and reads empty the receive fifo. 0 480 sr ro 0x00c status register 481 cpsr r/w 0x010 clock prescale register 0 482 imsc r/w 0x014 interrupt mask set and clear register 0 483 ris r/w 0x018 raw interrupt status register 484 mis r/w 0x01c masked interrupt status register 0 485 icr r/w 0x020 sspicr interrupt clear register na 486 dmacr r/w 0x024 dma control register 0 487
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 606 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6.1 sspn control register 0 this register controls the basic operatio n of the ssp controller. table 478: sspn control register 0 (cr0 - address 0x4008 8000 (ssp0), 0x4003 0000 (ssp1) , 0x400a c000 (ssp2)) bit description bit symbol value description reset value 3:0 dss data size select. this field controls the number of bits transferred in each frame. values 0000-0010 are not supported and should not be used. 0000 0011 4-bit transfer 0100 5-bit transfer 0101 6-bit transfer 0110 7-bit transfer 0111 8-bit transfer 1000 9-bit transfer 1001 10-bit transfer 1010 11-bit transfer 1011 12-bit transfer 1100 13-bit transfer 1101 14-bit transfer 1110 15-bit transfer 1111 16-bit transfer 5:4 frf frame format. 00 00 spi 01 ti 10 microwire 11 this combination is not supported and should not be used. 6 cpol clock out polarity. this bit is only used in spi mode. 0 0 ssp controller maintains the bus clock low between frames. 1 ssp controller maintains the bus clock high between frames. 7 cpha clock out phase. this bit is only used in spi mode. 0 0 ssp controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 1 ssp controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 15:8 scr serial clock rate. the numbe r of prescaler-output clocks pe r bit on the bus, minus one. given that cpsdvsr is the prescale divider, and the apb clock pclk clocks the prescaler, the bit frequency is pclk / (cpsdvsr ? [scr+1]). 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 607 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6.2 sspn control register 1 this register controls certain aspects of the operation of the ssp controller. 21.6.3 sspn data register software can write data to be transmitted to this register, and read data that has been received. table 479: sspn control register 1 (cr1 - address 0x4008 8004 (ssp0), 0x4003 0004 (ssp1), 0x400a c004 (ssp2)) bit description bit symbol value description reset value 0 lbm loop back mode. 0 0 during normal operation. 1 serial input is taken from the serial output (mosi or miso) rather than the serial input pin (miso or mosi respectively). 1 sse ssp enable. 0 0 the ssp controller is disabled. 1 the ssp controller will interact with othe r devices on the serial bus. software should write the app ropriate control information to the other ssp registers and interrupt controller registers, before setting this bit. 2 ms master/slave mode.this bit can only be written when the sse bit is 0. 0 0 the ssp controller acts as a master on the bus, driving the sclk, mosi, and ssel lines and receiving the miso line. 1 the ssp controller acts as a slave on th e bus, driving miso line and receiving sclk, mosi, and ssel lines. 3 sod slave output disable. this bit is relevant only in slave mode (ms = 1). if it is 1, this blocks this ssp controller from drivi ng the transmit data line (miso). 0 31:4 - reserved. read value is undefined, only zero should be written. na table 480: sspn data register (dr - address 0x4008 8008 (ssp0), 0x4003 0008 (ssp1), 0x400a c008 (ssp2)) bit description bit symbol description reset value 15:0 data write: software can write data to be sent in a future frame to this register whenever the tnf bit in the status register is 1, indicating that the tx fifo is not full. if the tx fifo was previously empty and the ssp controller is not busy on the bus, transmission of the data will begin immediately. otherwise the data written to th is register will be sent as soon as all previous data has been sent (and received). if the data length is less than 16 bits, software must right-justify the data written to this register. read: software can read data from this register whenever the rne bit in the status register is 1, indicating that the rx fifo is not empty. when softwa re reads this register, the ssp controller returns data from the least recent frame in the rx fifo. if the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 608 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6.4 sspn status register this read-only register reflects t he current status of the ssp controller. 21.6.5 sspn clock prescale register this register controls the factor by which t he prescaler divides pclk to yield the prescaler clock that is, in turn, divided by the scr factor in sspncr0, to determine the bit clock. important: the sspncpsr value must be properly initialized or the ssp controller will not be able to transmit data correctly. in slave mode, the ssp clock rate provided by the master must not exceed 1/12 of the peripheral clock selected in section 3.3.3.5 . the content of the sspn cpsr register is not relevant. in master mode, cpsdvsr min = 2 or larger (even numbers only). table 481: sspn status register (sr - address 0x4008 8 00c (ssp0), 0x4003 000c (ssp1), 0x400a c00c (ssp2)) bit description bit symbol description reset value 0 tfe transmit fifo empty. this bit is 1 is the transmit fifo is empty, 0 if not. 1 1 tnf transmit fifo not full. this bit is 0 if the tx fifo is full, 1 if not. 1 2 rne receive fifo not empty. this bit is 0 if the receive fifo is empty, 1 if not. 0 3 rff receive fifo full. this bit is 1 if the receive fifo is full, 0 if not. 0 4 bsy busy. this bit is 0 if the sspn controller is idle, or 1 if it is cu rrently sending/receiving a frame and/or the tx fifo is not empty. 0 31:5 - reserved. the value read from a reserved bit is not defined. na table 482: sspn clock prescale register (cpsr - addr ess 0x4008 8010 (ssp0), 0x4003 0010 (ssp1), 0x400a c010 (ssp2)) bit description bit symbol description reset value 7:0 cpsdvsr this even value between 2 and 254, by which pclk is divided to yield the prescaler output clock. bit 0 always reads as 0. 0 31:8 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 609 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6.6 sspn interrupt ma sk set/clear register this register controls whether each of the four possible interrup t conditions in the ssp controller are enabled. note that arm uses the word ?masked? in the opposite sense from classic computer terminology, in which ?masked? meant ?disabled?. arm uses the word ?masked? to mean ?enabled?. to avoid confusion we will not use the word ?masked?. 21.6.7 sspn raw interrupt status register this read-only register contains a 1 for ea ch interrupt condition that is asserted, regardless of whether or not the in terrupt is enabled in the sspnimsc. table 483: sspn interrupt mask set/clear register (imsc - address 0x4008 8014 (ssp0), 0x4003 0014 (ssp1), 0x400a c014 (ssp2)) bit description bit symbol description reset value 0 rorim software should set this bit to enable interrupt when a receive overrun occurs, that is, when the rx fifo is full and another frame is completely received. the arm spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 rtim software should set this bit to enable interrupt when a receive timeout condition occurs. a receive timeout occurs when the rx fifo is not empty, and has not been read for a period of 32 bit times. 0 2 rxim software should set this bit to enable interrupt when the rx fifo is at least half full. 0 3 txim software should set this bit to enable interrupt when the tx fifo is at least half empty. 0 31:4 - reserved. read value is undefined, only zero should be written. na table 484: sspn raw interrupt status register (ris - address 0x4008 8018 (ssp0), 0x4003 0018 (ssp1), 0x400a c018 (ssp2)) bit description bit symbol description reset value 0 rorris this bit is 1 if another frame was completely received while the rxfifo was full. the arm spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 rtris this bit is 1 if the rx fifo is not empty, and has not been read for a period of 32 bit times. 0 2 rxris this bit is 1 if the rx fifo is at least half full. 0 3 txris this bit is 1 if the tx fifo is at least half empty. 1 31:4 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 610 of 942 nxp semiconductors UM10562 chapter 21: lpc408 x/407x ssp interfaces 21.6.8 sspn masked inte rrupt status register this read-only register contains a 1 for each interrupt condition that is asserted and enabled in the sspnimsc. when an ssp interr upt occurs, the interrupt service routine should read this register to dete rmine the cause(s) of the interrupt. 21.6.9 sspn interrupt clear register software can write one or more one(s) to this write-only register, to clear the corresponding interrupt condition(s) in the ssp controller. note that the other two interrupt conditions can be cleared by writing or re ading the appropriate fifo, or disabled by clearing the corresponding bit in sspnimsc. 21.6.10 sspn dma control register the sspndmacr register is the dma contro l register. it is a read/write register. table 485: sspn masked interrupt status register (mis - address 0x4008 801c (ssp0), 0x4003 001c (ssp1), 0x400a c01c (ssp2)) bit description bit symbol description reset value 0 rormis this bit is 1 if another frame was completely received while the rxfifo was full, and this interrupt is enabled. 0 1 rtmis this bit is 1 if the rx fifo is not empty, has not been read for a period of 32 bit times, and this interrupt is enabled. 0 2 rxmis this bit is 1 if the rx fifo is at least half full, and this interrupt is enabled. 0 3 txmis this bit is 1 if the tx fifo is at l east half empty, and this interrupt is enabled. 0 31:4 - reserved. the value read from a reserved bit is not defined. na table 486: sspn interrupt clear register (icr - address 0x4008 8020 (ssp0), 0x4003 0020 (ssp1) , 0x400a c020 (ssp2)) bit description bit symbol description reset value 0 roric writing a 1 to this bit clears the ?frame was received when rxfifo was full? interrupt. na 1 rtic writing a 1 to this bit clears the "rx fifo was not empty and has not been read for a period of 32 bit times" interrupt. na 31:2 - reserved. read value is undefined, only zero should be written. na table 487: sspn dma control register (dmacr - addr ess 0x4008 8024 (ssp0), 0x4003 0024 (ssp1), 0x400a c024 (ssp2)) bit description bit symbol description reset value 0 rxdmae receive dma enable. when this bit is set to one 1, dma for the receive fifo is enabled, otherwise receive dma is disabled. 0 1 txdmae transmit dma enable. when this bit is set to one 1, dma for the transmit fifo is enabled, otherwise transmit dma is disabled 0 31:2 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 611 of 942 22.1 basic configuration the i 2 c0/1/2 interfaces are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pci2c0/1/2. remark: on reset, all i 2 c interfaces are enabled (pci2c0/1/2 = 1). 2. peripheral clock: the i 2 c interfaces operate from the common pclk that clocks both the bus interface and functional po rtion of most apb peripherals. see section 3.3.3.5 . 3. pins: select i 2 c0, i 2 c1, or i 2 c2 pins and pin modes using the relevant iocon registers (see section 7.4.1 ). remark: the pins p0[27] and p0[28] are specialized open-drain i 2 c pins that support fully compliant fast mode (400 khz) and standard mode (100 khz) i 2 c. these pins have no on-chip pull-up devices at all and must always be pulled up externally when they are outputs (per the i 2 c bus specification). pins p5[2] and p5[3] are similar, but in addition, also support fast mode plus (1 mhz) i 2 c. both sets of pins have somewhat different configuration options than most port pins, see section 7.4.1 for details. for all other pins that can be used for i 2 c communication, see the remark below. remark: i 2 c pins that do not use specialized i 2 c pads (as identified in ta b l e 7 4 ) can be configured to an open-drain mode via the relevant iocon registers, and can be used with fast mode (400 khz) and standard mode (100 khz) i 2 c. these pins do not include an analog filter to suppress line glitc hes, but a similar function is performed by the digital filter in the i 2 c block itself. these pins should be configured as: no pull-up, no pull-down, open drain mode. 4. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 5. initialization: see section 22.9.8.1 and section 22.10.1 . UM10562 chapter 22: lpc408x/407x i 2 c-bus interfaces rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 612 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.2 features ? supports 1 mhz fast mode plus (some pinouts of i 2 c0 only), 400 khz fast mode, and 100 khz standard mode. ? standard i 2 c compliant bus interfaces may be configured as master, slave, or master/slave. ? arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus. ? programmable clock allows adjustment of i 2 c transfer rates. ? data transfer is bidirectional between masters and slaves. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer. ? optional recognition of up to 4 distinct slave addresses. ? monitor mode allows observing all i 2 c-bus traffic, regardless of slave address, without affecting the actual i 2 c-bus traffic. 22.3 applications interfaces to external i 2 c standard parts, such as serial rams, lcds, tone generators, other microcontrollers, etc. can also be used as a diagnostic/test bus. 22.4 description a typical i 2 c-bus configuration is shown in figure 108 . depending on the state of the direction bit (r/w), two types of data transfers are possible on the i 2 c-bus: ? data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte, unless the slave device is unable to accept more data. ? data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows the data bytes transmitted by th e slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the i 2 c-bus will not be released. the i 2 c interfaces are byte oriented and have four operating modes: master transmitter mode, master receiver mode, slave transmitter mode and slave receiver mode.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 613 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.4.1 i 2 c fast mode plus fast mode plus is a 1 mbit/sec tran sfer rate to communicate with the i 2 c products which the nxp semiconductors is now providing. in order to use fast mode plus, the i 2 c0 pins must be configured, then rates above 400 khz and up to 1 mhz may be selected, see table 503 . to configure the pins for fast mode plus, the i2cmode bits in the iocon_p5_0 2 and iocon_p5_03 registers must be set to binary 10, see section 7.4.1 . fig 108. i 2 c-bus configuration other device with i 2 c interface pull-up resistor other device with i 2 c interface microcontroller sda scl i 2 c bus scl sda pull-up resistor
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 614 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.5 pin description the internal logic of the 3 i 2 c interfaces is identical. these interfaces can be brought out to device pins in several ways, some of whic h have different pin i/o characteristics. i2c0 on pins p0[27] and p0[28] use specialized i 2 c pads that support fully spec compliant fast mode and standard mode i 2 c. i2c0 on pins p5[2] and p5[3] also use specialized i 2 c pads. these pads support fast mode plus in additional to the previously mentioned modes. any of the i 2 c interfaces brought out to pins other than those just mentioned use standard i/o pins. these pins also support i 2 c operation in fast mode and standard mode. the primary difference is that these pins do not in clude an analog spike suppression filter that exists on the specialized i 2 c pads. the i 2 c interfaces all include a digital filter that can serve the same purpose. 22.6 i 2 c operating modes in a given application, the i 2 c block may operate as a master, a slave, or both. in the slave mode, the i 2 c hardware looks for any one of its f our slave addresses and the general call address. if one of these addres ses is detected, an interrupt is requested. if the processor wishes to become the bus master, the hardw are waits until the bus is free before the master mode is entered so that a possible slave operation is not interrupted. if bus arbitration is lost in the master mode, the i 2 c block switches to the slave mode immediately and can detect any of its own configured slave addresses in the same serial transfer. 22.6.1 master transmitter mode in this mode data is transmitted from master to slave. before the ma ster transmitter mode can be entered, the i2conset regist er must be initialized as shown in table 489 . i2en must be set to 1 to enable the i 2 c function. if the aa bit is 0, the i 2 c interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. the sta, sto and si bits must be 0. the si bit is cleared by writing 1 to the sic bit in the i2conclr register. the sta bit should be cleared after writing the slave address. table 488. i 2 c pin description pin type description i2c0_sda input/output i 2 c0 serial data i2c0_scl input/output i 2 c0 serial clock i2c1_sda input/output i 2 c1 serial data i2c1_scl input/output i 2 c1 serial clock i2c2_sda input/output i 2 c2 serial data i2c2_scl input/output i 2 c2 serial clock
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 615 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this mode the data direction bit (r/w) should be 0 which means write. the first byte transmitted contains the slave address and write bit. data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indi cate the beginning and the end of a serial transfer. the i 2 c interface will enter master transmitter m ode when software sets the sta bit. the i 2 c logic will send the start condition as s oon as the bus is free. after the start condition is transmitted, the si bit is set, an d the status code in the i2stat register is 0x08. this status code is used to vector to a state service routine which will load the slave address and write bit to the i2dat register, an d then clear the si bit. si is cleared by writing a 1 to the sic bit in the i2conclr register. when the slave address and r/w bit have been transmitted and an acknowledgment bit has been received, the si bit is set again, and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or 0x68, 0x78, or 0xb0 if the slave mode was enabled (by setting aa to 1). the appropriate actions to be taken for each of these status codes are shown in ta b l e 5 0 7 to table 510 . 22.6.2 master receiver mode in the master receiver mode, data is received from a slave transmitter. the transfer is initiated in the same way as in the master transmitter mode. when the start condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to the i 2 c data register (i2dat), and then clear the si bit. in this case, the data direction bit (r/w) should be 1 to indicate a read. when the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the si bit is set, and the status register will show the status code. for master mode, the possible status codes are 0x40 , 0x48, or 0x38. for slave mode, the possible status codes are 0x68, 0x78, or 0xb0. for details, refer to table 508 . table 489. i2c0conset and i2c1conset used to configure master mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value - 1 0 0 0 0 - - fig 109. format in the master transmitter mode a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition s slave address rw=0 a data a a/a p from master to slave from slave to master data n bytes data transmitted
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 616 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces when the cpu needs to acknowledge a received byte, the aa bit needs to be set accordingly prior to clearing the si bit and initiating the byte read. when the i 2 c interface needs to not acknowledge a received byte, the aa bit needs to be cleared prior to clearing the si bit and initiating the byte read. note that the last received byte is always followed by a "not acknowledge" from the i 2 c interface so that the master can signal the sl ave that the reading se quence is finished and that it needs to issue a stop or repeated start command. once the "not acknowledge has been sent and the si bit is set, the i 2 c interface can send either a stop (sto bit is set) or a repeated start (sta bit is set). then the si bit is cleared to initiate the requested operation. after a repeated start condition, i 2 c may switch to the master transmitter mode. 22.6.3 slave receiver mode in the slave receiver mode, data bytes are received from a master transmitter. to initialize the slave receiver mode, write any of the sl ave address registers (i2adr0-3) and slave mask registers (i2mask0-3) and write the i 2 c control set register (i2conset) as shown in table 490 . fig 110. format of master receiver mode fig 111. a master receiver switches to master transmitter after sending repeated start data a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition s slave address rw=1 a data p n bytes data received from master to slave from slave to master a a a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition sla = slave address sr = repeated start condition data n bytes data transmitted from master to slave from slave to master a data a a sla r sr w p s sla data a a
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 617 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces i2en must be set to 1 to enable the i 2 c function. aa bit must be set to 1 to acknowledge any of its own slave addresses or the general call address. the sta, sto and si bits are set to 0. after i2adr and i2conset are initialized, the i 2 c interface waits until it is addressed by its any of its own slave addresses or general call address followed by the data direction bit. if the direction bit is 0 (w), it enters slave receiver mode. if the direction bit is 1 (r), it enters slave transmitter mode. after the address and direction bit have been received, the si bit is set and a valid status code can be read from the status register (i2stat). refer to table 509 for the status codes and actions. 22.6.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will be 1, indicating a read operation. serial data is transmitted via sda while the serial clock is input through scl. start and stop conditions are recognized as the beginning and end of a se rial transfer. in a given application, i 2 c may operate as a master and as a slave. in the slave mode, the i 2 c hardware looks for any of its own slave addresses and the general call address. if one of these addresses is detected, an interrupt is requested. when the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. if bu s arbitration is lost in the master mode, the i 2 c interface switches to the slave mode imm ediately and can detect any of its own slave addresses in the same serial transfer. table 490. i2c0conset and i2c1conset used to configure slave mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value - 1 0 0 0 1 - - fig 112. format of slave receiver mode a a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition sr = repeated start condition a a/a n bytes data received from master to slave from slave to master s slave address rw=0 data p/sr data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 618 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.7 i 2 c implementation and operation figure 114 shows how the on-chip i 2 c-bus interface is implemented, and the following text describes the individual blocks. 22.7.1 input filters and output stages input signals are synchronized with the inter nal clock, and spikes shorter than three clocks are filtered out. fig 113. format of slave transmitter mode data a = acknowledge (sda low) a = not acknowledge (sda high) s = start condition p = stop condition a data n bytes data transmitted from master to slave from slave to master s slave address rw=1 a p a
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 619 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces fig 114. i 2 c serial interface block diagram ap b bus status register i2cnstat control register and scl duty cyle registers i2cnconset, i2cnconclr, i2cnsclh, i2cnscll address registers mask and compare shift register i2cndat ack bit counter/ arbitration and monitor mode register i2cnmmctrl sync logic serial clock generator timing and control logic status decoder status bus interrupt pclk input filter output stage scl input filter output stage sda i2cnaddr0 to i2cnaddr3 mask registers i2cnmask0 to i2cnmask3 i2cndatabuffer matchall i2cnmmctrl[3] 8 8 8 16
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 620 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.7.2 address registers, i2adr0 to i2adr3 these registers may be loaded with the 7-bit slave address (7 most significant bits) to which the i 2 c block will respond when programmed as a slave transmitter or receiver. the lsb (gc) is used to enable general call addre ss (0x00) recognition. when multiple slave addresses are enabled, the actual address re ceived may be read from the i2dat register at the state where the ?own slave address? has just been received. remark: in the remainder of this chapter, when t he phrase ?own slave address? is used, it refers to any of the four configured slave addresses after address masking. 22.7.3 address mask register s, i2mask0 to i2mask3 the four mask registers each contain seven acti ve bits (7:1). any bit in these registers which is set to ?1? will cause an automati c compare on the corresponding bit of the received address when it is compared to the i2adrn register associated with that mask register. in other words, bits in an i2adrn register which are masked are not taken into account in determining an address match. when an address-match interrup t occurs, the processo r will have to read the data register (i2dat) to determine which received address actually caused the match. 22.7.4 comparator the comparator compares the re ceived 7-bit slave address with any of the four configured slave addresses in i2adr0 through i2adr3 after masking. it also compares the first received 8-bit byte with the general call add ress (0x00). if an a match is found, the appropriate status bits are set and an interrupt is requested. 22.7.5 shift register, i2dat this 8-bit register contains a byte of serial data to be transmitted or a byte which has just been received. data in i2dat is always shifted from right to left; the first bit to be transmitted is the msb (bit 7) and, after a byte has been received, the first bit of received data is located at the msb of i2dat. while data is being shifted out, data on the bus is simultaneously being shifted in; i2dat always contains the last byte present on the bus. thus, in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in i2dat. 22.7.6 arbitration and synchronization logic in the master transmitter mode, the arbitratio n logic checks that every transmitted logic 1 actually appears as a logic 1 on the i 2 c-bus. if another device on the bus overrules a logic 1 and pulls the sda line low, arbitration is lost, and the i 2 c block immediately changes from master transmitter to slave receiver. the i 2 c block will continue to output clock pulses (on scl) until transmission of the current serial byte is complete. arbitration may also be lost in the master re ceiver mode. loss of arbitration in this mode can only occur while the i 2 c block is returning a ?not acknowledge: (logic 1) to the bus. arbitration is lost when another device on th e bus pulls this signal low. since this can occur only at the end of a serial byte, the i 2 c block generates no further clock pulses. figure 115 shows the arbitration procedure.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 621 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces the synchronization logic will sy nchronize the serial clock ge nerator with the clock pulses on the scl line from another device. if two or more master devices generate clock pulses, the ?mark? duration is determ ined by the device that generat es the shortest ?marks,? and the ?space? duration is determined by the device that generates the longest ?spaces?. figure 116 shows the synchron ization procedure. a slave may stretch the space duration to slow down the bus master. the space duration may also be stretched for handshaking purposes. this can be done after each bit or after a complete byte transfer. the i 2 c block will stretch the scl space duration after a byte has been transmitted or received and the acknowledge bit has been transferred. the serial interrupt flag (si) is set, and the stretching continues until the serial interrupt flag is cleared. 22.7.7 serial clock generator this programmable clock pulse generator pr ovides the scl clock pulses when the i 2 c block is in the master transmitter or master re ceiver mode. it is switched off when the i 2 c block is in a slave mode. the i 2 c output clock frequency and duty cycle is programmable (1) another device transmits serial data. (2) another device overrules a logic (dotted line) transmitted this i 2 c master by pulling the sda line low. arbitration is lost, and this i 2 c enters slave receiver mode. (3) this i 2 c is in slave receiver mode but still generates clock pulses until the current byte has been transmitted. this i 2 c will not generate clock pulses for the next byte. data on sda originates from the new master once it has won arbitration. fig 115. arbitration procedure (1) another device pulls the scl line low before this i 2 c has timed a complete high time. the other device effectively determines the (shorter) high period. (2) another device continues to pull the scl line low after this i 2 c has timed a complete low time and released scl. the i 2 c clock generator is forced to wait until scl goes high. the other device effectively determines the (longer) low period. (3) the scl line is released , and the cloc k generator begins timing the high time. fig 116. serial clock synchronization sda line scl line 12 34 8 9 ack (1) (2) (1) (3) sda line scl line (2) (1) (3) high period low period (1)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 622 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces via the i 2 c clock control registers. see the description of the i2cscll and i2csclh registers for details. the output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other sc l clock sources as described above. 22.7.8 timing and control the timing and control logic generates the timing and control signals for serial byte handling. this logic block provides the shift pulses for i2dat, enables the comparator, generates and detects start and stop condit ions, receives and transmits acknowledge bits, controls the master and slave modes, co ntains interrupt request logic, and monitors the i 2 c-bus status. 22.7.9 control register, i2conset and i2conclr the i 2 c control register contains bits used to control the following i 2 c block functions: start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition, and acknowledgment. the contents of the i 2 c control register may be read as i2conset. writing to i2conset will set bits in the i 2 c control register that correspond to ones in the value written. conversely, writing to i2conc lr will clear bits in the i 2 c control register that correspond to ones in the value written. 22.7.10 status decoder and status register the status decoder takes all of the internal status bits and compresses them into a 5-bit code. this code is unique for each i 2 c-bus status. the 5-bit code may be used to generate vector addresses for fast processi ng of the various service routines. each service routine processes a particular bus status. there are 26 possible bus states if all four modes of the i 2 c block are used. the 5-bit status co de is latched into the five most significant bits of the status register when th e serial interrupt flag is set (by hardware) and remains stable until the interrupt flag is cleared by software. the three least significant bits of the status register are always zero. if the status code is used as a vector to service routines, then the routines are displaced by ei ght address locations. ei ght bytes of code is sufficient for most of the service routines (see the software example in this section).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 623 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.8 register description table 491. register overview: i2c-bus interface (base address 0x4001 c000 (i2c0), 0x4005 c000 (i2c1), 0x400a 0000 (i2c2)) name access address offset description reset value [1] table conset r/w 0x000 i2c control set register. when a one is written to a bit of this register, the corresponding bit in the i 2 c control register is set. writing a zero has no effect on the corresponding bit in the i 2 c control register. 0x00 492 stat ro 0x004 i2c status register. during i 2 c operation, this register provides detailed status codes that allow software to determine the next action needed. 0xf8 494 dat r/w 0x008 i2c data register. during master or slave transmit mode, data to be transmitted is written to this regist er. during master or slave receive mode, data that has been received may be read from this register. 0x00 495 adr0 r/w 0x00c i2c slave address register 0. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit deter mines whether a slave responds to the general call address. 0x00 498 sclh r/w 0x010 sch duty cycle register high half word. determines the high time of the i 2 c clock. 0x04 501 scll r/w 0x014 scl duty cycle register low half word. determines the low time of the i 2 c clock. i2nscll and i2nsclh together determine the clock frequency generated by an i 2 c master and certain times used in slave mode. 0x04 502 conclr wo 0x018 i2c control clear register. when a one is written to a bit of this register, the corresponding bit in the i 2 c control register is cleared. writing a zero has no effect on the corresponding bit in the i 2 c control register. na 493 mmctrl r/w 0x01c monitor mode control register. 0x00 496 adr1 r/w 0x020 i2c slave address register 1. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit deter mines whether a slave responds to the general call address. 0x00 499 adr2 r/w 0x024 i2c slave address register 2. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit deter mines whether a slave responds to the general call address. 0x00 499 adr3 r/w 0x028 i2c slave address register 3. contains the 7-bit slave address for operation of the i 2 c interface in slave mode, and is not used in master mode. the least significant bit deter mines whether a slave responds to the general call address. 0x00 499 data_ buffer ro 0x02c data buffer register. the contents of the 8 msbs of the i2dat shift register will be transferred to the i2data_buffer auto matically after every 9 bits (8 bits of data plus ack or nack) has been received on the bus. 0x00 497 mask0 r/w 0x030 i2c slave address mask register 0 . this mask register is associated with i2adr0 to determine an address match. the mask register has no effect when comparing to the general call address (?0000000?). 0x00 500
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 624 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. 22.8.1 i 2 c control set register the i2conset registers control setting of bits in the i2con register that controls operation of the i 2 c interface. writing a one to a bit of this register causes the corresponding bit in the i 2 c control register to be set. writing a zero has no effect. reading this register provides the current values of the control and flag bits. i2en i 2 c interface enable. when i2en is 1, the i 2 c interface is enabled. i2en can be cleared by writing 1 to the i2enc bit in the i2conclr register. when i2en is 0, the i 2 c interface is disabled. when i2en is ?0?, the sda and sc l input signals are ignored, the i 2 c block is in the ?not addressed? slave state, and the sto bit is forced to ?0?. i2en should not be used to temporarily release the i 2 c-bus since, when i2en is reset, the i 2 c-bus status is lost. the aa flag should be used instead. sta is the start flag. setting this bit causes the i 2 c interface to enter master mode and transmit a start condition or transmit a repeated start condition if it is already in master mode. when sta is 1 and the i 2 c interface is not already in mast er mode, it enters master mode, checks the bus and generates a start condition if the bus is free. if the bus is not free, it waits for a stop condition (w hich will free the bus) and generates a start condition after a delay of a half clock period of the internal clock generator. if the i 2 c interface is mask1 r/w 0x034 i2c slave address mask register 1 . this mask register is associated with i2adr0 to determine an address match. the mask register has no effect when comparing to the general call address (?0000000?). 0x00 500 mask2 r/w 0x038 i2c slave address mask register 2 . this mask register is associated with i2adr0 to determine an address match. the mask register has no effect when comparing to the general call address (?0000000?). 0x00 500 mask3 r/w 0x03c i2c slave address mask register 3 . this mask register is associated with i2adr0 to determine an address match. the mask register has no effect when comparing to the general call address (?0000000?). 0x00 500 table 491. register overview: i2c-bus interface (base address 0x4001 c000 (i2c0), 0x4005 c000 (i2c1), 0x400a 0000 (i2c2)) name access address offset description reset value [1] table table 492. i 2 c control set register (conset - addresses 0x4001 c000 (i2c0), 0x4005 c000 (i2c1) , 0x400a 0000 (i2c2)) bit description bit symbol description reset value 1:0 - reserved. read value is undefined, only zero should be written. na 2 aa assert acknowledge flag. 0 3si i 2 c interrupt flag. 0 4 sto stop flag. 0 5 sta start flag. 0 6i2eni 2 c interface enable. 0 31:7 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 625 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces already in master mode and data has been transm itted or received, it transmits a repeated start condition. sta may be set at any time, including when the i 2 c interface is in an addressed slave mode. sta can be cleared by writing 1 to the stac bit in the i2conclr register. when sta is 0, no start condition or repeat ed start condition will be generated. if sta and sto are both set, then a stop condition is transmitted on the i 2 c-bus if it the interface is in master mode, and transmit s a start condition thereafter. if the i 2 c interface is in slave mode, an internal stop condition is generated, but is not transmitted on the bus. sto is the stop flag. setting this bit causes the i 2 c interface to transmit a stop condition in master mode, or recover from an error condition in slave mode. when sto is 1 in master mode, a stop condition is transmitted on the i 2 c-bus. when the bus detects the stop condition, sto is cleared automatically. in slave mode, setting this bit can recover from an error condit ion. in this case, no stop condition is transmitted to the bus. the hardware behaves as if a stop condition has been received and it switches to ?not addr essed? slave receiver mode. the sto flag is cleared by hardware automatically. si is the i 2 c interrupt flag. this bit is set when the i 2 c state changes. however, entering state f8 does not set si since there is nothing for an interrupt service routine to do in that case. while si is set, the low period of the serial clock on the scl line is stretched, and the serial transfer is suspended. when scl is high, it is unaffected by the state of the si flag. si must be reset by software, by writing a 1 to the sic bit in i2conclr register. the si bit should be cleared only after the required bit( s) has (have) been set and the value in i2dat has been loaded or read. aa is the assert acknowledge flag. when set to 1, an acknowledge (low level to sda) will be returned during the acknowledge clock pulse on the scl line on the following situations: 1. a matching address defined by registers i2adr0 through i2adr3, masked by i2mask0 though i2mask3, has been received. 2. the general call address has been received while the general call bit (gc) in i2adr is set. 3. a data byte has been received while the i 2 c is in the master receiver mode. 4. a data byte has been received while the i 2 c is in the addressed slave receiver mode the aa bit can be cleared by writing 1 to the aac bit in the i2conclr register. when aa is 0, a not acknowledge (hig h level to sda) will be retu rned during the acknowledge clock pulse on the scl line on the following situations: 1. a data byte has been received while the i 2 c is in the master receiver mode. 2. a data byte has been received while the i 2 c is in the addressed slave receiver mode.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 626 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.8.2 i 2 c control clear register the i2conclr registers control clearing of bits in the i2con register that controls operation of the i 2 c interface. writing a one to a bit of this register causes the corresponding bit in the i 2 c control register to be cleared. writing a zero has no effect. i2conclr is a write-only register. the value of the related bits can be read from the i2conset register. aac is the assert acknowledge clear bit. writing a 1 to this bit clears the aa bit in the i2conset register. writing 0 has no effect. sic is the i 2 c interrupt clear bit. writing a 1 to this bit clears the si bit in the i2conset register. writing 0 has no effect. stac is the start flag clear bit. writing a 1 to this bit clears the sta bit in the i2conset register. writing 0 has no effect. i 2enc is the i 2 c interface disable bit. writing a 1 to this bit clears the i2en bit in the i2conset register. writing 0 has no effect. 22.8.3 i 2 c status register each i 2 c status register reflects the condition of the corresponding i 2 c interface. the i 2 c status register is read-only. the three least significant bits are always 0. ta ken as a byte, the status register contents represent a status code. ther e are 26 possible status codes. when the status code is 0xf8, there is no relevant information available and the si bit is not set. all other 25 status codes correspond to defined i 2 c states. when any of these st ates entered, the si bit will be set. for a complete list of status codes, refer to tables from table 507 to table 510 . table 493. i 2 c control clear register (conclr - addresses 0x4001 c018 (i2c0), 0x4005 c018 (i2c1), 0x400a 0018 (i2c2)) bit description bit symbol description 1:0 - reserved. read value is undefined, only zero should be written. 2 aac assert acknowledge clear bit. 3sic i 2 c interrupt clear bit. 4 - reserved. read value is undefined, only zero should be written. 5 stac start flag clear bit. 6i2enci 2 c interface disable bit. 31:7 - reserved. read value is undefined, only zero should be written. table 494. i 2 c status register (stat - addresses 0x4001 c004 (i2c0), 0x4005 c004 (i2c1), 0x400a 0004 (i2c2)) bit description bit symbol description reset value 2:0 - these bits are unused and are always 0. 0 7:3 status these bits give the actual status information about the i 2 c interface. 0x1f 31:8 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 627 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.8.4 i 2 c data register this register contains the data to be trans mitted or the data just received. the cpu can read and write to this register only while it is not in the proc ess of shifting a byte, when the si bit is set. data in i2dat remains stable as long as the si bit is set. data in i2dat is always shifted from right to left: the first bit to be transmitted is the msb (bit 7), and after a byte has been received, the first bit of rece ived data is located at the msb of i2dat. 22.8.5 i 2 c monitor mode control register this register controls the monitor mode which allows the i 2 c module to monitor traffic on the i 2 c-bus without actually participating in traffic or interfering with the i 2 c-bus. [1] when the ena_scl bit is cleared and the i 2 c no longer has the ability to stretch the clock, interrupt response time becomes important. to give the part more time to respond to an i 2 c interrupt under these conditions, an i2data_buffer register is used ( section 22.8.6 ) to hold received data for a full 9-bit word transmission time. table 495. i 2 c data register (dat- addresses 0x4001 c008 (i2c0), 0x4005 c008 (i2c1), 0x400a 0008 (2c2)) bit description bit symbol description reset value 7:0 data this register holds data values that have been received or are to be transmitted. 0 31:8 - reserved. read value is undefined, only zero should be written. na table 496. i 2 c monitor mode control register (mmctrl - addresses 0x4001 c01c (i2c0), 0x4005 c01c (i2c1), 0x400a 001c (i2c2)) bit description bit symbol value description reset value 0 mm_ena monitor mode enable. 0 0 monitor mode disabled. 1 the i 2 c module will enter monitor mode. in this mode the sda output will be put in high impedance mode. this prevents the i 2 c module from outputting data of any kind (including ack) onto the i 2 c data bus. depending on the state of the ena_scl bit, the output may be also forced high, preventing the module from having control over the i 2 c clock line. 1 ena_scl scl output enable. 0 0 when this bit is cleared to ?0 ?, the scl output will be forced high when the module is in monitor mode. as described above, this will prevent the module from having any control over the i 2 c clock line. 1 when this bit is set, the i 2 c module may exercise the same control over the clock line that it would in normal operation. this means that, acting as a slave peripheral, the i 2 c module can ?stretch? the clock line (hold it low) until it has had time to respond to an i 2 c interrupt. [1] 2 match_all select interrupt register match. 0 0 when this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers, i2adr0 through i2adr3. that is, the module will respond as a normal slave as far as address-recognition is concerned. 1 when this bit is set to ?1? and the i 2 c is in monitor mode, an interrupt will be generated on any address received. this will enable the part to monitor all traffic on the bus. 31:3 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 628 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces remark: the ena_scl and match_all bits have no effect if the mm_ena is ?0? (i.e. if the module is not in monitor mode). 22.8.5.1 interrupt in monitor mode all interrupts will occur as no rmal when the module is in monitor mode. this means that the first interrupt will occur when an address-match is det ected (any addre ss received if the match_all bit is set, otherwise an ad dress matching one of the four address registers). subsequent to an addres s-match detection, interrupts will be gene rated after each data byte is received for a slave-wr ite transfer, or after each byte that the module believes it has transmitted for a slave- read transfer. in this second case, the da ta register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master. following all of these interrupts, the processor may read the data register to see what was actually transmitted on the bus. 22.8.5.2 loss of arbitration in monitor mode in monitor mode, the i 2 c module will not be able to respond to a requ est for information by the bus master or is sue an ack. some other slave on the bus will re spond instead. software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected. 22.8.6 i 2 c data buffer register in monitor mode, the i 2 c module may lose the ability to stretch the clock if the ena_scl bit is not set. this means that the processor will have a limited amount of time to read the contents of the data received on the bus. if the processor reads the i2dat shift register, as it ordinarily would, it could have only one bi t-time to respond to the interrupt before the received data is overwritten by new data. to give the processor more time to respond, a new 8-bit, read-only i2data_buffer register has been added. the contents of t he 8 msbs of the i2dat shift register are transferred to the i2data_buffer automatically after every 9 bits (8 bits of data plus ack or nack) has been received on the bus. this means that the processor will have 9 bit transmission times to respond to the interr upt and read the data before it is overwritten. the processor will still have the ability to read i2dat directly , as usual, and the behavior of i2dat will not be altered in any way. although the i2data_buffer register is primar ily intended for use in monitor mode with the ena_scl bit = ?0?, it is available for re ading at any time under any mode of operation. table 497. i 2 c data buffer register (data_buffer - addresses 0x4001 c02c (i2c0), 0x4005 c02c (i2c1), 0x400a 002c (i2c2)) bit description bit symbol description reset value 7:0 data this register holds contents of the 8 msbs of the i2dat shift register. 0 31:8 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 629 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.8.7 i 2 c slave address registers these registers are readable and writable and are only used when an i 2 c interface is set to slave mode. in master mode, this regist er has no effect. the lsb of i2adr is the general call bit. when this bit is set, the general call address (0x00) is recognized. if these registers contain 0x00, the i 2 c will not acknowledge any address on the bus. all four registers will be cleared to this disabled state on reset. 22.8.8 i 2 c mask registers the four mask registers each contain seven acti ve bits (7:1). any bit in these registers which is set to ?1? will cause an automati c compare on the corresponding bit of the received address when it is compared to the i2adrn register associated with that mask register. in other words, bits in an i2adrn register which are masked are not taken into account in determining an address match. the mask register has no effect on comparison to the general call address (?0000000?). when an address-match interrup t occurs, the processo r will have to read the data register (i2dat) to determine which received address actually caused the match. table 498. i 2 c slave address register 0 (adr0 - address 0x4001 c00c (i2c0), 0x4005 c00c (i2c1), 0x400a 000c (i2c2)) bit description bit symbol description reset value 0 gc general call enable bit. 0 7:1 address the i 2 c device address for slave mode. 0x00 31:8 - reserved. the value read from a reserved bit is not defined. - table 499. i 2 c slave address registers (adr[1:3] - address 0x4001 c020 (adr1) to 0x4001 c028 (adr3) (i2c0), 0x4005 c020 (adr1) to 0x4005 c028 (adr3) (i2c1), 0x400a 0020 (adr1) to 0x400a 0028 (adr3) (i2c2)) bit description bit symbol description reset value 0 gc general call enable bit. 0 7:1 address the i 2 c device address for slave mode. 0x00 31:8 - reserved. the value read from a reserved bit is not defined. - table 500. i 2 c mask registers (mask[0:3] - address 0x4001 c030 (mask0) to 0x4001 c03c (mask3) (i2c0), 0x4005 c030 (mask0) to 0x4005 c03c (mask3) (i2c1), 0x400a 0030 (mask0) to 0x400a 003c (mask3) (i2c1)) bit description bit symbol description reset value 0 - reserved. user software should not write ones to reserved bits. this bit reads always back as 0. 0 7:1 mask mask bits. 0x00 31:8 - reserved. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 630 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.8.9 i 2 c scl high duty cycle register 22.8.10 i 2 c scl low duty cycle register 22.8.11 selecting the appropriate i 2 c data rate and duty cycle software must set values for the registers i2sclh and i2scll to select the appropriate data rate and duty cycle. i2sclh defines the number of pclk cycles for the scl high time, i2scll defines the number of pclk cyc les for the scl low time. the frequency is determined by the following formula (pclk is the frequency of the peripheral bus apb): (13) the values for i2scll and i2sclh must ensure that the data rate is in the appropriate i 2 c data rate range. each register value must be greater than or equal to 4. table 503 gives some examples of i 2 c-bus rates based on pclk frequency and i2scll and i2sclh values. table 501. i 2 c scl high duty cycle register (sclh - address 0x4001 c010 (i2c0), 0x4005 c010 (i2c1), 0x400a 0010(i2c2)) bit description bit symbol description reset value 15:0 sclh count for scl high time period selection. 0x0004 31:16 - reserved. read value is undefined, only zero should be written. na table 502. i 2 c scl low duty cycle register (scll - address 0x4001 c014 (i2c0), 0x4005 c014 (i2c1), 0x400a 0014 (i2c2)) bit description bit symbol description reset value 15:0 scll count for scl low time period selection. 0x0004 31:16 - reserved. read value is undefined, only zero should be written. na i 2 c bitfrequency pclki2c i2csclh i2cscll + -------------------------------------------------------- - = table 503. example i 2 c clock rates i 2 c rate i2scll + i2sclh values at pclk (mhz) 6 8 10 12 16 20 30 40 50 60 70 80 90 100 100 khz (standard) 60 80 100 120 160 200 300 400 500 600 700 800 900 1000 400 khz (fast mode) 15 20 25 30 40 50 75 100 125 150 175 200 225 250 1 mhz (fast mode plus) - 8 10 12 16 20 30 40 50 60 70 80 90 100
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 631 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces i2scll and i2sclh values should not ne cessarily be the same. software can set different duty cycles on scl by setting these two registers. for example, the i 2 c-bus specification defines the scl low time and high time at different values for fast mode and fast mode plus i 2 c.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 632 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9 details of i 2 c operating modes the four operating modes are: ? master transmitter ? master receiver ? slave receiver ? slave transmitter data transfers in each mode of operation are shown in figure 117 , figure 118 , figure 119 , figure 120 , and figure 121 . table 504 lists abbreviations used in these figures when describing the i 2 c operating modes. in figure 117 to figure 121 , circles are used to indicate wh en the serial interrupt flag is set. the numbers in the circles show the status code held in the i2stat register. at these points, a service routine must be executed to continue or complete the serial transfer. these service routines are not critical since th e serial transfer is suspended until the serial interrupt flag is cleared by software. when a serial interrupt routine is entered, the status code in i2stat is used to branch to the appropriate service routine. for each status code, the required software action and details of the following serial transfer are given in tables from table 507 to table 511 . table 504. abbreviations used to describe an i 2 c operation abbreviation explanation s start condition sla 7-bit slave address r read bit (high level at sda) w write bit (low level at sda) a acknowledge bit (low level at sda) a not acknowledge bit (high level at sda) data 8-bit data byte p stop condition sr repeated start condition
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 633 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.1 master transmitter mode in the master transmitter mode, a number of da ta bytes are transmitted to a slave receiver (see figure 117 ). before the master transmitter mode can be entered, i2con must be initialized as follows: the i 2 c rate must also be configured in the i2 scll and i2sclh registers. i2en must be set to logic 1 to enable the i 2 c block. if the aa bit is reset, the i 2 c block will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus. in other words, if aa is reset, the i 2 c interface cannot enter a slave mode. sta, sto, and si must be reset. the master transmitter mode may now be entered by setting the sta bit. the i 2 c logic will now test the i 2 c-bus and generate a start condition as soon as the bus becomes free. when a start condition is transmitted, the seri al interrupt flag (si) is set, and the status code in the status register (i 2stat) will be 0x08. this status code is used by the interrupt service routine to enter the appropriate state service routine that loads i2dat with the slave address and the data direction bit (sla+w ). the si bit in i2con must then be reset before the serial transfer can continue. when the slave address and the direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in i2stat are possible. there are 0x18, 0x20, or 0x38 for the master mode and also 0x68, 0x78, or 0xb0 if the slave mode was enabled (aa = logic 1). the appropriate action to be taken for eac h of these status codes is detailed in ta b l e 5 0 7 . after a repeated start condition (state 0x10). the i 2 c block may switch to the master receiver mode by loading i2dat with sla+r). table 505. i2conset used to initialize master transmitter mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value - 1 0 0 0 x - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 634 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces fig 117. format and states in the master transmitter mode data a r w sla s data a w sla to master receive mode, entry = mr mt to corresponding states in slave mode a or a a or a a other master continues other master continues a other master continues 20h 08h 18h 28h 30h 10h 68h 78h b0h 38h 38h arbitration lost in slave address or data byte not acknowledge received after a data byte not acknowledge received after the slave address next transfer started with a repeated start condition arbitration lost and addressed as slave successful transmission to a slave receiver from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus a p p s p
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 635 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.2 master receiver mode in the master receiver mode, a number of dat a bytes are received from a slave transmitter (see figure 118 ). the transfer is initialized as in the master transmitter mode. when the start condition has been transmitted, the inte rrupt service routine mu st load i2dat with the 7-bit slave address and the data direction bit (sla+r). the si bit in i2con must then be cleared before the serial transfer can continue. when the slave address and the data direction bit have been transmitted and an acknowledgment bit has been received, the serial interrupt flag (si) is set again, and a number of status codes in i2stat are possi ble. these are 0x40, 0x48, or 0x38 for the master mode and also 0x68, 0x78, or 0xb0 if the slave mode was enabled (aa = 1). the appropriate action to be taken for each of these status codes is detailed in table 508 . after a repeated start condition (state 0x10), the i 2 c block may switch to the master transmitter mode by loading i2dat with sla+w.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 636 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces fig 118. format and states in the master receiver mode a to master transmit mode, entry = mt mr to corresponding states in slave mode a r sla s r sla s w a a or a a p other master continues other master continues a other master continues 48h 40h 58h 10h 68h 78h b0h 38h 38h arbitration lost in slave address or acknowledge bit not acknowledge received after the slave address next transfer started with a repeated start condition arbitration lost and addressed as slave successful transmission to a slave transmitter from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus data a data 50h a data p 08h
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 637 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 119 ). to initiate the slave receiver mode, i2con register, the i2adr registers, and the i2mask registers must be configured. the values on the four i2adr registers combined with the values on the four i2mask registers determines which address or addresses the i 2 c block will respond to when slave functions are enabled. see sections 22.7.2 , 22.7.3 , 22.8.7 , and 22.8.8 for details. the i 2 c-bus rate settings do not affect the i 2 c block in the slave mode. i2en must be set to logic 1 to enable the i 2 c block. the aa bit must be set to enable the i 2 c block to acknowledge its own slave address or the gene ral call address. sta, sto, and si must be reset. when the i2adr, i2mask, and i2con re gisters have been initialized, the i 2 c block waits until it is addressed by its ow n slave address followed by the data direction bit which must be ?0? (w) for the i 2 c block to operate in the slave receiver mode. after its own slave address and the w bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from i2stat. this stat us code is used to vector to a state service routine. the appropriate action to be taken fo r each of these status codes is detailed in table 509 . the slave receiver mode may also be enter ed if arbitration is lost while the i 2 c block is in the master mode (see status 0x68 and 0x78). if the aa bit is reset during a transfer, the i 2 c block will return a not acknowledge (logic 1) to sda after the next received data byte. while aa is reset, the i 2 c block does not respond to its own slave address or a general call address. however, the i 2 c-bus is still monitored and address recognition may be resumed at any time by setting aa. this means that the aa bit may be us ed to temporarily isolate the i 2 c block from the i 2 c-bus. table 506. i2conset used to initialize slave receiver mode bit 7 6 5 4 3 2 1 0 symbol - i2en sta sto si aa - - value - 1 0 0 0 1 - -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 638 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces fig 119. format and states in the slave receiver mode a a p or s a w sla s p or s a a 68h 60h 80h 88h reception of the general call address and one or more data bytes arbitration lost as master and addressed as slave last data byte received is not acknowledged arbitration lost as master and addressed as slave by general call reception of the own slave address and one or more data bytes all are acknowledged from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a dened state of the i 2 c bus data a data 80h a0h last data byte is not acknowledged a p or s a 70h 90h data a data 90h a0h general call a 98h p or s a 78h data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 639 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.4 slave transmitter mode in the slave transmitter mode, a number of dat a bytes are transmitted to a master receiver (see figure 120 ). data transfer is init ialized as in the slave receiver mode. when i2adr and i2con have been initialized, the i 2 c block waits until it is addressed by its own slave address followed by the data direction bit which must be ?1? (r) for the i 2 c block to operate in the slave transmitter mode. after its own slave address and the r bit have been received, the serial interrupt flag (si) is set and a valid status code can be read from i2stat. this status code is used to vector to a state service routi ne, and the appropriate action to be taken for each of these status codes is detailed in table 510 . the slave transmitter mode may also be entered if arbitration is lost while the i 2 c block is in the master mode (see state 0xb0). if the aa bit is reset during a transfer, the i 2 c block will transmit the la st byte of the transfer and enter state 0xc0 or 0xc8. the i 2 c block is switched to the not addressed slave mode and will ignore the master receiver if it continues the tr ansfer. thus the master receiver receives all 1s as serial data. while aa is reset, the i 2 c block does not respond to its own slave address or a general call address. however, the i 2 c-bus is still monitored, and address recognition may be resumed at any time by setting aa. this means that the aa bit may be used to temporarily isolate the i 2 c block from the i 2 c-bus. fig 120. format and states in the slave transmitter mode data a a r sla s p or s a a b0h a8h c0h c8h last data byte transmitted. switched to not addressed slave (aa bit in i2con = ?0?) arbitration lost as master and addressed as slave reception of the own slave address and one or more data bytes all are acknowledged from master to slave from slave to master any number of data bytes and their associated acknowledge bits n this number (contained in i2sta) corresponds to a defined state of the i 2 c bus a data b8h all ones a data p or s
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 640 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.5 detailed state tables the following tables show detailed state information for the four i 2 c operating modes. table 507. master transmitter mode i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa 0x08 a start condition has been transmitted. load sla+w; clear sta x 0 0 x sla+w will be transmitted; ack bit will be received. 0x10 a repeated start condition has been transmitted. load sla+w or x 0 0 x as above. load sla+r; clear sta x 0 0 x sla+w will be transmitted; the i 2 c block will be switched to mst/rec mode. 0x18 sla+w has been transmitted; ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no i2dat action or 1 0 0 x repeated start will be transmitted. no i2dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no i2dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x20 sla+w has been transmitted; not ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no i2dat action or 1 0 0 x repeated start will be transmitted. no i2dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no i2dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x28 data byte in i2dat has been transmitted; ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no i2dat action or 1 0 0 x repeated start will be transmitted. no i2dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no i2dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x30 data byte in i2dat has been transmitted; not ack has been received. load data byte or 0 0 0 x data byte will be transmitted; ack bit will be received. no i2dat action or 1 0 0 x repeated start will be transmitted. no i2dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no i2dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x38 arbitration lost in sla+r/w or data bytes. no i2dat action or 0 0 0 x i 2 c-bus will be rel eased; not addressed slave will be entered. no i2dat action 1 0 0 x a start condition will be transmitted when the bus becomes free.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 641 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces table 508. master receiver mode i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa 0x08 a start condition has been transmitted. load sla+r x 0 0 x sla+r will be transmitted; ack bit will be received. 0x10 a repeated start condition has been transmitted. load sla+r or x 0 0 x as above. load sla+w x 0 0 x sla+w will be transmitted; the i 2 c block will be switched to mst/trx mode. 0x38 arbitration lost in not ack bit. no i2dat action or 0 0 0 x i 2 c-bus will be released; the i 2 c block will enter a slave mode. no i2dat action 1 0 0 x a start condition will be transmitted when the bus becomes free. 0x40 sla+r has been transmitted; ack has been received. no i2dat action or 0 0 0 0 data byte will be received; not ack bit will be returned. no i2dat action 0 0 0 1 data byte will be received; ack bit will be returned. 0x48 sla+r has been transmitted; not ack has been received. no i2dat action or 1 0 0 x repeated start condition will be transmitted. no i2dat action or 0 1 0 x stop condition will be transmitted; sto flag will be reset. no i2dat action 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset. 0x50 data byte has been received; ack has been returned. read data byte or 0 0 0 0 data byte will be received; not ack bit will be returned. read data byte 0 0 0 1 data byte will be received; ack bit will be returned. 0x58 data byte has been received; not ack has been returned. read data byte or 1 0 0 x repeated start condition will be transmitted. read data byte or 0 1 0 x stop condition will be transmitted; sto flag will be reset. read data byte 1 1 0 x stop condition followed by a start condition will be transmitted; sto flag will be reset.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 642 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces table 509. slave receiver mode i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa 0x60 own sla+w has been received; ack has been returned. no i2dat action or x 0 0 0 data byte will be received and not ack will be returned. no i2dat action x 0 0 1 data byte w ill be received and ack will be returned. 0x68 arbitration lost in sla+r/w as master; own sla+w has been received, ack returned. no i2dat action or x 0 0 0 data byte will be received and not ack will be returned. no i2dat action x 0 0 1 data byte w ill be received and ack will be returned. 0x70 general call address (0x00) has been received; ack has been returned. no i2dat action or x 0 0 0 data byte will be received and not ack will be returned. no i2dat action x 0 0 1 data byte w ill be received and ack will be returned. 0x78 arbitration lost in sla+r/w as master; general call address has been received, ack has been returned. no i2dat action or x 0 0 0 data byte will be received and not ack will be returned. no i2dat action x 0 0 1 data byte w ill be received and ack will be returned. 0x80 previously addressed with own sla address; data has been received; ack has been returned. read data byte or x 0 0 0 data byte will be received and not ack will be returned. read data byte x 0 0 1 data byte will be received and ack will be returned. 0x88 previously addressed with own sla; data byte has been received; not ack has been returned. read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0x90 previously addressed with general call; data byte has been received; ack has been returned. read data byte or x 0 0 0 data byte will be received and not ack will be returned. read data byte x 0 0 1 data byte will be received and ack will be returned.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 643 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 0x98 previously addressed with general call; data byte has been received; not ack has been returned. read data byte or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. read data byte or 0 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. read data byte or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. read data byte 1 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0xa0 a stop condition or repeated start condition has been received while still addressed as slave receiver or slave transmitter. no stdat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no stdat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. no stdat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no stdat action 1 0 0 1 switched to not addressed slv mode; own sla will be recogni zed; general call address will be recognized if i2adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. table 509. slave receiver mode i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 644 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces table 510. slave transmitter mode i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa 0xa8 own sla+r has been received; ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack will be received. 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received, ack has been returned. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack bit will be received. 0xb8 data byte in i2dat has been transmitted; ack has been received. load data byte or x 0 0 0 last data byte will be transmitted and ack bit will be received. load data byte x 0 0 1 data byte will be transmitted; ack bit will be received. 0xc0 data byte in i2dat has been transmitted; not ack has been received. no i2dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no i2dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if i2adr[0] = logic 1. no i2dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no i2dat action 1 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if i2adr[0] = logic 1. a start condition will be transmitted when the bus becomes free. 0xc8 last data byte in i2dat has been transmitted (aa = 0); ack has been received. no i2dat action or 0 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. no i2dat action or 0 0 0 1 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if i2adr[0] = logic 1. no i2dat action or 1 0 0 0 switched to not addressed slv mode; no recognition of own sla or general call address. a start condition will be transmitted when the bus becomes free. no i2dat action 1 0 0 01 switched to not addressed slv mode; own sla will be recognized; general call address will be recognized if i2adr.0 = logic 1. a start condition will be transmitted when the bus becomes free.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 645 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.6 miscellaneous states there are two i2stat codes that do not correspond to a defined i 2 c hardware state (see ta b l e 5 11 ). these are discussed below. 22.9.6.1 i2stat = 0xf8 this status code indicates that no relevant information is available because the serial interrupt flag, si, is not yet set. this occurs between other states and when the i 2 c block is not involved in a serial transfer. 22.9.6.2 i2stat = 0x00 this status code indicates that a bus error has occurred during an i 2 c serial transfer. a bus error is caused when a star t or stop conditio n occurs at an illegal position in the format frame. examples of su ch illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. a bus error may also be caused when external interference disturbs the internal i 2 c block signals. when a bus error occurs, si is set. to recover from a bus error, the sto flag must be set and si must be cleared. this causes the i 2 c block to enter the ?not addressed? slave mode (a defined state) and to clear the sto flag (no other bits in i2con are affected). the sda and scl lines are released (a stop condition is not transmitted). table 511. miscellaneous states i2cstat status code status of the i 2 c-bus and hardware application software response next action taken by i 2 c hardware to/from i2dat to i2con sta sto si aa 0xf8 no relevant state information available; si = 0. no i2dat action no i2con action wait or proceed current transfer. 0x00 bus error during mst or selected slave modes, due to an illegal start or stop condition. state 0x00 can also occur when interference causes the i 2 c block to enter an undefined state. no i2dat action 0 1 0 x only the internal hardware is affected in the mst or addressed slv modes. in all cases, the bus is released and the i 2 c block is switched to the not addressed slv mode. sto is reset.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 646 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.7 some special cases the i 2 c hardware has facilities to handle the following special ca ses that may occur during a serial transfer: 22.9.7.1 simultaneous repeated start conditions from two masters a repeated start condition may be generated in the master transmitter or master receiver modes. a special case occurs if another master simultaneously generates a repeated start condition (see figure 121 ). until this occurs, arbi tration is not lost by either master since they were both transmitting the same data. if the i 2 c hardware detects a repeated start condition on the i 2 c-bus before generating a repeated start condition itse lf, it will release the bus, and no in terrupt re quest is generated. if another master frees the bu s by generating a stop condition, the i 2 c block will transmit a normal start co ndition (state 0x08), and a re try of the total serial data transfer can commence. 22.9.7.2 data transfer after loss of arbitration arbitration may be lost in the master tr ansmitter and master receiver modes (see figure 115 ). loss of arbitration is indicated by the following states in i2stat; 0x38, 0x68, 0x78, and 0xb0 (see figure 117 and figure 118 ). if the sta flag in i2con is set by the routines which service these states, then, if the bus is free again, a start condition (state 0x08) is transmitted without intervention by the cpu, and a retry of the total serial transfer can commence. 22.9.7.3 forced access to the i 2 c-bus in some applications, it may be possible for an uncontrolled source to cause a bus hang-up. in such situations, the problem may be caused by interference, temporary interruption of the bus or a temporary short-circuit between sda and scl. if an uncontrolled source generates a superfluous start or masks a stop condition, then the i 2 c-bus stays busy indefinitely. if the sta flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the i 2 c-bus is possible. this is achieved by setting the sto flag while the st a flag is still set. no stop condition is transmitted. the i 2 c hardware behaves as if a stop condition was received and is able to transmit a start condition. the sto flag is cleared by hardware figure 122 . 22.9.7.4 i 2 c-bus obstructed by a low level on scl or sda an i 2 c-bus hang-up can occur if either the sda or scl line is held low by any device on the bus. if the scl line is obstructed (pulled lo w) by a device on the bus, no further serial transfer is possible, and the problem must be resolved by t he device that is pulling the scl bus line low. typically, the sda line may be obstructed by another device on the bus that has become out of synchronization with the current bus master by either mi ssing a clock, or by sensing a noise pulse as a clock. in this case, the problem can be solved by transmitting additional clock pulses on the scl line figure 123 . the i 2 c interface does not include a dedicated timeout timer to detect an obstructed bus, but this can be implemented using another timer in the system. when detected, software can force clocks (up to 9 may be required)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 647 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces on scl until sda is released by the offendin g device. at that point, the slave may still be out of synchronization, so a start should be generated to insure that all i 2 c peripherals are synchronized. 22.9.7.5 bus error a bus error occurs when a start or stop cond ition is detected at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data bit, or an acknowledge bit. the i 2 c hardware only reacts to a bus error when it is involved in a serial transfer either as a master or an addressed slave. when a bus error is detected, the i 2 c block immediately switches to the not addressed slave mode, releases the sda and scl lines, sets the interrupt flag, and loads the status register with 0x00. this status code may be used to vector to a state service routin e which either attempts the aborted serial transfer again or simply recovers from the error condition as shown in table 511 . fig 121. simultaneous repeated start conditions from two masters fig 122. forced access to a busy i 2 c-bus sla aw sla s 18h 08h a data 28h 08h other master continues other master sends repeated start earlier s retry s p sda line scl line sta flag sto flag time limit start condition
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 648 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces (1) unsuccessful attempt to send a start condition. (2) sda line is released. (3) successful attempt to send a start condition. state 08h is entered. fig 123. recovering from a bus obstruction caused by a low level on sda sda line scl line (1) (2) (1) (3) sta flag start condition
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 649 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.9.8 i 2 c state service routines this section provides examples of operations that must be performed by various i 2 c state service routines. this includes: ? initialization of the i 2 c block after a reset. ? i 2 c interrupt service ? the 26 state service routines providing support for all four i 2 c operating modes. 22.9.8.1 initialization in the initialization example, the i 2 c block is enabled for both master and slave modes. for each mode, a buffer is used for transmissi on and reception. the initialization routine performs the following functions: ? the i2adr registers and i2mask registers ar e loaded with values to configure the part?s own slave address(es) and the general call bit (gc) ? the i 2 c interrupt enable and interrupt priority bits are set ? the slave mode is enabled by simultaneously setting the i2en and aa bits in i2con and the serial clock frequency (for master modes) is defined by loading the i2sclh and i2scll registers. the master routines must be started in the main program. the i 2 c hardware now begins checking the i 2 c-bus for its own slave address and general call. if the general call or the own slave add ress is detected, an interrupt is requested and i2stat is loaded with the appropriate state information. 22.9.8.2 i 2 c interrupt service when the i 2 c interrupt is entered, i2stat contains a status code which identifies one of the 26 state services to be executed. 22.9.8.3 the state service routines each state routine is part of the i 2 c interrupt routine and handles one of the 26 states. 22.9.8.4 adapting state services to an application the state service examples show the typical actions that must be performed in response to the 26 i 2 c state codes. if one or more of the four i 2 c operating modes are not used, the associated state services can be omitted, as long as care is taken that the those states can never occur. in an application, it may be desirable to implement some kind of timeout during i 2 c operations, in order to trap an inoper ative bus or a lost service routine.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 650 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10 software example 22.10.1 initialization routine example to initialize i 2 c interface as a slave and/or master. 1. load the i2adr registers and i2mask registers with values to configure the own slave address, enable general call recognition if needed. 2. enable i 2 c interrupt. 3. write 0x44 to i2conset to set the i2en and aa bits, enabling slave functions. for master only functions, write 0x40 to i2conset. 22.10.2 start master transmit function begin a master transmit operation by settin g up the buffer, pointer, and data count, then initiating a start. 1. initialize master data counter. 2. set up the slave address to which data will be transmitted, and add the write bit. 3. write 0x20 to i2con set to set the sta bit. 4. set up data to be transmitted in master transmit buffer. 5. initialize the master data counter to ma tch the length of the message being sent. 6. exit 22.10.3 start master receive function begin a master receive operation by setting up the buffer, pointer, and data count, then initiating a start. 1. initialize master data counter. 2. set up the slave address to which data will be transmitted, and add the read bit. 3. write 0x20 to i2con set to set the sta bit. 4. set up the master receive buffer. 5. initialize the master data counter to match the length of the message to be received. 6. exit 22.10.4 i 2 c interrupt routine determine the i 2 c state and which state routin e will be used to handle it. 1. read the i 2 c status from i2sta. 2. use the status value to branch to one of 26 possible state routines.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 651 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.5 non mode specific states 22.10.5.1 state: 0x00 bus error. enter not addressed slave mode and release bus. 1. write 0x14 to i2conset to set the sto and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.5.2 master states state 0x08 and state 0x10 are for both mast er transmit and master receive modes. the r/w bit decides whether the next state is with in master transmit mode or master receive mode. 22.10.5.3 state: 0x08 a start condition has been transmitted. the slave ad dress + r/w bit will now be transmitted. 1. write slave address with r/w bit to i2dat. 2. write 0x04 to i2conset to set the aa bit. 3. write 0x08 to i2conclr to clear the si flag. 4. set up master transmit mode data buffer. 5. set up master receive mode data buffer. 6. initialize master data counter. 7. exit 22.10.5.4 state: 0x10 a repeated start cond ition has been transmitted. the slave address + r/w bit will now be transmitted. 1. write slave address with r/w bit to i2dat. 2. write 0x04 to i2conset to set the aa bit. 3. write 0x08 to i2conclr to clear the si flag. 4. set up master transmit mode data buffer. 5. set up master receive mode data buffer. 6. initialize master data counter. 7. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 652 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.6 master transmitter states 22.10.6.1 state: 0x18 previous state was state 0x08 or state 0x10, slave address + write has been transmitted, ack has been received. the first data byte will be transmitted. 1. load i2dat with first data byte from master transmit buffer. 2. write 0x04 to i2conset to set the aa bit. 3. write 0x08 to i2conclr to clear the si flag. 4. increment master transmit buffer pointer. 5. exit 22.10.6.2 state: 0x20 slave address + write has been transmitted, not ack has been received. a stop condition will be transmitted. 1. write 0x14 to i2conset to set the sto and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.6.3 state: 0x28 data has been transmitted, ack has been received. if the transmitted data was the last data byte then transmit a stop condition, otherwise transmit the next data byte. 1. decrement the master data counter, skip to step 5 if not the last data byte. 2. write 0x14 to i2conset to set the sto and aa bits. 3. write 0x08 to i2conclr to clear the si flag. 4. exit 5. load i2dat with next data byte from master transmit buffer. 6. write 0x04 to i2conset to set the aa bit. 7. write 0x08 to i2conclr to clear the si flag. 8. increment master transmit buffer pointer 9. exit 22.10.6.4 state: 0x30 data has been transmitted, not ack receiv ed. a stop condition will be transmitted. 1. write 0x14 to i2conset to set the sto and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 653 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.6.5 state: 0x38 arbitration has been lost during slave address + write or data. the bus has been released and not addr essed slave mode is entered. a new start condition will be transmitted when the bus is free again. 1. write 0x24 to i2conset to set the sta and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 654 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.7 master receiver states 22.10.7.1 state: 0x40 previous state was state 08 or state 10. slave address + read has been transmitted, ack has been received. data will be received an d ack returned. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.7.2 state: 0x48 slave address + read has been transmitted, not ack has been received. a stop condition will be transmitted. 1. write 0x14 to i2conset to set the sto and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.7.3 state: 0x50 data has been received, ack ha s been returned. data will be read from i2dat. additional data will be received. if this is the last data byte then not ack will be returned, otherwise ack will be returned. 1. read data byte from i2dat into master receive buffer. 2. decrement the master data counter, skip to step 5 if not the last data byte. 3. write 0x0c to i2co nclr to clear the si flag and the aa bit. 4. exit 5. write 0x04 to i2conset to set the aa bit. 6. write 0x08 to i2conclr to clear the si flag. 7. increment master receive buffer pointer 8. exit 22.10.7.4 state: 0x58 data has been received, not ac k has been returned. data w ill be read from i2dat. a stop condition will be transmitted. 1. read data byte from i2dat into master receive buffer. 2. write 0x14 to i2conset to set the sto and aa bits. 3. write 0x08 to i2conclr to clear the si flag. 4. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 655 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.8 slave receiver states 22.10.8.1 state: 0x60 own slave address + write has been received, ack has been returned. data will be received and ack returned. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit 22.10.8.2 state: 0x68 arbitration has been lost in slave address and r/w bit as bus master. own slave address + write has been received, ac k has been return ed. data will be rece ived and ack will be returned. sta is set to restart master mode after the bus is free again. 1. write 0x24 to i2conset to set the sta and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit. 22.10.8.3 state: 0x70 general call has been received, ack has been returned. data will be received and ack returned. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit 22.10.8.4 state: 0x78 arbitration has been lost in slave address + r/w bit as bus master. general call has been received and ack has b een returned. data will be re ceived and ack returned. sta is set to restart master mode after the bus is free again. 1. write 0x24 to i2conset to set the sta and aa bits. 2. write 0x08 to i2conclr to clear the si flag. 3. set up slave receive mode data buffer. 4. initialize slave data counter. 5. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 656 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.8.5 state: 0x80 previously addressed with own slave addr ess. data has been received and ack has been returned. addition al data will be read. 1. read data byte from i2dat into the slave receive buffer. 2. decrement the slave data counter, skip to step 5 if not the last data byte. 3. write 0x0c to i2co nclr to clear the si flag and the aa bit. 4. exit. 5. write 0x04 to i2conset to set the aa bit. 6. write 0x08 to i2conclr to clear the si flag. 7. increment slave receive buffer pointer. 8. exit 22.10.8.6 state: 0x88 previously addressed with own slave addr ess. data has been received and not ack has been returned. received data will not be saved. not addressed slave mode is entered. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.8.7 state: 0x90 previously addressed with gener al call. data has been received, ack has been returned. received data will be saved. on ly the first data byte will be received with ack. additional data will be received with not ack. 1. read data byte from i2dat into the slave receive buffer. 2. write 0x0c to i2co nclr to clear the si flag and the aa bit. 3. exit 22.10.8.8 state: 0x98 previously addressed with general call. data has been received, not ack has been returned. received data will not be saved. no t addressed slave mode is entered. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit 22.10.8.9 state: 0xa0 a stop condition or repeated start has been received, while still addressed as a slave. data will not be saved. not addressed slave mode is entered. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 657 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.9 slave tran smitter states 22.10.9.1 state: 0xa8 own slave address + read ha s been received, ack has been return ed. data will be transmitted, ack bi t will be received. 1. load i2dat from slave transmit buffer with first data byte. 2. write 0x04 to i2conset to set the aa bit. 3. write 0x08 to i2conclr to clear the si flag. 4. set up slave transmit mode data buffer. 5. increment slave transmit buffer pointer. 6. exit 22.10.9.2 state: 0xb0 arbitration lost in slave address and r/w bit as bus master. own slave address + read has been received, ack has been returned. data will be transmitted, ack bit will be received. sta is set to restart master mode after the bus is free again. 1. load i2dat from slave transmit buffer with first data byte. 2. write 0x24 to i2conset to set the sta and aa bits. 3. write 0x08 to i2conclr to clear the si flag. 4. set up slave transmit mode data buffer. 5. increment slave transmit buffer pointer. 6. exit 22.10.9.3 state: 0xb8 data has been transmitted, ac k has been received. data will be transmitted, ack bit will be received. 1. load i2dat from slave transmit buffer with data byte. 2. write 0x04 to i2conset to set the aa bit. 3. write 0x08 to i2conclr to clear the si flag. 4. increment slave transmit buffer pointer. 5. exit 22.10.9.4 state: 0xc0 data has been transmitted, not ack has bee n received. not addre ssed slave mode is entered. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 658 of 942 nxp semiconductors UM10562 chapter 22: lpc408x/407x i2c-bus interfaces 22.10.9.5 state: 0xc8 the last data byte has been transmitted, ack has been received. not addressed slave mode is entered. 1. write 0x04 to i2conset to set the aa bit. 2. write 0x08 to i2conclr to clear the si flag. 3. exit
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 659 of 942 23.1 basic configuration the i 2 s interface is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pci2s. remark: on reset, the i 2 s interface is disabled (pci2s = 0). 2. peripheral clock: the functional portion of the i 2 s interface operates from the cpu clock (cclk), rather than pclk. the bus interface operates fr om the common pclk for apb peripherals. see section 3.3.3.5 . 3. pins: select i 2 s pins and their modes in the relevant iocon registers (see section 7.4.1 ). 4. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 5. dma: the i 2 s interface supports two dma requests, see table 519 and table 520 , and table 692 . UM10562 chapter 23: lpc408x/407x i 2 s interface rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 660 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.2 features the i 2 s bus provides a standard communication interface for digital audio applications. the i 2 s bus specification defines a 3-wire serial bus, having one data, one clock, and one word select signal. the basic i 2 s connection has one master, which is always the master, and one slave. the i 2 s interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave, and an optional oversample master clock output (mclk). ? the i 2 s input can operate in both master and slave mode. ? the i 2 s output can operate in both master an d slave mode, independent of the input. ? capable of handling 8-bit, 16-bit, and 32-bit word sizes. ? mono and stereo audio data supported. ? versatile clocking includes independent transmit and receive fractional rate generators, a nd an ability to use a single clock in put or output fo r a 4-wire mode. ? sampling frequencies (fs) supported include standard 16 to 96 khz ranges (16, 22.05, 32, 44.1, 48, or 96 khz) for audio applications, and above, depending on the clock frequency. ? separate master clock outputs for both transmit and receive channels support a clock up to 512 times the i 2 s sampling frequency. ? word select period in ma ster mode is separate ly configurable for i 2 s input and output. ? two 8 word (32 byte) fifo data buffers, one set each for transmit and receive. ? generates interrupt requests when buffer levels cross a programmable boundary. ? two dma requests, controlled by programma ble buffer levels. these are connected to the general purpose dma block. ? controls include reset, stop and mute options separately for i 2 s input and i 2 s output. ? optional mclk (oversample) output.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 661 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.3 description the i 2 s performs serial data out via the transmit channel and serial data in via the receive channel. these support the nxp inter ic audio format for 8-bit, 16-bit and 32-bit audio data, both for stereo and mono modes. configuration, data access and control is performed by a apb register set. data stream s are buffered by fifos with a depth of 8 words. the i 2 s receive and transmit stage can operate in dependently in either slave or master mode. within the i 2 s module the difference between these modes lies in the word select (ws) signal which determines the timing of data transmissions. data words start on the next falling edge of the transmitting clock after a ws change. in stereo mode when ws is low left data is transmitted and right data when ws is high. in mono mode the same data is transmitted twice, once when ws is low and again when ws is high. ? in master mode, word select is generated internally with a 9-bit counter. the half period count value of this counter can be set in the control register. ? in slave mode, word select is input from the relevant bus pin. ? when an i 2 s bus is active, the word select, receive clock and transmit clock signals are sent continuously by the bus master, while data is sent continuously by the transmitter. ? disabling the i 2 s can be done with the stop or mute control bits separately for the transmit and receive. ? the stop bit will disable acce sses by the transmit channel or the receive channel to the fifos and will place the tran smit channel in mute mode. ? the mute control bit will place the transmit channel in mute mode. in mute mode, the transmit channel fifo operates normally, but the output is discarded and replaced by zeroes. this bit does not affect the receive channel, data reception can occur normally.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 662 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.4 pin descriptions table 512. pin descriptions pin name type description i2s_rx_clk input/ output receive clock. a clock signal used to synchronize the transfer of data on the receive channel. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s bus specification. when this pin is an input, each level on this pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. i2s_rx_ws input/ output receive word select. selects the channel from whic h data is to be received. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s bus specification. ws = 0 indicates that data is being received by channel 1 (left channel). ws = 1 indicates that data is being received by channel 2 (right channel). i2s_rx_sda input/ output receive data. serial data, received msb first. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s bus specification. i2s_rx_mclk output optional master clock output for the i 2 s receive function. i2s_tx_clk input/ output transmit clock. a clock signal used to synchronize the transfer of data on the transmit channel. it is driven by the master and received by the slave. corresponds to the signal sck in the i 2 s bus specification. when this pin is an input, each level on this pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. i2s_tx_ws input/ output transmit word select. selects the channel to which data is being sent. it is driven by the master and received by the slave. corresponds to the signal ws in the i 2 s bus specification. ws = 0 indicates that data is being sent to channel 1 (left channel). ws = 1 indicates that data is being sent to channel 2 (right channel). i2s_tx_sda input/ output transmit data. serial data, sent msb first. it is driven by the transmitter and read by the receiver. corresponds to the signal sd in the i 2 s bus specification. i2s_tx_mclk output optional master clock output for the i 2 s transmit function.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 663 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 124. simple i 2 s configurations and bus timing transmitter (master) controller (master) transmitter (slave) receiver (master) sck: serial clock ws: word select sd: serial data transmitter (slave) receiver (slave) sck ws sd sck ws sd msb lsb msb word n left channel word n+1 right channel word n-1 right channel receiver (slave) sck: serial clock ws: word select sd: serial data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 664 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5 register description [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 513. register overview: i 2 s (base address 0x400a 8000) name access address offset description reset value [1] table dao r/w 0x000 digital audio output register. contains control bits for the i 2 s transmit channel. 0x87e1 514 dai r/w 0x004 digital audio input register. contains control bits for the i 2 s receive channel. 0x07e1 515 txfifo wo 0x008 transmit fifo. access register for the 8 ? 32-bit transmitter fifo. 0 516 rxfifo ro 0x00c receive fifo. access register for the 8 ? 32-bit receiver fifo. 0 517 state ro 0x010 status feedback register. contains status information about the i 2 s interface. 0x7 518 dma1 r/w 0x014 dma configuration register 1. contains control information for dma request 1. 0 519 dma2 r/w 0x018 dma configuration register 2. contains control information for dma request 2. 0 520 irq r/w 0x01c interrupt request control register. contains bits that control how the i 2 s interrupt request is generated. 0 521 txrate r/w 0x020 transmit reference clock divider. this register determines the i 2 s tx_ref rate by specifying the value to divide cclk by in order to produce tx_ref. 0 522 rxrate r/w 0x024 receive reference clock divider. this register determines the i 2 s rx_ref rate by specifying the value to divide cclk by in order to produce rx_ref. 0 523 txbitrate r/w 0x028 transmit bit rate divider. this register determines the i 2 s transmit bit rate by specifying the value to divide tx_ref by in order to produce the transmit bit clock. 0 524 rxbitrate r/w 0x02c receive bit rate divider. this register determines the i 2 s receive bit rate by specifying the value to divide rx_ref by in order to produce the receive bit clock. 0 525 txmode r/w 0x030 transmit mode control. 0 526 rxmode r/w 0x034 receive mode control. 0 527
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 665 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.1 digital audio output register the i2sdao register controls the operation of the i 2 s transmit channel. the function of bits in dao are shown in table 514 . 23.5.2 digital audio input register the i2sdai register controls the operation of the i 2 s receive channel. the function of bits in dai are shown in table 515 . table 514: digital audio output register (dao - address 0x400a 8000) bit description bit symbol value description reset value 1:0 wordwidth selects the number of bytes in data as follows: 01 0x0 8-bit data 0x1 16-bit data 0x2 reserved, do not use this setting 0x3 32-bit data 2 mono when 1, data is of monaural format. when 0, the data is in stereo format. 0 3 stop when 1, disables accesses on fifos, places the transmit channel in mute mode. 0 4 reset when 1, asynchronously resets the transmit channel and fifo. 0 5 ws_sel when 0, the interface is in master mode. when 1, the interface is in slave mode. see section 23.7 for a summary of useful combinations for this bit with i2stxmode. 1 14:6 ws_halfperiod word select half period minus 1, i.e. ws 64clk period -> ws_halfperiod = 31. 0x1f 15 mute when 1, the transmit channel sends only zeroes. 1 31:16 - reserved. read value is undefined, only zero should be written. na table 515: digital audio input register (dai - address 0x400a 8004) bit description bit symbol value description reset value 1:0 wordwidth selects the number of bytes in data as follows: 01 0x0 8-bit data 0x1 16-bit data 0x2 reserved, do not use this setting 0x3 32-bit data 2 mono when 1, data is of monaural format. when 0, the data is in stereo format. 0 3 stop when 1, disables accesses on fifo s, places the transmit channel in mute mode. 0 4 reset when 1, asynchronously reset the transmit channel and fifo. 0 5 ws_sel when 0, the interface is in master mode. when 1, the interface is in slave mode. see section 23.7 for a summary of useful combinations for this bit with i2srxmode. 1 14:6 ws_halfperiod word select half period minus 1, i.e. ws 64clk period -> ws_halfperiod = 31. 0x1f 31:15 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 666 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.3 transmit fifo register the i2stxfifo register provides access to the transmit fifo. the function of bits in i2stxfifo are shown in table 516 . 23.5.4 receive fifo register the i2srxfifo register provides access to the receive fifo. the function of bits in i2srxfifo are shown in table 517 . 23.5.5 status feedback register the i2sstate register provides status information about the i 2 s interface. the meaning of bits in i2sstate are shown in table 518 . table 516: transmit fifo register (txfifo - address 0x400a 8008) bit description bit symbol description reset value 31:0 i2stxfifo 8 ? 32-bit transmit fifo. level = 0 table 517: receive fifo register (rxfifo - address 0x400a 800c) bit description bit symbol description reset value 31:0 i2srxfifo 8 ? 32-bit transmit fifo. level = 0 table 518: status feedback register (state - address 0x400a 8010) bit description bit symbol description reset value 0 irq this bit reflects the presence of receive interrupt or transmit interrupt. this is determined by comparing the current fifo levels to the rx_ depth_irq and tx_depth_irq fields in the i2sirq register. 1 1 dmareq1 this bit reflects the presence of receive or transmit dma request 1. this is determined by comparing the current fifo levels to the rx_depth_dma1 and tx_depth_dma1 fields in the i2sdma1 register. 1 2 dmareq2 this bit reflects the presence of receive or transmit dma request 2. this is determined by comparing the current fifo levels to the rx_depth_dma2 and tx_depth_dma2 fields in the i2sdma2 register. 1 7:3 - unused. 0 11:8 rx_level reflects the current level of the receive fifo. 0 15:12 - reserved. read value is undefined, only zero should be written. na 19:16 tx_level reflects the current level of the transmit fifo. 0 31:20 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 667 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.6 dma configur ation register 1 the i2sdma1 register controls the operation of dma request 1. the function of bits in i2sdma1 are shown in table 519 . refer to the general purpose dma controller chapter for details of dma operation. 23.5.7 dma configur ation register 2 the i2sdma2 register controls the operation of dma request 2. the function of bits in i2sdma2 are shown in table 514 . table 519: dma configuration register 1 (dma1 - address 0x400a 8014) bit description bit symbol description reset value 0 rx_dma1_enable when 1, enables dma1 for i 2 s receive. 0 1 tx_dma1_enable when 1, enables dma1 for i 2 s transmit. 0 7:2 - reserved. read value is undefined, only zero should be written. 0 11:8 rx_depth_dma1 set the fifo level that triggers a receive dma request on dma1. 0 15:12 - reserved. read value is undefined, only zero should be written. na 19:16 tx_depth_dma1 set the fifo level that triggers a transmit dma request on dma1. 0 31:20 - reserved. read value is undefined, only zero should be written. na table 520: dma configuration register 2 (dma2 - address 0x400a 8018) bit description bit symbol description reset value 0 rx_dma2_enable when 1, enables dma1 for i 2 s receive. 0 1 tx_dma2_enable when 1, enables dma1 for i 2 s transmit. 0 7:2 - unused. 0 11:8 rx_depth_dma2 set the fifo level that triggers a receive dma request on dma2. 0 15:12 - reserved. read value is undefined, only zero should be written. na 19:16 tx_depth_dma2 set the fifo level that triggers a transmit dma request on dma2. 0 31:20 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 668 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.8 interrupt request control register the i2sirq register controls the operation of the i 2 s interrupt request. the function of bits in i2sirq are shown in table 514 . 23.5.9 transmit clock rate register the tx_ref rate for the i 2 s transmitter is determined by the values in the i2stxrate register. the required i2stxrate setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size. when the mclk output is enabled for the transmit function, it is tx _ref that is sent to the i2s_tx_mclk pin. the tx_ref rate is generated using a frac tional rate generator, dividing down the frequency of cclk. values of the numerator (x) and the denominator (y) must be chosen to produce a frequency twice that desired fo r tx_ref, which must be an integer multiple of the transmitter bit clock rate. fractional rate generators have some aspects that the user should be aware of when choosing settings. these are discussed in section 23.5.9.1 . the equation for the fractional rate generator is: i2s tx_ref = cclk * (x/y) /2 note: if the value of x or y is 0, the clock divider is bypassed. also, the value of y must be greater than or equal to x. table 521: interrupt request control register (irq - address 0x400a 801c) bit description bit symbol description reset value 0 rx_irq_enable when 1, enables i 2 s receive interrupt. 0 1 tx_irq_enable when 1, enables i 2 s transmit interrupt. 0 7:2 - unused. 0 11:8 rx_depth_irq set the fifo level on which to create an irq request. 0 15:12 - reserved. read value is undefined, only zero should be written. na 19:16 tx_depth_irq set the fifo level on which to create an irq request. 0 31:20 - reserved. read value is undefined, only zero should be written. na table 522: transmit clock rate register (txrate - address 0x400a 8020) bit description bit symbol description reset value 7:0 y_divider i 2 s transmit tx_ref rate denominator. this value is used to divide cclk to produce tx_ref. eight bits of fractional divide supports a wide range of possibilities. a value of 0 causes the clock divider to be bypassed. 0 15:8 x_divider i 2 s transmit tx_ref rate numerator. this value is used to multiply cclk by to produce the tx_ref. a value of 0 causes the clock divider to be bypassed. eight bits of fractional divide supports a wide range of possibilities. note: the resulting ratio x/y is divided by 2. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 669 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.9.1 notes on fractional rate generators the nature of a fractional rate generator is that there will be some ou tput jitter with some divide settings. this is because the fractional rate generator is a fully digital function, so output clock transitions are synchronous with the source clock, whereas a theoretical perfect fractional rate may have edges that are not related to the source clock. so, output jitter will not be greater than plus or minus one source clock betwe en consecutive clock edges. for example, if x = 0x07 and y = 0x11, the fractional rate gene rator will output 7 clocks for every 17 (11 hex) input clocks, distributed as even ly as it can. in this example, there is no way to distribute the output clocks in a perfectly even fa shion, so some clocks will be longer than others. the output is divided by 2 in order to square it up, which also helps with the jitter. the frequency av erages out to exactly (7/17) / 2, but some clocks will be a slightly different length than their neighbors. it is possible to avoid jitter entirely by choosing fractions such that x divides evenly into y, such as 2/4, 2/6, 3/9, 1/n, etc. 23.5.10 receive clock rate register the rx_ref rate for the i 2 s receiver is determined by the values in the i2srxrate register. the required i2srxrate setting de pends on the cpu clock rate (cclk) and the desired rx_ref rate (such as 256 fs). when the mclk output is enabled for the receive function, it is rx_ref that is sent to the i2s_rx_mclk pin. the rx_ref rate is generated using a frac tional rate generator, dividing down the frequency of cclk. values of the numerator (x) and the denominator (y) must be chosen to produce a frequency twice that desired for the rx_ref, which must be an integer multiple of the re ceiver bit clock rate. fractional rate generators have some aspects that the user should be aware of when choosing settings. these are discussed in section 23.5.9.1 . the equation for the fractional rate generator is: i2s rx_ref = cclk * (x/y) /2 note: if the value of x or y is 0, the clock divider is bypassed. also, the value of y must be greater than or equal to x. table 523: receive clock rate register (rxrate - address 0x400a 8024) bit description bit symbol description reset value 7:0 y_divider i 2 s receive rx_ref rate denominator. this value is used to divide cclk to produce rx_ref. eight bits of fractional divide supports a wide range of possibilities. a value of 0 causes the clock divider to be bypassed. 0 15:8 x_divider i 2 s receive rx_ref rate numerator. this value is used to multiply cclk by to produce rx_ref. a value of 0 causes the clock divider to be bypassed. eight bits of fractional divide supports a wide range of possibilities. note: the resulting ratio x/y is divided by 2. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 670 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.11 transmit clock bit rate register the bit rate for the i 2 s transmitter is determined by the value of the i2stxbitrate register. the value depends on the audio sample rate desired, and the data size and format (stereo/mono) used. for example, a 48 khz sample rate for 16-bit stereo data requires a bit rate of 48,000 ? 16 ? 2 = 1.536 mhz. 23.5.12 receive clock bit rate register the bit rate for the i 2 s receiver is determined by the value of the i2srxbitrate register. the value depends on the audio sample rate, as well as the data size and format used. the calculation is the same as for i2srxbitrate. 23.5.13 transmit mode control register the transmit mode control register contains additional controls for transmit clock source, enabling the 4-pin mode, how tx_ref is used , and whether the mclk output is enabled. see section 23.7 for a summary of useful mode combinations. table 524: transmit clock bit rate register (txbitrate - address 0x400a 8028) bit description bit symbol description reset value 5:0 tx_bitrate i 2 s transmit bit rate. this value plus one is us ed to divide tx_ref to produce the transmit bit clock. 0 31:6 - reserved. read value is undefined, only zero should be written. na table 525: receive clock rate bit register (rxbitrate - address 0x400a 802c) bit description bit symbol description reset value 5:0 rx_bitrate i 2 s receive bit rate. this value plus one is used to divide rx_ref to produce the receive bit clock. 0 31:6 - reserved. read value is undefined, only zero should be written. na table 526: transmit mode control register (txmode - 0x400a 8030) bit description bit symbol value description reset value 1:0 txclksel clock source selection for the transmit bit clock divider. 0 0x0 select the tx fractional rate divider clock output as the source 0x1 reserved 0x2 select the rx_ref signal as the tx_ref clock source 0x3 reserved 2 tx4pin transmit 4-pin mode selection. when 1, enables 4-pin mode. 0 3 txmcena enable for the tx_mclk output. 0 0 output of tx_mclk to a pin is disabled. 1 output of tx_mclk to a pin is enabled. 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 671 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.5.14 receive mode control register the receive mode control register contains additional controls for receive clock source, enabling the 4-pin mode, and how rx_ref is used. see section 23.7 for a summary of useful mode combinations. table 527: receive mode control register (rxmode - 0x400a 8034) bit description bit symbol value description reset value 1:0 rxclksel clock source selection fo r the receive bit clock divider. 0 0x0 select the rx fractional rate divider clock output as the source 0x1 reserved 0x2 select the tx_ref signal as the rx_ref clock source 0x3 reserved 2 rx4pin receive 4-pin mode selection. when 1, enables 4-pin mode. 0 3 rxmcena enable for the rx_mclk output. 0 0 output of rx_mclk to a pin is disabled. 1 output of rx_mclk to a pin is enabled. 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 672 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.6 i 2 s transmit and r eceive interfaces the i 2 s interface can transmit and receive 8-bit, 16-bit or 32-bit stereo or mono audio information. some details of i 2 s implementation are: ? when the fifo is empty, th e transmit channel will repeat transmitting the same data until new data is written to the fifo. ? when mute is true, the da ta value 0 is transmitted. ? when mono is false, two successive data words are respectively left and right data. ? data word length is determined by the wo rdwidth value in the configuration register. there is a separate wordwidth value for the receive channel and the transmit channel. ? 0: word is considered to contain four 8-bit data words. ? 1: word is considered to contain two 16-bit data words. ? 3: word is considered to contain one 32-bit data word. ? when the transmit fifo contains insufficient data the transmit channe l will repeat transmitting the last data until new data is available. this can occur when the microprocessor or the dma at some time is unable to provide new data fast enough. because of this delay in new data ther e is a need to f ill the gap, which is accomplished by continuing to transmit the last sample. the data is not muted as this would produce an noticeable and undesirable effect in the sound. ? the transmit channel and the receive channel only handle 32-bit aligned words, data chunks must be clipped or extended to a multiple of 32 bits. when switching between data width or modes the i 2 s must be reset via the reset bit in the control register in order to ensure correct synchr onization. it is advisable to set the stop bit also until sufficient data has been written in the transmit fifo. note that when stopped data output is muted. all data accesses to fifos are 32 bits. figure 138 shows the possible data sequences. a data sample in the fifo consists of: ? 1 ? 32 bits in 8-bit or 16-bit stereo modes. ? 1 ? 32 bits in mono modes. ? 2 ? 32 bits, first left data, second right data, in 32-bit stereo modes. data is read from the transmit fifo after the fallin g edge of ws, it w ill be transferred to the transmit clock domain after the rising edge of ws. on the next falling edge of ws the left data will be loaded in the shift register and tr ansmitted and on the fo llowing rising edge of ws the right data is loaded and transmitted. the receive ch annel will start receiving data after a change of ws. when word select becomes low it expects this data to be left data, when ws is high received data is expected to be right data. reception will stop when the bit counter has reached the limit set by wordwidth. on the ne xt change of ws the received data will be stored in the appropriate hold register. when complete data is available it w ill be written into the receive fifo.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 673 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.7 i 2 s operating modes the clocking and ws usage of the i 2 s interface is configurable. in addition to master and slave modes, which are independently configurable for the transmitter and the receiver, several different clock sources are possible, including variations that share the clock and/or ws between the transm itter and receiver. this last option allows using i 2 s with fewer pins, typically four. many configurations are possible that are not considered useful, the following tables and figures give details of the configuratio ns that are most likely to be useful.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 674 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.7.1 i 2 s transmit modes table 528: i 2 s transmit modes i2sdao[5] i2stxmode[3:0] description 0 0 0 0 0 typical transmitter master mode. see figure 125 . the i 2 s transmit function operates as a master. the transmit clock source is the fractional rate divider. the ws used is the internally generated tx_ws. tx_mclk is not output on the i2s_tx_mclk pin. 0 0 0 1 0 transmitter master mode sharing the receiver reference clock. see figure 126 . the i 2 s transmit function operates as a master. the transmit clock source is rx_ref. the ws used is the internally generated tx_ws. tx_mclk is not output on the i2s_tx_mclk pin. 0 0 1 0 0 4-wire transmitter master mode sharing the receiver bit clock and ws. see figure 127 . the i 2 s transmit function operates as a master. the transmit clock source is the rx bit clock. the ws used is the internally generated rx_ws. tx_mclk is not output on the i2s_tx_mclk pin. 0 1 0 0 0 transmitter master mode with tc_mclk output. see figure 125 . the i 2 s transmit function operates as a master. the transmit clock source is the fractional rate divider. the ws used is the internally generated tx_ws. tx_mclk is output on the i2s_tx_mclk pin. 1 0 0 0 0 typical transmitter slave mode. see figure 128 . the i 2 s transmit function operates as a slave. the transmit clock source is the tx_clk pin. the ws used is the tx_ws pin. 1 0 0 1 0 transmitter slave mode sharing the receiver reference clock. see figure 129 . the i 2 s transmit function operates as a slave. the transmit clock source is rx_ref. the ws used is the tx_ws pin. 1 0 1 0 0 4-wire transmitter slave mode sharing the receiver bit clock and ws. see figure 130 . the i 2 s transmit function operates as a slave. the transmit clock source is the rx bit clock. the ws used is rx_ws ref.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 675 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 125. typical transmitter master mode, with or wi thout mclk output i2stxmode[3] cclk n (1 to 64) 8-bit fractional rate divider 2 xy i 2 s peripheral block (transmit) i2stxbitrate[5:0] tx_ref tx bit clock i2stx_rate[7:0] i2stx_rate[15:8] (pin oe) tx_ws ref 110407 i2s_tx_mclk i2s_tx_ws i2s_tx_sda i2s_tx_clk fig 126. transmitter master mode sharing the receiver reference clock n (1 to 64) i2stxbitrate[5:0] rx_ref tx bit clock tx_ws ref i 2 s peripheral block (transmit) i2s_tx_ws i2s_tx_sda i2s_tx_clk 110407 fig 127. 4-wire transmitter master mode sharing the receiver bit clock and ws rx bit clock rx_ws ref i 2 s peripheral block (transmit) i2s_tx_sda i2s_tx_clk 110527 fig 128. typical transmitter slave mode n (1 to 64) i 2 s peripheral block (transmit) i2stxbitrate[5:0] tx_ref tx bit clock i2s_tx_ws i2s_tx_sda i2s_tx_clk 110407
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 676 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 129. transmitter slave mode sharing the receiver reference clock n (1 to 64) i 2 s peripheral block (transmit) i2stxbitrate[5:0] rx_ref tx bit clock i2s_tx_ws i2s_tx_sda 110407 fig 130. 4-wire transmitter slave mode sharing the receiver bit clock and ws rx bit clock rx_ws ref i 2 s peripheral block (transmit) i2s_tx_sda 110527
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 677 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.7.2 i 2 s receive modes table 529: i 2 s receive modes i2sdai[5] i2srxmode[3:0] description 0 0 0 0 0 typical receiver master mode. see figure 131 . the i 2 s receive function operates as a master. the receive clock source is the fractional rate divider. the ws used is the internally generated rx_ws. rx_mclk is not output on the i2s_rx_mclk pin. 0 0 0 1 0 receiver master mode sharing the transmitter reference clock. see figure 132 . the i 2 s receive function operates as a master. the receive clock source is tx_ref. the ws used is the internally generated rx_ws. rx_mclk is not output on the i2s_rx_mclk pin. 0 0 1 0 0 4-wire receiver master mode sharing the transmitter bit clock and ws. see figure 133 . the i 2 s receive function operates as a master. the receive clock source is the tx bit clock. the ws used is the internally generated tx_ws. rx_mclk is not output on the i2s_rx_mclk pin. 0 1 0 0 0 receiver master mode with rx_mclk output. see figure 131 . the i 2 s receive function operates as a master. the receive clock source is the fractional rate divider. the ws used is the internally generated rx_ws. rx_mclk is output on the i2s_rx_mclk pin. 1 0 0 0 0 typical receiver slave mode. see figure 134 . the i 2 s receive function operates as a slave. the receive clock source is the rx_clk pin. the ws used is the rx_ws pin. 1 0 0 1 0 receiver slave mode sharing the transmitter reference clock. see figure 135 . the i 2 s receive function operates as a slave. the receive clock source is tx_ref. the ws used is the rx_ws pin. 1 0 1 0 0 this is a 4-wire receiver slave mode sharing the transmitter bit clock and ws. see figure 136 . the i 2 s receive function operates as a slave. the receive clock source is the tx bit clock. the ws used is tx_ws ref.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 678 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 131. typical receiver master mode, with or without mclk output i2srxmode[3] cclk n (1 to 64) 8-bit fractional rate divider 2 xy i 2 s peripheral block (receive) i2srxbitrate[5:0] rx_ref rx bit clock i2srx_rate[7:0] i2srx_rate[15:8] (pin oe) rx_ws ref 110407 i2s_rx_mclk i2s_rx_ws i2s_rx_sda i2s_rx_clk fig 132. receiver master mode sharing the transmitter reference clock n (1 to 64) i2srxbitrate[5:0] tx_ref rx bit clock rx_ws ref i 2 s peripheral block (receive) i2s_rx_ws i2s_rx_sda i2s_rx_clk 110407 fig 133. 4-wire receiver master mode sharing the transmitter bit clock and ws tx bit clock tx_ws ref i 2 s peripheral block (receive) i2s_rx_sda i2s_rx_clk 110527 fig 134. typical receiver slave mode n (1 to 64) i 2 s peripheral block (receive) i2srxbitrate[5:0] rx_ref rx bit clock i2s_rx_ws i2s_rx_sda i2s_rx_clk 110407
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 679 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 135. receiver slave mode sharing the transmitter reference clock n (1 to 64) i 2 s peripheral block (receive) i2srxbitrate[5:0] tx_ref rx bit clock i2s_rx_ws i2s_rx_sda 110407 fig 136. 4-wire receiver slave mode sharing the transmitter bit clock and ws tx bit clock tx_ws ref i 2 s peripheral block (receive) i2s_rx_sda 110531
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 680 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.7.2.1 overall clocking and pin connections figure 137 shows all of the clocking connections and pin connections for the i 2 s block. fig 137. i 2 s clocking and pin connections i2stxmode[1:0] i2srxmode[1:0] i2stxmode[2] i2srxmode[2] i2stxmode[3] i2srxmode[3] i2sdao[5] i2sdai[5] i2sdao[5] i2sdai[5] cclk n (1 to 64) 8-bit fractional rate divider n (1 to 64) 8-bit fractional rate divider 2 2 xy xy i 2 s peripheral block i2stxbitrate[5:0] i2srxbitrate[5:0] tx_ref rx_ref tx bit clock rx bit clock i2stx_rate[7:0] i2srx_rate[7:0] i2stx_rate[15:8] i2srx_rate[15:8] (pin oe) (pin oe) (pin oen) (pin oen) i2stxmode[2] i2sdao[5] (pin oen) i2sdai[5] (pin oen) 120104 i2s_tx_mclk i2s_rx_mclk i2s_tx_ws i2s_rx_ws i2s_tx_sda i2s_tx_clk i2s_rx_clk i2s_rx_sda 0 1 i2srxmode[2] 0 1 rx_ws ref tx_ws ref 0 1 0 1 1 0 0 1 00 10 00 10
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 681 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface 23.8 fifo controller handling of data for transmission and reception is performed via the fifo controller which can generate two dma requests and an interrupt request. the controller consists of a set of comparators which compare fifo levels with depth settings contained in registers. the current status of the level comparators can be seen in the apb status register. how the fifo is used in different modes and with different data widths is shown in figure 138 . system signaling occurs when a level detection is true and enabled. table 530. conditions for fifo level comparison level comparison condition dmareq_tx_1 tx_depth_dma1 >= tx_level dmareq_rx_1 rx_depth_dma1 <= rx_level dmareq_tx_2 tx_depth_dma2 >= tx_level dmareq_rx_2 rx_depth_dma2 <= rx_level irq_tx tx_depth_irq >= tx_level irq_rx rx_depth_irq <= rx_level table 531. dma and interrupt request generation system signaling condition irq (irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable) dmareq[0] (dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 & rx_dma1_enable ) dmareq[1] ( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 & rx_dma2_enable ) table 532. status feedback in the i2sstate register status feedback status irq irq_rx | irq_tx dmareq1 (dmareq_tx_1 | dmareq_rx_1) dmareq2 (dmareq_rx_2 | dmareq_tx_2)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 682 of 942 nxp semiconductors UM10562 chapter 23: lpc408x/407x i 2 s interface fig 138. fifo contents for various i 2 s modes left + 1 7 0 right + 1 7 0 left 7 0 right 7 0 stereo 8-bit data mode n + 3 7 0 n + 2 7 0 n + 1 7 0 n 7 0 mono 8-bit data mode n + 1 15 0 n 15 0 mono 16-bit data mode left 15 0 right 15 0 stereo 16-bit data mode n 31 0 mono 32-bit data mode left 31 0 stereo 32-bit data mode n right 31 0 n + 1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 683 of 942 24.1 basic configuration the timer 0, 1, 2, and 3 peripherals are configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bits pctim0/1/2/3. remark: on reset, timer0/1 are enabled (pctim0/1 = 1), and timer2/3 are disabled (pctim2/3 = 0). 2. peripheral clock: the timers operate from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . 3. pins: select timer pins and pin modes through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: see register t0/1/2/3mcr ( table 540 ) and t0/1/2/3ccr ( ta b l e 5 4 2 ) for match and capture events. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 5. dma: up to two match conditions can be used to generate timed dma requests, see table 692 . 24.2 features remark: the four timer/counters are identical except for the peripheral base address. a minimum of two capture inputs and two match outputs are pinned out for all four timers, with a choice of multiple pins for each. timer 2 brings out all four match outputs. ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? counter or timer operation ? up to two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. UM10562 chapter 24: lpc408x/407x timer0/1/2/3 rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 684 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.3 applications ? interval timer for counting internal events. ? pulse width demodulator via capture inputs. ? free running timer. 24.4 description the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally-supplied clock, and can optionally g enerate interrupts or perform other actions at specified timer values, based on four match registers. it also includes four capture inputs to trap the timer value when an input si gnal transitions, optionally generating an interrupt.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 685 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 fig 139. timer block diagram reset maxval timer control register prescale register prescale counter pclk enable reserved reserved capture register 1 capture register 0 match register 3 match register 2 match register 1 match register 0 capture control register control timer counter csn tci ce = = = = interrupt register external match register match control register mat[3:0] interrupt cap[3:0] stop on match dma clear[1:0] dma request[1:0] reset on match load[3:0]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 686 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.5 pin description table 533 gives a brief summary of each of the timer/counter related pins. 24.5.1 multiple cap and mat pins software can select from mu ltiple pins for the cap or mat functions in the iocon registers, which are described in section 7.4.1 . when more than one pin is selected for a mat output, all such pins are driven identically. when more than one pin is selected for a cap input, the pin with the lowest port number is used. note that match conditions may be used internally without the use of a device pin. table 533. timer/counter pin description pin type description t0_cap1:0 t1_cap1:0 t2_cap1:0 t3_cap1:0 input capture signals- a transition on a capture pi n can be configured to load one of the capture registers with the value in the timer counter and optionally generate an interrupt. capture functionality can be selected from a number of pins. when more than one pin is selected for a capture input on a single timer0/1 channel, the pin with the lowest port number is used timer/counter block can select a capture signal as a clock source instead of the pclk derived clock. for more details see section 24.6.11 . t0_mat1:0 t1_mat1:0 t2_mat3:0 t3_mat1:0 output external match output - when a match register (mr3:0) equals the timer counter (tc) this output can either toggle, go low, go high, or do nothing. the external match register (emr) controls the functionality of this output. match output functionality can be selected on a number of pins in parallel.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 687 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6 register description each timer/counter contains the registers shown in table 534 ("reset value" refers to the data stored in used bits only; it does not include reserved bits content). more detailed descriptions follow. [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 534. register overview: timer0/1/2/3 (register base addresses 0x4000 4000 (timer0), 0x4000 8000 (timer1), 0x4009 0000 (timer2), 0x4009 4000 (timer3)) name access address offset description reset value [1] section ir r/w 0x000 interrupt register. the ir can be written to clear interrupts. the ir can be read to identify which of eight possible interrupt sources are pending. 0 ta b l e 5 3 5 tcr r/w 0x004 timer control register. the tcr is used to control the timer counter functions. the timer counter can be disabled or reset through the tcr. 0 ta b l e 5 3 6 tc r/w 0x008 timer counter. the 32 bit tc is incremented every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 ta b l e 5 3 7 pr r/w 0x00c prescale register. when the prescale counter (pc) is equal to this value, the next clock increments the tc and clears the pc. 0 ta b l e 5 3 8 pc r/w 0x010 prescale counter. the 32 bit pc is a counter which is incremented to the value stored in pr. when the value in pr is reached, the tc is incremented and the pc is cleared. the pc is observable and controllable through the bus interface. 0 ta b l e 5 3 9 mcr r/w 0x014 match control register. the mcr is used to control if an interrupt is generated and if the tc is reset when a match occurs. 0 ta b l e 5 4 0 mr0 r/w 0x018 match register 0. mr0 can be enabled through the mcr to reset the tc, stop both the tc and pc, and/or generate an interrupt every time mr0 matches the tc. 0 ta b l e 5 4 1 mr1 r/w 0x01c match register 1. see mr0 description. 0 ta b l e 5 4 1 mr2 r/w 0x020 match register 2. see mr0 description. 0 ta b l e 5 4 1 mr3 r/w 0x024 match register 3. see mr0 description. 0 ta b l e 5 4 1 ccr r/w 0x028 capture control register. the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated when a capture takes place. 0 ta b l e 5 4 2 cr0 ro 0x02c capture register 0. cr0 is loaded with the value of tc when there is an event on the capn.0 input. 0 ta b l e 5 4 3 cr1 ro 0x030 capture register 1. see cr0 description. 0 ta b l e 5 4 3 emr r/w 0x03c external match register. the emr controls the external match pins. 0 ta b l e 5 4 4 ctcr r/w 0x070 count control register. the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 ta b l e 5 4 6
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 688 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.1 interrupt register the interrupt register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. if an interrupt is generated then th e corresponding bit in the ir will be high. otherwise, the bit will be low. writing a logic one to the corr esponding ir bit will reset the interrupt. writing a zero has no effect. the act of clearing an interrupt for a timer match also clears any corresponding dma request. 24.6.2 timer control register the timer control register (tcr) is used to control the operation of the timer/counter. table 535. interrupt register (ir - addresses 0x4000 4000 (timer0), 0x4000 8000 (timer1), 0x4009 0000 (timer2), 0x4009 4000 (timer3)) bit description bit symbol description reset value 0 mr0int interrupt flag for match channel 0. 0 1 mr1int interrupt flag for match channel 1. 0 2 mr2int interrupt flag for match channel 2. 0 3 mr3int interrupt flag for match channel 3. 0 4 cr0int interrupt flag for capture channel 0 event. 0 5 cr1int interrupt flag for capture channel 1 event. 0 31:6 - reserved. read value is undefined, only zero should be written. - table 536. timer control register (tcr - addresses 0x4000 4004 (timer0), 0x4000 8004 (timer1), 0x4009 0004 (timer2), 0x4009 4004 (timer3)) bit description bit symbol description reset value 0 cen when one, the timer counter and prescale counter are enabled for counting. when zero, the counters are disabled. 0 1 crst when one, the timer counter and the prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until tcr[1] is returned to zero. 0 31:2 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 689 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.3 timer counter registers the 32-bit timer counter register is incremented when the prescale counter reaches its terminal count. unless it is reset before reaching its upper limit, t he timer counter will count up through the value 0xffff ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. 24.6.4 prescale register the 32-bit prescale register specifies the maximum value for the prescale counter. 24.6.5 prescale counter register the 32-bit prescale counter controls division of pclk by some constant value before it is applied to the timer counter. this allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. the prescale counter is incremented on every pclk. when it reaches the value stored in the prescale register, the timer counter is incremented and the pres cale counter is reset on the next pclk. this causes the timer counter to increment on every pclk when pr = 0, every 2 pclks when pr = 1, etc. 24.6.6 match control register the match control register is used to control what operations are performed when one of the match registers matches the timer counter. the function of each of the bits is shown in table 540 . table 537. timer counter registers (tc - addresses 0x400 4008 (timer0), 0x4000 8008 (timer1), 0x4009 0008 (timer2), 0x4009 4008 (timer3)) bit description bit symbol description reset value 31:0 tc timer counter value. 0 table 538. timer prescale registers (pr - addresses 0x4000 400c (timer0), 0x4000 800c (timer1), 0x4009 000c (timer2), 0x4009 400c (timer3)) bit description bit symbol description reset value 31:0 pm prescale counter maximum value. 0 table 539. timer prescale counter registers (pc - addresses 0x4000 4010 (timer0), 0x4000 8010 (timer1), 0x4009 0010 (timer2), 0x4009 4010 (timer3)) bit description bit symbol description reset value 31:0 pc prescale counter value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 690 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 table 540. match control register (mcr - addresses 0x4000 4014 (timer0), 0x4000 8014 (timer1), 0x4009 0014 (timer2), 0x4009 4014 (timer3)) bit description bit symbol value description reset value 0 mr0i interrupt on mr0 0 1 interrupt is generated when mr0 matches the value in the tc. 0 interrupt is disabled 1 mr0r reset on mr0 0 1 tc will be reset if mr0 matches it. 0 feature disabled. 2 mr0s 1 stop on mr0 0 1 tc and pc will be stopped and tcr[0] will be set to 0 if mr0 matches the tc. 0 feature disabled. 3 mr1i interrupt on mr1 0 1 interrupt is generated when mr1 matches the value in the tc. 0 interrupt is disabled. 4 mr1r reset on mr1 0 1 tc will be reset if mr1 matches it. 0 feature disabled. 5 mr1s stop on mr1 0 1 tc and pc will be stopped and tcr[0] will be set to 0 if mr1 matches the tc. 0 feature disabled. 6 mr2i interrupt on mr2 0 1 interrupt is generated when mr2 matches the value in the tc. 0 interrupt is disabled 7 mr2r reset on mr2 0 1 tc will be reset if mr2 matches it. 0 feature disabled. 8 mr2s stop on mr2. 0 1 tc and pc will be stopped and tcr[0] will be set to 0 if mr2 matches the tc 0 feature disabled. 9 mr3i interrupt on mr3 0 1 interrupt is generated when mr3 matches the value in the tc. 0 this interrupt is disabled 10 mr3r reset on mr3 0 1 tc will be reset if mr3 matches it. 0 feature disabled. 11 mr3s stop on mr3 0 1 tc and pc will be stopped and tcr[0] will be set to 0 if mr3 matches the tc. 0 feature disabled. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 691 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.7 match registers (mr0 to mr3) the match register values are continuously compared to the timer counter value. when the two values are equal, acti ons can be triggere d automatically. the action possibilities are to generate an interrupt, reset the timer counter, or stop the timer. actions are controlled by the settings in the mcr register. 24.6.8 capture control register the capture control register is used to cont rol whether one of the four capture registers is loaded with the value in the timer counter when the capture event occurs, and whether an interrupt is g enerated by the capture even t. setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the description below, "n" represents the timer number, 0 or 1. note: if counter mode is selected for a particular cap input in the ctcr, the 3 bits for that input in this register should be program med as 000, but captur e and/or interrupt can be selected for the other 3 cap inputs. table 541. timer match registers (mr[0:3], addresses 0x4000 4018 (mr0) to 0x4000 4024 (mr3) (timer0), 0x4000 8018 (mr0) to 0x4000 8024 (mr3) (timer1), 0x4009 0018 (mr0) to 0x4009 0024 (mr3) (timer2), 0x4009 4018 (mr0) to 0x4009 4024 (mr3)(timer3)) bit description bit symbol description reset value 31:0 match timer counter match value. 0 table 542. capture control register (ccr - addresses 0x4000 4028 (timer0), 0x4000 8020 (timer1), 0x4009 0028 (timer2), 0x4009 4028 (timer3)) bit description bit symbol value description reset value 0 cap0re capture on capn.0 rising edge 0 1 a sequence of 0 then 1 on capn.0 will cause cr0 to be loaded with the contents of tc. 0 this feature is disabled. 1 cap0fe capture on capn.0 falling edge 0 1 a sequence of 1 then 0 on capn.0 will cause cr0 to be loaded with the contents of tc. 0 this feature is disabled. 2 cap0i interrupt on capn.0 event 0 1 a cr0 load due to a capn.0 event will generate an interrupt. 0 this feature is disabled. 3 cap1re capture on capn.1 rising edge 0 1 a sequence of 0 then 1 on capn.1 will cause cr1 to be loaded with the contents of tc. 0 this feature is disabled. 4 cap1fe capture on capn.1 falling edge 0 1 a sequence of 1 then 0 on capn.1 will cause cr1 to be loaded with the contents of tc. 0 this feature is disabled.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 692 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.9 capture registers each capture register is associated with a device pin and may be loaded with the timer counter value when a specified event occurs on that pin. the settings in the capture control register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 5 cap1i interrupt on capn.1 event 0 1 a cr1 load due to a capn.1 event will generate an interrupt. 0 this feature is disabled. 31:6 - reserved. read value is undefined, only zero should be written. na table 542. capture control register (ccr - addresses 0x4000 4028 (timer0), 0x4000 8020 (timer1), 0x4009 0028 (timer2), 0x4009 4028 (timer3)) bit description bit symbol value description reset value table 543. timer capture registers (cr[0:1], address 0x4000 402c (cr0) to 0x4000 4030 (cr1) (timer0), 0x4000 802c (cr0) to 0x4000 0030 (cr1) (timer1), 0x4009 002c (cr0) to 0x4009 0030 (cr1) (timer2), 0x4009 402c (cr0) to 0x4000 4030 (cr1) (timer3)) bit description bit symbol description reset value 31:0 cap timer counter capture value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 693 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.10 external match register the external match register provides both control and status of the external match pins. in the descriptions below, ?n? represents th e timer number, 0 or 1, and ?m? represent a match number, 0 through 3. match events for match 0 and match 1 in each timer can cause a dma request, see section 24.6.12 . table 544. timer external match registers (emr - addresses 0x4000 403c (timer0), 0x4000 803c (timer1), 0x4009 403c (timer2), 0x400c 403c (timer3)) bit description bit symbol value description reset value 0 em0 external match 0. when a match occurs between the tc and mr0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. this bit can be driven onto a matn.0 pin, in a positive-logic manner (0 = low, 1 = high). 0 1 em1 external match 1. when a match occurs between the tc and mr1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. this bit can be driven onto a matn.1 pin, in a positive-logic manner (0 = low, 1 = high). 0 2 em2 external match 2. when a match occurs between the tc and mr2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. this bit can be driven onto a matn.0 pin, in a positive-logic manner (0 = low, 1 = high). 0 3 em3 external match 3. when a match occurs between the tc and mr3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. this bit can be driven onto a matn.0 pin, in a positive-logic manner (0 = low, 1 = high). 0 5:4 emc0 external match control 0. determines the functionality of external match 0. 00 0x0 do nothing. 0x1 clear the corresponding external match bit/output to 0 (matn.m pin is low if pinned out). 0x2 set the corresponding external match bit/output to 1 (matn.m pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 7:6 emc1 external match control 1. determines the functionality of external match 1. 00 0x0 do nothing. 0x1 clear the corresponding external match bit/output to 0 (matn.m pin is low if pinned out). 0x2 set the corresponding external match bit/output to 1 (matn.m pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 9:8 emc2 external match control 2. determines the functionality of external match 2. 00 0x0 do nothing. 0x1 clear the corresponding external match bit/output to 0 (matn.m pin is low if pinned out). 0x2 set the corresponding external match bit/output to 1 (matn.m pin is high if pinned out). 0x3 toggle the corresponding external match bit/output.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 694 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 11:10 emc3 external match control 3. determines the functionality of external match 3. 00 0x0 do nothing. 0x1 clear the corresponding external match bit/output to 0 (matn.m pin is low if pinned out). 0x2 set the corresponding external match bit/output to 1 (matn.m pin is high if pinned out). 0x3 toggle the corresponding external match bit/output. 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. na table 544. timer external match registers (emr - addresses 0x4000 403c (timer0), 0x4000 803c (timer1), 0x4009 403c (timer2), 0x400c 403c (timer3)) bit description bit symbol value description reset value table 545. external match control emr[11:10], emr[9:8], emr[7:6], or emr[5:4] function 00 do nothing. 01 clear the corresponding external match bit/output to 0 (matn.m pin is low if pinned out). 10 set the corresponding external match bit/output to 1 (matn.m pin is high if pinned out). 11 toggle the corresponding external match bit/output.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 695 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.11 count control register the count control register (c tcr) is used to select be tween timer and counter mode, and in counter mode to select the pin and edge(s) for counting. when counter mode is chosen as a mode of operation, the cap input (selected by the ctcr bits 3:2) is sampled on every rising edge of the pclk clock. after comparing two consecutive samples of this cap input, one of the following four events is recognized: rising edge, falling edge, either of edges or no cha nges in the level of the selected cap input. only if the identified event occurs and the event corresponds to the one selected by bits 1:0 in the ctcr register, will the timer counter regist er be incremented. note that two successive samples of the pin are used to identify an edge on the cap selected input. therefore, the duration of the high and low levels on the same cap input must be greater than 1 pclk, and the frequency of the cap input must be less than one quarter of the pclk rate. table 546. count control register (ctcr - addresses 0x4000 4070 (timer0), 0x4000 8070 (timer1), 0x4009 0070 (timer2), 0x4009 4070 (timer3)) bit description bit symbol value description reset value 1:0 ctmode counter/timer mode this field selects which rising pclk edges can increment timer?s prescale counter (pc), or clear pc and increment timer counter (tc). timer mode: the tc is incremented when the prescale counter matches the prescale register. 00 0x0 timer mode: every rising pclk edge 0x1 counter mode: tc is incremented on rising edges on the cap input selected by bits 3:2. 0x2 counter mode: tc is incremented on falling edges on the cap input selected by bits 3:2. 0x3 counter mode: tc is incremented on both edges on the cap input selected by bits 3:2. 3:2 cinsel count input select when bits 1:0 in this register are not 00, these bits select which cap pin is sampled for clocking. note: if counter mode is selected for a particular capn input in the tnctcr, the 3 bits for that input in the capture control regi ster (tnccr) must be programmed as 000. however, capture and/or interrupt can be selected for the other 3 capn inputs in the same timer. 0 0x0 capn.0 for timern 0x1 capn.1 for timern 0x2 reserved 0x3 reserved 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 696 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.6.12 dma operation dma requests are generated by a match of the timer counter (tc) register value to either match register 0 (mr0) or match register 1 (m r1). this is not connected to the operation of the match outputs controlled by the emr re gister. each match sets a dma request flag, which is connected to the dma controller. in order to have an effect, the gpdma must be configured and the relevant timer dma request selected as a dma source via the dmareqsel register, see section 3.3.7.6 . when a timer is initially set up to generate a dma request, the request may already be asserted before a match condition occurs. an initial dma request may be avoided by having software write a one to the interrupt fl ag location, as if clearing a timer interrupt. see section 24.6.1 . a dma request will be cl eared automatically when it is acted upon by the gpdma controller. note: because timer dma requests are generat ed whenever the timer value is equal to the related match register value, dma reques ts are always generated when the timer is running, unless the match register value is higher than the upper count limit of the timer. it is important not to select and enable timer dma requests in the gpdma block unless the timer is correctly configured to generate valid dma requests.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 697 of 942 nxp semiconductors UM10562 chapter 24: lpc408x/407x timer0/1/2/3 24.7 example timer operation figure 140 shows a timer configured to reset the count and generate an interrupt on match. the prescaler is set to 2 and the match register set to 6. at the end of the timer cycle where the match occurs, the timer count is reset. this gives a full length cycle to the match value. the interrupt indicating that a ma tch occurred is generat ed in the next clock after the timer reached the match value. figure 141 shows a timer configured to stop and generate an interrupt on match. the prescaler is again set to 2 and the match register set to 6. in the next clock after the timer reaches the match value, the timer enable bit in tcr is cleare d, and the interrupt indicating that a match occurred is generated. fig 140. a timer cycle in which pr=2, mrx=6, and both interrupt and reset on match are enabled. pclk prescale counter interrupt timer counter timer counter reset 2 2 2 2000 0 1111 45 6 0 1 fig 141. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled pclk prescale counter interrupt timer counter tcr[0] (counter enable) 2 20 0 1 45 6 1 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 698 of 942 25.1 basic configuration the system tick timer is configured using the following registers: 1. clock source: select either the internal cclk or external stclk (pin p3[26]) clock as the source in the stctrl register. 2. pins: if stclk (pin p3[26]) was selected as clock source enable the stclk pin function in the relevant iocon register ( section 7.4.1 ). 3. interrupt: the system tick timer inte rrupt is enabled in the nvic using the appropriate interrupt set enable register. t he systick interrupt is hard-wired within the cortex-m4 as exception 15. see the arm cortex-m4 user guide referred to in section 40.1 for details of the system tick timer. 25.2 features ? times intervals of 10 milliseconds ? dedicated exception vector ? can be clocked internally by the cpu cloc k or by a clock input from a pin (stclk) 3. description the system tick timer is an integral part of the cortex-m4. the system tick timer is intended to generat e a fixed 10 millisecond in terrupt for use by an operating s ystem or other system management software. since the system tick timer is a part of the co rtex-m4, it facilitates porting of software by providing a standard timer that is av ailable on cortex-m4 based devices. see the arm cortex-m4 user guide referred to in section 40.1 for details of system tick timer operation. 25.4 operation the system tick timer is a 24-bit timer t hat counts down to zero and generates an interrupt. the intent is to provide a fixed 10 millisecond time interval be tween interrupts. the system tick timer may be clocked either from the cpu clock or from the external pin stclk. the stclk function shares pin p3[26] with other functions, and must be selected for use as the system tick timer clock. in order to generate recurring interrupts at a specific interval, the streload register must be initialized with th e correct value for the desired interval. a default value is provided in the stcalib register and may be changed by software. the default value gives a 10 millisecond interrupt rate if the cpu clock is set to 100 mhz. the block diagram of the system tick timer is shown below in the figure 142 . UM10562 chapter 25: lpc408x/407x system tick timer rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 699 of 942 nxp semiconductors UM10562 chapter 25: lpc408x/407x system tick timer fig 142. system tick timer block diagram cclk stcalib streload stcurr 24-bit down counter enable stctrl private peripheral bus system tick interrupt stclk pin clksource tickint countflag load under- flow count enable clock dq load data 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 700 of 942 nxp semiconductors UM10562 chapter 25: lpc408x/407x system tick timer 25.5 register description [1] reset value reflects the data stored in used bits only. it does not include content of reserved bits. 25.5.1 system timer cont rol and status register the stctrl register contains control informat ion for the system tick timer, and provides a status flag. 25.5.2 system timer reload value register the streload register is set to the value that will be loade d into the system tick timer whenever it counts down to zero. this regist er is loaded by software as part of timer initialization. the stcalib register may be read and used as the value for streload if the cpu or external clock is running at the frequency intended for use with the stcalib value. table 547. system tick timer register map name description access reset value [1] address table stctrl system timer control and status register r/w 0x4 0xe000 e010 548 streload system timer reload value register r/w 0 0xe000 e014 549 stcurr system timer current va lue register r/w 0 0xe000 e018 550 stcalib system timer calibration value register r/w 0x000f 423f 0xe000 e01c 551 table 548. system timer control and status register (stctrl - 0xe000 e010) bit description bit symbol description reset value 0 enable system tick counter enable. when 1, the counter is enabled. when 0, the counter is disabled. 0 1 tickint system tick interrupt enable. when 1, the system tick interrupt is enabled. when 0, the system tick interrupt is disabled. when enabled, the interrupt is generated when the system tick counter counts down to 0. 0 2 clksource system tick clock source selection. when 1, the cpu clock is selected. when 0, the external clock pin (stclk) is selected. if the stclk pin is selected, each level on the pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. 1 15:3 - reserved. read value is undefined, only zero should be written. na 16 countflag system tick counter flag. this flag is set when the system tick counter counts down to 0, and is cleared by reading this register. 0 31:17 - reserved. read value is undefined, only zero should be written. na table 549. system timer reload value register (streload - 0xe000 e014) bit description bit symbol description reset value 23:0 reload this is the value that is loaded into the system tick counter when it counts down to 0. 0 31:24 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 701 of 942 nxp semiconductors UM10562 chapter 25: lpc408x/407x system tick timer 25.5.3 system timer current value register the stcurr register returns the current count from the system tick counter when it is read by software. 25.5.4 system timer calibration value register the stcalib register contains a value that is initialized by the boot code to a factory programmed value that is appr opriate for generating an inte rrupt every 10 milliseconds if the system tick timer is clocked at a frequency of 100 mhz. this is the intended use of the system tick timer by arm. it can be used to generate interrupts at other frequencies by selecting the correct reload value. table 550. system timer current value register (stcurr - 0xe000 e018) bit description bit symbol description reset value 23:0 current reading this register returns the current value of the system tick counter. writing any value clears the system tick counter and the countflag bit in stctrl. 0 31:24 - reserved. read value is undefined, only zero should be written. na table 551. system timer calibration value register (stcalib - 0xe000 e01c) bit description bit symbol description reset value 23:0 tenms reload value to get a 10 millisecond system tick underflow rate when running at 100 mhz. this value initialized at reset with a factory supplied value selected for the lpc408x/407x. the provided values of te nms, skew, and noref are applicable only when using a cpu clock or external stclk source of 100 mhz. 0x0f 423f 29:24 - reserved. read value is undefined, only zero should be written. na 30 skew indicates whether the tenms value will generate a pr ecise 10 millisecond time, or an approximation. this bit is initialized at reset with a factory supplied value selected for the lpc408x/407x. see the description of tenms above. when 0, the value of tenms is considered to be precise. when 1, the value of tenms is not considered to be precise. 0 31 noref indicates whether an external reference clock is available. this bit is initialized at reset with a factory supplied value selected for the lpc408x/407x. see the description of tenms above. when 0, a separate reference clock is available. when 1, a separate reference clock is not available. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 702 of 942 nxp semiconductors UM10562 chapter 25: lpc408x/407x system tick timer 25.6 example timer calculations the following examples illustrate selecting system tick timer values for different system configurations. all of the exam ples calculate an interrupt inte rval of 10 milliseconds, as the system tick timer is intended to be used. example 1) this example is for the system tick timer running from the cpu clock (cclk), which is 100 mhz. stctrl = 7. this enables the timer and its interrupt, and selects cclk as the clock source. reload = (cclk / 100) - 1 = 1,000,000 - 1 = 999,999 = 0xf423f in this case, there is no rounding error, so the result is as accurate as cclk. example 2) this example is for the system tick timer running from the cpu clock (cclk), which is 80 mhz. stctrl = 7. this enables the timer and its interrupt, and selects cclk as the clock source. reload = (cclk / 100) - 1 = 800,000 - 1 = 799,999 = 0xc34ff in this case, there is no rounding error, so the result is as accurate as cclk. example 3) this example is for the cpu clock (cclk) is taken from the internal rc oscillator (irc), factory trimmed to 4 mhz. stctrl = 7. this enables the timer and its interrupt, and selects cclk as the clock source. reload = (f irc / 100) - 1 = 40,000 - 1 = 39,999 = 0x9c3f in this case, there is no rounding error, so the result is as accurate as the irc. example 4) this example is for the system tick timer running from an external clock source (the stclk pin), which in this case happens to be 32.768 khz. stctrl = 3. this enables the timer and its interrupt, and selects the stclk pin as the clock source. stclk must be selected as the function of the relevant pin. see section 7.4.1 . reload = (cclk / 100) - 1 = 327. 6 - 1 = 327 (rounded up) = 0x0147 in this case, there is rounding error, so the interrupt rate will drift slightly relative to the input frequency.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 703 of 942 26.1 basic configuration the pwm is configured usin g the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcpwm1. remark: on reset, pwm1 is enabled (pcp wm1 = 1) and pwm0 is disabled (pcpwm1 = 0). 2. peripheral clock: the pwms operate from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . 3. pins: select pwm pins and pin modes for port pins with pwm functions through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: see registers pwmmcr ( table 560 ) and pwmccr ( table 563 ) for match and capture events. interrupts are enabled in the nvic using the appropriate interrupt set enable register. UM10562 chapter 26: lpc408x/407x pu lse width modula tors (pwm0/1) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 704 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.2 features ? the two pwms have the same operational features. the pwms may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. pwm0 acts as the ma ster and pwm1 as the slave for this use. ? counter or timer operation (may use the peripheral clock or one of the capture inputs as the clock source). ? seven match registers allow up to 6 single edge controlled or 3 double edge controlled pwm outputs, or a mix of bot h types. the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge controlled pwm outputs can have either edge occur at any position within a cycle. this allows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and repe tition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wi th pulse outputs to prevent generation of erroneous pulses. software must "release" new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32 bit timer/counter with a programmable 32 bit prescaler. ? a transition on a capture input signal can trigger a snapshot of the 32-bit timer value. a capture event may also opti onally generate an interrupt.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 705 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.3 description the pwm function is based on the standard timer block and inherits all of its features, although many timer functions are not brought out to package pins. the timer is designed to count cycles of the peripheral clock (pclk) or a capture input and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. it also includes capture in puts to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. the pwm function is in addition to these featur es, and is based on match register events. the ability to separa tely control rising and falling edge locations allows the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with indivi dual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycl e rate, by resetting t he count upon match. the other match register controls the pw m edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge controlled pwm ou tputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs. three match registers can be used to provide a pwm output with both edges controlled. again, the mr0 match register controls the pwm cycle rate. the other match registers control the two pwm edge positions. additional double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allo ws both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative going pwm pulses (when the falling edge occurs prior to the rising edge). figure 143 shows the block diagram of the pwm. the portions that have been added to the standard timer block are on the right hand si de and at the top of the diagram. at the lower left of the diagram may be found the ma ster enable output from the timer control register that allows the master pwm (pwm0) to enable both itself and the slave pwm (pwm1) at the same time, if desired. the ma ster enable output from pwm0 is connected to the external enable in put of both pwm blocks.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 706 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) fig 143. pwm block diagram load enable register clear match 0 control m[6:0] interrupt stop on match reset on match capture[1:0] capture control register load[1:0] = = = = = = = pwmsel2..6 mux mux mux mux mux pwmsel2 pwmsel3 pwmsel4 pwmsel5 pwmsel6 match 0 match 1 match 3 match 4 match 5 match 6 match 2 timer control register prescale register pwm control register prescale counter timer counter pwmena1..6 maxval tci ce csn enable reset master disable match control register interrupt register pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 match register 3 match register 2 match register 0 match register 4 match register 5 match register 6 match register 1 capture register 0 capture register 1 reserved reserved pwmena6 pwmena5 pwmena4 pwmena3 pwmena2 pwmena1 shadow register 6 load enable shadow register 5 load enable shadow register 3 load enable shadow register 2 load enable shadow register 0 load enable shadow register 4 load enable shadow register 1 load enable r s q en r s q en r s q en r s q en r s q en r s q en
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 707 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.4 sample waveform with rules fo r single and double edge control a sample of how pwm values relate to waveform outputs is shown in figure 144 . pwm output logic is shown in figure 143 that allows selection of either single or double edge controlled pwm outputs via the muxes controlled by the pwmseln bits. the match register selections for various pwm outputs is shown in table 552 . this implementation supports up to n-1 single edge pwm outputs or (n-1)/2 double edge pwm outputs, where n is the number of match registers and ou tputs that are implemented. pwm types can be mixed if desired. [1] identical to single edge mode in this case since match 0 is the neighbor ing match register. essentially, pwm1 cannot be a double edged output. [2] it is generally not advantageous to use pwm channels 3 and 5 for double edge pwm outputs because it would reduce the number of double edge pwm outputs that are possible. using pwm[2], pwm[4], and pwm[6] for double edge pwm outputs provides the most pairings. the waveforms below show a single pwm cycle and demonstrate pwm outputs under the following conditions: the timer is configured for pwm mode (counter resets to 1). match 0 is configured to reset the ti mer/counter when a match event occurs. control bits pwmsel2 and pwmsel4 are set. the match register values are as follows: mr0 = 100 (pwm rate) mr1 = 41, mr2 = 78 (pwm[2] output) mr3 = 53, mr4 = 27 (pwm[4] output) mr5 = 65 (pwm[5] output) fig 144. sample pwm waveforms table 552. set and reset inputs for pwm flip-flops pwm channel single edge pw m (pwmseln = 0) double edge pwm (pwmseln = 1) set by reset by set by reset by 1 match 0 match 1 match 0 [1] match 1 [1] 2 match 0 match 2 match 1 match 2 3 match 0 match 3 match 2 [2] match 3 [2] 4 match 0 match 4 match 3 match 4 5 match 0 match 5 match 4 [2] match 5 [2] 6 match 0 match 6 match 5 match 6 pwm2 pwm4 pwm5 100 (counter is reset) 1 2741536578
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 708 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.4.1 rules for single edge controlled pwm outputs 1. all single edge controlled pwm outputs go high at the beginning of a pwm cycle unless their match value is equal to 0. 2. each pwm output will go low when its match value is reach ed. if no match occurs (i.e. the match value is greater than the pwm rate ), the pwm output remains continuously high. 26.4.2 rules for double edge controlled pwm outputs five rules are used to determine the next value of a pwm output when a new cycle is about to begin: 1. the match values for the next pwm cycle are used at the end of a pwm cycle (a time point which is coincident with the beginning of the next pwm cycle), except as noted in rule 3. 2. a match value equal to 0 or the current pwm rate (the same as the match channel 0 value) have the same effect, except as noted in rule 3. for example, a request for a falling edge at the beginning of the pwm cycle has the same effect as a request for a falling edge at the en d of a pwm cycle. 3. when match values are changing, if one of the "old" match values is equal to the pwm rate, it is used again onc e if the neither of the new match values are equal to 0 or the pwm rate, and there was no old match value equal to 0. 4. if both a set and a clear of a pwm output are requested at the same time, clear takes precedence. this can occur when the set an d clear match values are the same as in, or when the set or clear value equals 0 and the other value equals the pwm rate. 5. if a match value is out of range (i.e. greater than the pwm rate value), no match event occurs and that match channel has no effect on the output. this means that the pwm output will remain always in one state, allowing always low, always high, or "no change" outputs. 26.5 pin description table 553 gives a brief summary of each of pwm related pins. table 553. pin summary pin type description pwm0[6:1] output outputs from pwm0 channels 6 to 1. pwm0_cap0 input capture input for pwm0. a transition on the capture pin can be configured to load the corresponding capture register with the value of the timer counter and optionally generate an interrupt. each level on this pin must be at least 1 pclk in duration in order to be sampled. the maximum frequency must therefore be less than pclk/2. pwm1[6:1] output outputs from pwm1 channels 6 to 1. pwm1_cap1:0 input capture inputs for pwm1. a transition on the capture pin can be configured to load the corresponding capture register with the value of the timer counter and optionally generate an interrupt.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 709 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6 register description [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. 26.6.1 pwm interrupt register the pwm interrupt register consists of eleven bits ( table 555 ), seven for the match interrupts and four reserved. if an interrupt is generated then the corresponding bit in the pwmir will be high. othe rwise, the bit will be low. writin g a logic one to the corresponding ir bit will reset the interrupt. writing a zero has no effect. table 554. register overview: pwm (base addresses 0x4001 4000 (pwm0) and 0x4001 8000 (pwm1)) name access address offset description reset value [1] section ir r/w 0x000 interrupt register. the ir can be written to clear interrupts, or read to identify which pwm interrupt sources are pending. 0 26.6.1 tcr r/w 0x004 timer control register. the tcr is used to control the timer counter functions. 0 26.6.2 tc r/w 0x008 timer counter. t he 32 bit tc is increment ed every pr+1 cycles of pclk. the tc is controlled through the tcr. 0 26.6.3 pr r/w 0x00c prescale register. determines how often the pwm counter is incremented. 0 26.6.4 pc r/w 0x010 prescale counter. pre scaler for the main pwm counter. 0 26.6.5 mcr r/w 0x014 match control register. the mcr is used to control whether an interrupt is generated and if the pwm counter is reset when a match occurs. 0 26.6.6 mr0 r/w 0x018 match register 0. match registers are continuously compared to the pwm counter in order to control pwm output edges. 0 26.6.7 mr1 r/w 0x01c match register 1. see mr0 description. 0 26.6.7 mr2 r/w 0x020 match register 2. see mr0 description. 0 26.6.7 mr3 r/w 0x024 match register 3. see mr0 description. 0 26.6.7 ccr r/w 0x028 capture control register. the ccr controls which edges of the capture inputs are used to load the capture registers and whether or not an interrupt is generated for a capture event. 0 26.6.8 cr0 ro 0x02c capture register 0. cr0 of pwmn is loaded with the value of the tc when there is an event on the pwmn_cap0 input. 0 26.6.9 cr1 ro 0x030 capture register 1. see cr0 description. 0 26.6.9 mr4 r/w 0x040 match register 4. see mr0 description. 0 26.6.7 mr5 r/w 0x044 match register 5. see mr0 description. 0 26.6.7 mr6 r/w 0x048 match register 6. see mr0 description. 0 26.6.7 pcr r/w 0x04c pwm control register. enables pwm outputs and selects either single edge or double edge controlled pwm outputs. 0 26.6.10 ler r/w 0x050 load enable register. enables use of updated pwm match values. 0 26.6.11 ctcr r/w 0x070 count control register. the ctcr selects between timer and counter mode, and in counter mode selects the signal and edge(s) for counting. 0 26.6.12
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 710 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) table 555: pwm interrupt register (ir - address 0x4001 4000 (pwm0) and 0x4001 8000 (pwm1)) bit description bit symbol description reset value 0 pwmmr0int interrupt flag for pwm match channel 0. 0 1 pwmmr1int interrupt flag for pwm match channel 1. 0 2 pwmmr2int interrupt flag for pwm match channel 2. 0 3 pwmmr3int interrupt flag for pwm match channel 3. 0 4 pwmcap0 int interrupt flag for capture input 0 0 5 pwmcap1int interrupt flag for capture input 1 (available in pwm1ir only; this bit is reserved in pwm0ir). 0 7:6 - reserved. read value is undefined, only zero should be written. - 8 pwmmr4int interrupt flag for pwm match channel 4. 0 9 pwmmr5int interrupt flag for pwm match channel 5. 0 10 pwmmr6int interrupt flag for pwm match channel 6. 0 31:11 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 711 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.2 pwm timer control register the pwm timer control register (pwmtcr) is used to control the operation of the pwm timer counter. the function of each of the bits is shown in table 556 . 26.6.3 pwm timer counter the 32-bit pwm timer counter is increment ed when the prescale counter reaches its terminal count. unless it is reset before reaching its upper limit, the pwmtc will count up through the value 0xffff ffff and then wrap back to the value 0x0000 0000. this event does not cause an interrupt, but a match register can be used to detect an overflow if needed. table 556: pwm timer control register (tcr - address 0x4001 4004 (pwm0) and 0x4001 8004 (pwm1)) bit description bit symbol value description reset value 0 ce counter enable 0 1 the pwm timer counter and pwm prescale counter are enabled for counting. 0 the counters are disabled. 1 cr counter reset 0 1 the pwm timer counter and the pwm prescale counter are synchronously reset on the next positive edge of pclk. the counters remain reset until this bit is returned to zero. 0 clear reset. 2 - reserved. read value is undefined, only zero should be written. na 3 pwmen pwm enable 0 1 pwm mode is enabled (counter resets to 1). pwm mode causes the shadow registers to operate in connection with the match registers. a program write to a match register will not have an effect on the match result until the corresponding bit in pwmler has been set, followed by the occurrence of a pwm match 0 event. note that the pwm match register that determines the pwm rate (pwm match register 0 - mr0) must be set up prior to the pwm being enabled. otherwise a match event will not occur to cause shadow register contents to become effective. 0 timer mode is enabled (counter resets to 0). 4 mdis master disable (pwm0 only). the two pwms may be synchronized using the master disable control bit. the master disable bit of the master pwm (pwm0 module) controls a secondary enable input to both pwms, as shown in figure 143 . this bit has no function in the slave pwm (pwm1). 0 1 master use. pwm0 is the master, and both pwms are enabled for counting. 0 individual use. the pwms are used independently, and the individual counter enable bits are used to control the pwms. 31:5 - reserved. read value is undefined, only zero should be written. na table 557. pwm timer counter registers (tc - addresses 0x4001 4008 (pwm0), 0x4001 8008 (pwm1)) bit description bit symbol description reset value 31:0 tc timer counter value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 712 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.4 pwm prescale register the 32-bit pwm prescale register specifie s the maximum value fo r the pwm prescale counter. 26.6.5 pwm prescale counter register the 32-bit pwm prescale counter controls division of pclk by some constant value before it is applied to the pwm timer counter. this allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. the pwm prescale counter is incremented on every pclk . when it reaches the value stored in the pwm prescale register, the pwm timer counter is incremented and the pwm prescale counter is reset on the next pclk. this causes the pwm tc to increment on every pclk when pwmpr = 0, every 2 pclks when pwmpr = 1, etc. 26.6.6 pwm match control register the pwm match control registers are used to control what operations are performed when one of the pwm match registers matche s the pwm timer counter. the function of each of the bits is shown in table 560 . table 558. pwm prescale registers (pr - addresses 0x4001 400c (pwm0), 0x4001 800c (pwm1)) bit description bit symbol description reset value 31:0 pm prescale counter maximum value. 0 table 559. pwm prescale counter registers (pc - addresses 0x4001 4010 (pwm0), 0x4001 8010 (pwm1)) bit description bit symbol description reset value 31:0 pc prescale counter value. 0 table 560. match control register (mcr - address 0x4001 4014 (pwm0) and 0x4001 8014 (pwm1)) bit description bit symbol value description reset value 0 pwmmr0i interrupt pwm0 0 0 disabled. 1 interrupt on pwmmr0: an interrupt is generated when pwmmr0 matches the value in the pwmtc. 1pwmmr0r reset pwm0 0 0 disabled. 1 reset on pwmmr0: the pwmtc will be reset if pwmmr0 matches it. 2 pwmmr0s stop pwm0 0 0 disabled 1 stop on pwmmr0: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr0 matches the pwmtc. 3 pwmmr1i interrupt pwm1 0 0 disabled. 1 interrupt on pwmmr1: an interrupt is generated when pwmmr1 matches the value in the pwmtc.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 713 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 4pwmmr1r reset pwm1 0 0 disabled. 1 reset on pwmmr1: the pwmtc will be reset if pwmmr1 matches it. 5 pwmmr1s stop pwm1 0 0 disabled 1 stop on pwmmr1: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr1 matches the pwmtc. 6 pwmmr2i interrupt pwm0 0 0 disabled. 1 interrupt on pwmmr2: an interrupt is generated when pwmmr2 matches the value in the pwmtc. 7pwmmr2r reset pwm0 0 0 disabled. 1 reset on pwmmr2: the pwmtc will be reset if pwmmr2 matches it. 8 pwmmr2s stop pwm0 0 0 disabled 1 stop on pwmmr2: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr0 matches the pwmtc. 9 pwmmr3i interrupt pwm3 0 0 disabled. 1 interrupt on pwmmr3: an interrupt is generated when pwmmr3 matches the value in the pwmtc. 10 pwmmr3r reset pwm3 0 0 disabled. 1 reset on pwmmr3: the pwmtc will be reset if pwmmr3 matches it. 11 pwmmr3s stop pwm0 0 0 disabled 1 stop on pwmmr3: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr0 matches the pwmtc. 12 pwmmr4i interrupt pwm4 0 0 disabled. 1 interrupt on pwmmr4: an interrupt is generated when pwmmr4 matches the value in the pwmtc. 13 pwmmr4r reset pwm4 0 0 disabled. 1 reset on pwmmr4: the pwmtc will be reset if pwmmr4 matches it. 14 pwmmr4s stop pwm4 0 0 disabled 1 stop on pwmmr4: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr4 matches the pwmtc. table 560. match control register (mcr - address 0x4001 4014 (pwm0) and 0x4001 8014 (pwm1)) bit description bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 714 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.7 pwm match registers the 32-bit pwm match register values are continuously compared to the pwm timer counter value. when the two values are equa l, actions can be triggered automatically. the action possibilities are to generate an interrupt, reset th e pwm timer counter, or stop the timer. actions are controlled by th e settings in the pwmmcr register. 15 pwmmr5i interrupt pwm5 0 0 disabled. 1 interrupt on pwmmr5: an interrupt is generated when pwmmr5 matches the value in the pwmtc. 16 pwmmr5r reset pwm5 0 0 disabled. 1 reset on pwmmr5: the pwmtc will be reset if pwmmr5 matches it. 17 pwmmr5s stop pwm5 0 0 disabled 1 stop on pwmmr5: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr5 matches the pwmtc. 18 pwmmr6i interrupt pwm6 0 0 disabled. 1 interrupt on pwmmr6: an interrupt is generated when pwmmr6 matches the value in the pwmtc. 19 pwmmr6r reset pwm6 0 0 disabled. 1 reset on pwmmr6: the pwmtc will be reset if pwmmr6 matches it. 20 pwmmr6s stop pwm6 0 0 disabled 1 stop on pwmmr6: the pwmtc and pwmpc will be stopped and pwmtcr bit 0 will be set to 0 if pwmmr6 matches the pwmtc. 31:21 - reserved. read value is undefined, only zero should be written. na table 560. match control register (mcr - address 0x4001 4014 (pwm0) and 0x4001 8014 (pwm1)) bit description bit symbol value description reset value table 561. pwm match registers (mr[0:3], addresses 0x4001 4018 (mr0) to 0x4001 4024 (mr3) (pwm0), 0x4001 8018 (mr0) to 0x4001 5024 (mr3) (pwm1)) bit description bit symbol description reset value 31:0 match timer counter match value. 0 table 562. pwm match registers (mr[4:6], addresses 0x4001 4040 (mr4) to 0x4001 4048 (mr6) (pwm0), 0x4001 8040 (mr4) to 0x4001 5048 (mr6) (pwm1)) bit description bit symbol description reset value 31:0 match timer counter match value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 715 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.8 pwm capture control register the capture control register is used to cont rol whether any of the capture registers is loaded with the value in the timer counter when a capture event occurs on pwm0_cap0 or pwm1_cap1:0, and whether an interrupt is generated by the capture event. setting both the rising and falling bits at the same time is a valid configuration, resulting in a capture event for both edges. in the descriptions below, ?n? represents the timer number, 0 or 1. note: if counter mode is selected for a particular pwm_cap input in the ctcr, the 3 bits for that input in this register should be pr ogrammed as 000, but capture and/or interrupt can be selected for the other two pwm_cap inputs. 26.6.9 pwm capture registers each 32-bit capture register is associated with a device pin and may be loaded with the pwm timer counter value when a specified even t occurs on that pin. the settings in the pwm capture control register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. table 563: pwm capture control register (ccr - address 0x4001 4028 (pwm0) and 0x4001 8028 (pwm1)) bit description bit symbol value description reset value 0 cap0_r capture on pwmn_cap0 rising edge 0 0 disabled. this feature is disabled. 1 rising edge. a synchronously sampled rising edge on pwmn_cap0 will cause cr0 to be loaded with the contents of the tc. 1 cap0_f capture on pwmn_cap0 falling edge 0 0 disabled. this feature is disabled. 1 falling edge. a synchronously sampled falling edge on pwmn_cap0 will cause cr0 to be loaded with the contents of tc. 2 cap0_i interrupt on pwmn_cap0 event 0 0 disabled. this feature is disabled. 1 interrupt. a cr0 load due to a pwmn_cap0 event will generate an interrupt. 3 cap1_r capture on pwmn_cap1 rising edge. reserved for pwm0. 0 0 disabled. this feature is disabled. 1 rising edge. a synchronously sampled rising edge on pwmn_cap1 will cause cr1 to be loaded with the contents of the tc. 4 cap1_f capture on pwmn_cap1 falling edge. reserved for pwm0. 0 0 disabled. this feature is disabled. 1 falling edge. a synchronously sampled falling edge on pwmn_cap1 will cause cr1 to be loaded with the contents of tc. 5 cap1_i interrupt on pwmn_cap1 event. reserved for pwm0. 0 0 disabled. this feature is disabled. 1 interrupt. a cr1 load due to a pwmn_cap1 event will generate an interrupt. 31:6 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 716 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.10 pwm control registers the pwm control registers are used to enable and select the type of each pwm channel. the function of each of the bits are shown in ta b l e 5 6 5 . table 564. pwm capture registers (cr[0:1], address 0x4001 402c (cr0) to 0x4001 4038 (cr3) (pwm0), 0x4001 802c (cr0) to 0x4001 8038 (cr3) (pwm1)) bit description bit symbol description reset value 31:0 cap timer counter capture value. 0 table 565: pwm control registers (pcr - address 0x4001 404c (pwm0) and 0x4001 804c (pwm1)) bit description bit symbol value description reset value 1:0 - reserved. - 2 pwmsel2 pwm[2] output single/double edge mode control. 0 0 single edge controlled mode is selected. 1 double edge controlled mode is selected. 3 pwmsel3 pwm[3] output edge control. 0 0 single edge controlled mode is selected. 1 double edge controlled mode is selected. 4 pwmsel4 pwm[4] output edge control. 0 0 single edge controlled mode is selected. 1 double edge controlled mode is selected. 5 pwmsel5 pwm[5] output edge control. 0 0 single edge controlled mode is selected. 1 double edge controlled mode is selected. 6 pwmsel6 pwm[6] output edge control. 0 0 single edge controlled mode is selected. 1 double edge controlled mode is selected. 8:7 - reserved. read value is undefined, only zero should be written. - 9 pwmena1 pwm[1] output enable control. 0 0 the pwm output is disabled. 1 the pwm output is enabled. 10 pwmena2 pwm[2] output enable control. 0 0 the pwm output is disabled. 1 the pwm output is enabled. 11 pwmena3 pwm[3] output enable control. 0 0 the pwm output is disabled. 1 the pwm output is enabled. 12 pwmena4 pwm[4] output enable control. 0 0 the pwm output is disabled. 1 the pwm output is enabled.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 717 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.11 pwm latch enable register the pwm latch enable registers are used to control the update of the pwm match registers when they are used fo r pwm generation. when software writes to the location of a pwm match register while th e timer is in pwm mode, the value is actually held in a shadow register and not used immediately. when a pwm match 0 event occurs (normally also resetting the timer in pwm mode), the contents of shadow registers will be transferred to the ac tual match registers if the corresponding bit in the latch enable register has been set. at that point, the new values will take effect and determine the course of the next pwm cycle. once the transfer of new values has taken place, all bits of the ler are automatically cleared. until the corresponding bit in the pwmler is set and a pwm match 0 event occurs, any value written to the pwm match registers has no effect on pwm operation. for example, if pwm is configured for double edge operation and is currently running, a typical sequence of events for changing the timing would be: ? write a new value to the pwm match1 register. ? write a new value to the pwm match2 register. ? write to the pwmler, setting bits 1 and 2 at the same time. ? the altered values will become effective at the next rese t of the timer (when a pwm match 0 event occurs). the order of writing the two pw m match registers is not import ant, since neither value will be used until after the write to pwmler. this insures that both values go into effect at the same time, if that is required. a single value may be altered in the same way if needed. 13 pwmena5 pwm[5] output enable control. 0 0 the pwm output is disabled. 1 the pwm output is enabled. 14 pwmena6 pwm[6] output enable control. see pwmena1 for details. 0 0 the pwm output is disabled. 1 the pwm output is enabled. 31:15 - unused, always zero. na table 565: pwm control registers (pcr - address 0x4001 404c (pwm0) and 0x4001 804c (pwm1)) bit description bit symbol value description reset value table 566: pwm latch enable register (ler - address 0x4001 4050 (pwm0) and 0x4001 8050 (pwm1)) bit description bit symbol description reset value 0 mat0latchen enable pwm match 0 latch. pwm mr0 register update control. writing a one to this bit allows the last value written to the pwm match register 0 to be become effective when the timer is next reset by a pwm match event. see section 26.6.6 . 0 1 mat1latchen enable pwm match 1 latch. pwm mr1 register update control. see bit 0 for details. 0 2 mat2latchen enable pwm match 2 latch. pwm mr2 register update control. see bit 0 for details. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 718 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 3 mat3latchen enable pwm match 3 latch. pwm mr3 register update control. see bit 0 for details. 0 4 mat4latchen enable pwm match 4 latch. pwm mr4 register update control. see bit 0 for details. 0 5 mat5latchen enable pwm match 5 latch. pwm mr5 register update control. see bit 0 for details. 0 6 mat6latchen enable pwm match 6 latch. pwm mr6 register update control. see bit 0 for details. 0 31:7 - reserved. read value is undefined, only zero should be written. na table 566: pwm latch enable register (ler - address 0x4001 4050 (pwm0) and 0x4001 8050 (pwm1)) bit description bit symbol description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 719 of 942 nxp semiconductors UM10562 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.6.12 pwm count control register the count control register (c tcr) is used to select be tween timer and counter mode, and in counter mode to select the pin and edges for counting. the function of each of the bits is shown in table 567 . remark: the input frequency of pwm_cap must not exceed pclk/4. when the pwm clock is supplied via the pwm_cap pin, at no time can a high or low level of the signal on this pin last less than 2 pclks. table 567: pwm count control register (ctcr - address 0x4001 4070 (pwm0) and 0x4001 8070 (pwm1)) bit description bit symbol value description reset value 1:0 mod counter/timer mode 0 0x0 timer mode: the tc is incremented when the prescale counter matches the prescale register. 0x1 rising edge counter mode: the tc is incremented on rising edges of the pwm_cap input selected by bits 3:2. 0x2 falling edge counter mode: the tc is incremented on falling edges of the pwm_cap input selected by bits 3:2. 0x3 dual edge counter mode: the tc is incremented on both edges of the pwm_cap input selected by bits 3:2. 3:2 cis count input select. when bits 1:0 are not 00, these bits select which pwm_cap pin carries the signal used to increment the tc. other combinations are reserved. 0 0x0 for pwm0: 00 = pwm0_cap0 (other combinations are reserved) for pwm1: 00 = pwm1_cap0, 01 = pwm1_cap1 (other combinations are reserved) 31:4 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 720 of 942 27.1 basic configuration the motor control pwm is configur ed using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcmcpwm. remark: on reset, the mcpwm is disabled (pcmcpwm = 0). 2. peripheral clock: the mcpwm operates from the common pclk that clocks both the bus interface and functional porti on of most apb peripherals. see section 3.3.3.5 . 3. pins: select mcpwm pins through and pin modes for port pins with mcpwm functions through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: see section 27.9.8 . the mcpwm interrupt is e nabled in the nvic using the appropriate interrupt set enable register. 27.2 introduction the motor control pwm (mcpwm) is optimize d for three-phase ac and dc motor control applications, but can be used in many othe r applications that need timing, counting, capture, and comparison. 27.3 description the mcpwm contains three independent channels, each including: ? a 32-bit timer/counter (tc) ? a 32-bit limit register (lim) ? a 32-bit match register (mat) ? a 10-bit dead-time register (dt) and an associated 10-bit dead-time counter ? a 32-bit capture register (cap) ? two modulated outputs (mc_a and mc_b) with opposite polarities ? a period interrupt, a pulse-width interrupt, and a capture interrupt input pins mc_fb0-2 can trigger tc capture or increment a channel?s tc. a global abort input can force all of the channels into ?a passive? state and cause an interrupt. UM10562 chapter 27: lpc408x/4 07x motor control pwm rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 721 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.4 pin description table 568 lists the mcpwm pins. table 568. pin summary pin type description mc_0a, mc_0b o outputs a and b for channel 0 mc_1a, mc_1b o outputs a and b for channel 1 mc_2a, mc_2b o outputs a and b for channel 2 mc_abort i low-active fast abort mc_fb0, mc_fb1, mc_fb2 i inputs for channels 0, 1, 2. each level on this pin must be at least 1 pclk in duration in order to be sampled.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 722 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.5 block diagram fig 145. mcpwm block diagram clock selection pclk mc_fb0-2 clock selection clock selection tc0 tc1 tc2 event selection mccntcon mccapcon = mat0 (oper) mat0 (write) lim0 (oper) lim0 (write) = cap0 channel output control dead- time counter dt0 mccon rt0 cntl = mat1 (oper) mat1 (write) lim1 (oper) lim1 (write) = cap1 dt1 mccon rt1 mat2 (oper) mat2 (write) lim2 (oper) lim2 (write) global output control mccon mccp mc_abort mc_a0 mc_b0 mc_a1 mc_b1 mc_a2 mc_b2 mux cntl cntl = = cap2 dt2 mccon rt2 mux acmode interrupt logic mc_abort mcinten mcintf mux mux acmode acmode dead- time counter dead- time counter channel output control channel output control event selection event selection acmode a0 b0 a1 b1 a2 b2
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 723 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.6 configuring other modules for mcpwm use configure the following registers in other modules before using the motor control pwm: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcmcpwm. remark: on reset the mcpwm is disabled (pcmcpwm = 0). 2. peripheral clock: the mcpwm operates fr om the common pclk that clocks both the bus interface and functional porti on of most apb peripherals. see section 3.3.3.5 . 3. pins: select mcpwm functions and pin mo des for these pins through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: see section 27.8.9 for motor control pwm related interrupts. interrupts can be enabled in the nvic using the appropriate interrupt set enable register. 27.7 general operation section 27.9 includes detailed descriptions of t he various modes of mcpwm operation, but a quick preview here will provide background for the r egister descriptions below. the mcpwm includes 3 channels, each of which controls a pair of outputs that in turn can control something off-chip, like one set of coils in a motor. each channel includes a timer/counter (tc) register that is incremen ted by a processor clock (timer mode) or by an input pin (counter mode). each channel has a limit register that is compared to the tc value, and when a match occurs the tc is ?recycled? in one of two ways. in ?edge-aligned mode? the tc is reset to 0, while in ?centered mode? a match switches the tc into a state in which it decrements on each processor clock or input pin transition until it reaches 0, at which time it starts counting up again. each channel also includes a match register that holds a smaller value than the limit register. in edge-aligned mode the channel? s outputs are switched whenever the tc matches either the match or limit register, wh ile in center-aligned mode they are switched only when it matches the match register. so the limit register controls the period of th e outputs, while the match register controls how much of each period the outputs spend in each state. having a small value in the limit register minimizes ?ripple? if the output is integrated into a voltage, and allows the mcpwm to control devices that operate at high speed. the ?downside? of small values in the limit re gister is that they reduce the resolution of the duty cycle controlled by the match register. if you have 8 in the limit register, the match register can only select the duty cycl e among 0%, 12.5%, 25%, ?, 87.5%, or 100%. in general, the resolution of each step in the match value is 1 divided by the limit value. this trade-off between resolution and period/fre quency is inherent in the design of pulse width modulators.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 724 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8 register description ?control? registers and ?interrupt? registers ha ve separate read, set, and clear addresses. reading such a register?s read address (e.g. mc con) yields the state of the register bits. writing ones to the set address (e.g. mccon_set) sets register bits, and writing ones to the clear address (e.g. mccon_clr) clears register bits. the capture registers (mccap) are read-only, and the wr ite-only mccap_clr address can be used to clear one or more of them. all the other mcpwm registers (mctim, mcper, mcpw, mcdeadtime, and mccp) are normal read-write registers. table 569. register overview: motor control pulse width modulator (mcpwm) (base address 0x400b 8000) name access address offset description reset value reference con ro 0x000 pwm control read address 0 table 570 con_set wo 0x004 pwm control set address - table 571 con_clr wo 0x008 pwm control clear address - table 572 capcon ro 0x00c capture control read address 0 table 573 capcon_set wo 0x010 capture control set address - table 574 capcon_clr wo 0x014 event control clear address - table 575 tc0 r/w 0x018 timer counter register, channel 0 0 table 576 tc1 r/w 0x01c timer counter register, channel 1 0 table 576 tc2 r/w 0x020 timer counter register, channel 2 0 table 576 lim0 r/w 0x024 limit register, channel 0 0xffff ffff table 577 lim1 r/w 0x028 limit register, channel 1 0xffff ffff table 577 lim2 r/w 0x02c limit register, channel 2 0xffff ffff table 577 mat0 r/w 0x030 match register, channel 0 0xffff ffff table 578 mat1 r/w 0x034 match register, channel 1 0xffff ffff table 578 mat2 r/w 0x038 match register, channel 2 0xffff ffff table 578 dt r/w 0x03c dead time register 0x3fff ffff table 579 mccp r/w 0x040 communication pattern register 0 table 580 cap0 ro 0x044 capture register, channel 0 0 table 581 cap1 ro 0x048 capture register, channel 1 0 table 581 cap2 ro 0x04c capture register, channel 2 0 table 581 inten ro 0x050 interrupt enable read address 0 table 583 inten_set wo 0x054 interrupt enable set address - table 584 inten_clr wo 0x058 interrupt enable clear address - table 585 cntcon ro 0x05c count control read address 0 table 586 cntcon_set wo 0x060 count control set address - table 587 cntcon_clr wo 0x064 count control clear address - table 588 intf ro 0x068 interrupt flags read address 0 table 589 intf_set wo 0x06c interrupt flags set address - table 590 intf_clr wo 0x070 interrupt flags clear address - table 591 cap_clr wo 0x074 capture clear address - table 592
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 725 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.1 mcpwm control register 27.8.1.1 mcpwm control read address the con register controls the operation of all channels of the pwm. this address is read-only, but the underlying register can be modified by writing to addresses con_set and con_clr. table 570. mcpwm control read address (con - 0x400b 8000) bit description bit symbol value description reset value 0 run0 stops/starts timer channel 0. 0 0stop. 1run. 1 center0 edge/center aligned operation for channel 0. 0 0 edge-aligned. 1 center-aligned. 2 pola0 selects polarity of the mcoa0 and mcob0 pins. 0 0 passive state is low, active state is high. 1 passive state is high, active state is low. 3 dte0 controls the dead-time feature for channel 0. 0 0 dead-time disabled. 1 dead-time enabled. 4 disup0 enable/disable updates of functional registers for channel 0 (see section 27.9.2 ). 0 0 functional registers are updated from the write registers at the end of each pwm cycle. 1 functional registers remain the same as long as the timer is running. 7:5 - - reserved. 8 run1 stops/starts timer channel 1. 0 0stop. 1run. 9 center1 edge/center aligned operation for channel 1. 0 0 edge-aligned. 1 center-aligned. 10 pola1 selects polarity of the mcoa1 and mcob1 pins. 0 0 passive state is low, active state is high. 1 passive state is high, active state is low. 11 dte1 controls the dead-time feature for channel 1. 0 0 dead-time disabled. 1 dead-time enabled. 12 disup1 enable/disable updates of functional registers for channel 1 (see section 27.9.2 ). 0 0 functional registers are updated from the write registers at the end of each pwm cycle. 1 functional registers remain the same as long as the timer is running. 15:13 - - reserved. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 726 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.1.2 mcpwm control set address writing ones to this write-only address sets the corresponding bits in mccon. 16 run2 stops/starts timer channel 2. 0 0stop. 1run. 17 center2 edge/center aligned operation for channel 2. 0 0 edge-aligned. 1 center-aligned. 18 pola2 selects polarity of the mcoa2 and mcob2 pins. 0 0 passive state is low, active state is high. 1 passive state is high, active state is low. 19 dte2 controls the dead-time feature for channel 1. 0 0 dead-time disabled. 1 dead-time enabled. 20 disup2 enable/disable updates of functional registers for channel 2 (see section 27.9.2 ). 0 0 functional registers are updated from the write registers at the end of each pwm cycle. 1 functional registers remain the same as long as the timer is running. 28:21 - - reserved. 29 invbdc controls the polarity of the mcob outputs for all 3 channels. this bit is typically set to 1 only in 3-phase dc mode. 0 the mcob outputs have opposite polarity from the mcoa outputs (aside from dead time). 1 the mcob outputs have the same basic polarity as the mcoa outputs. (see section 27.9.6 ) 30 acmode 3-phase ac mode select (see section 27.9.7 ). 0 0 3-phase ac-mode off: each pwm channel uses its own timer-counter and period register. 1 3-phase ac-mode on: all pwm channels use the timer-counter and period register of channel 0. 31 dcmode 3-phase dc mode select (see section 27.9.6 ). 0 0 3-phase dc mode off: pwm channels are independent (unless bit acmode = 1) 1 3-phase dc mode on: the internal mcoa0 output is routed through the cp register (i.e. a mask) register to all six pwm outputs. table 570. mcpwm control read address (con - 0x400b 8000) bit description bit symbol value description reset value table 571. mcpwm control set address (con_set - 0x400b 8004) bit description bit symbol description reset value 0 run0_set writing a one sets the corresponding bit in the con register. - 1 center0_set writing a one sets the corresponding bit in the con register. - 2 pola0_set writing a one sets the corresponding bit in the con register. - 3 dte0_set writing a one sets the corresponding bit in the con register. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 727 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.1.3 mcpwm control clear address writing ones to this write-only address clears the corresponding bits in con. 4 disup0_set writing a one sets the corresponding bit in the con register. - 7:5 - writing a one sets the corresponding bit in the con register. - 8 run1_set writing a one sets the corresponding bit in the con register. - 9 center1_set writing a one sets the corresponding bit in the con register. - 10 pola1_set writing a one sets the corresponding bit in the con register. - 11 dte1_set writing a one sets the corresponding bit in the con register. - 12 disup1_set writing a one sets the corresponding bit in the con register. - 15:13 - writing a one sets the corresponding bit in the con register. - 16 run2_set writing a one sets the corresponding bit in the con register. - 17 center2_set writing a one sets the corresponding bit in the con register. - 18 pola2_set writing a one sets the corresponding bit in the con register. - 19 dte2_set writing a one sets the corresponding bit in the con register. - 20 disup2_set writing a one sets the corresponding bit in the con register. - 28:21 - writing a one sets the corresponding bit in the con register. - 29 invbdc_set writing a one sets the corresponding bit in the con register. - 30 acmode_set writing a one sets the corresponding bit in the con register. - 31 dcmode_set writing a one sets the corresponding bit in the con register. - table 571. mcpwm control set address (con_set - 0x400b 8004) bit description bit symbol description reset value table 572. mcpwm control clear address (con_clr - 0x400b 8008) bit description bit symbol description reset value 0 run0_clr writing a one clears the corresponding bit in the con register. - 1 center0_clr writing a one clears the corresponding bit in the con register. - 2 pola0_clr writing a one clears the corresponding bit in the con register. - 3 dte0_clr writing a one clears the corresponding bit in the con register. - 4 disup0_clr writing a one clears the corresponding bit in the con register. - 7:5 - writing a one clears the corresponding bit in the con register. - 8 run1_clr writing a one clears the corresponding bit in the con register. - 9 center1_clr writing a one clears the corresponding bit in the con register. - 10 pola1_clr writing a one clears the corresponding bit in the con register. - 11 dte1_clr writing a one clears the corresponding bit in the con register. - 12 disup1_clr writing a one clears the corresponding bit in the con register. - 15:1 3 - writing a one clears the corresponding bit in the con register. - 16 run2_clr writing a one clears the corresponding bit in the con register. - 17 center2_clr writing a one clears the corresponding bit in the con register. - 18 pola2_clr writing a one clears the corresponding bit in the con register. - 19 dte2_clr writing a one clears the corresponding bit in the con register. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 728 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.2 pwm capture control register 27.8.2.1 mcpwm capture control read address the mccapcon register controls detection of events on the mci0-2 inputs for all mcpwm channels. any of the three mci inputs can be used to trigger a capture event on any or all of the three channels. this address is read-only, but the underlying register can be modified by writing to addresses capcon_set and capcon_clr. 20 disup2_clr writing a one clears the corresponding bit in the con register. - 28:2 1 - writing a one clears the corresponding bit in the con register. - 29 invbdc_clr writing a one clears the corresponding bit in the con register. - 30 acmod_clr writing a one clears the corresponding bit in the con register. - 31 dcmode_clr writing a one clears the corresponding bit in the con register. table 572. mcpwm control clear address (con_clr - 0x400b 8008) bit description bit symbol description reset value table 573. mcpwm capture control read address (capcon - 0x400b 800c) bit description bit symbol description reset value 0 cap0mci0_re a 1 in this bit enables a channel 0 capture event on a rising edge on mci0. 0 1 cap0mci0_fe a 1 in this bit enables a channel 0 capture event on a falling edge on mci0. 0 2 cap0mci1_re a 1 in this bit enables a channel 0 capture event on a rising edge on mci1. 0 3 cap0mci1_fe a 1 in this bit enables a channel 0 capture event on a falling edge on mci1. 0 4 cap0mci2_re a 1 in this bit enables a channel 0 capture event on a rising edge on mci2. 0 5 cap0mci2_fe a 1 in this bit enables a channel 0 capture event on a falling edge on mci2. 0 6 cap1mci0_re a 1 in this bit enables a channel 1 capture event on a rising edge on mci0. 0 7 cap1mci0_fe a 1 in this bit enables a channel 1 capture event on a falling edge on mci0. 0 8 cap1mci1_re a 1 in this bit enables a channel 1 capture event on a rising edge on mci1. 0 9 cap1mci1_fe a 1 in this bit enables a channel 1 capture event on a falling edge on mci1. 0 10 cap1mci2_re a 1 in this bit enables a channel 1 capture event on a rising edge on mci2. 0 11 cap1mci2_fe a 1 in this bit enables a channel 1 capture event on a falling edge on mci2. 0 12 cap2mci0_re a 1 in this bit enables a channel 2 capture event on a rising edge on mci0. 0 13 cap2mci0_fe a 1 in this bit enables a channel 2 capture event on a falling edge on mci0. 0 14 cap2mci1_re a 1 in this bit enables a channel 2 capture event on a rising edge on mci1. 0 15 cap2mci1_fe a 1 in this bit enables a channel 2 capture event on a falling edge on mci1. 0 16 cap2mci2_re a 1 in this bit enables a channel 2 capture event on a rising edge on mci2. 0 17 cap2mci2_fe a 1 in this bit enables a channel 2 capture event on a falling edge on mci2. 0 18 rt0 if this bit is 1, tc0 is reset by a channel 0 capture event. 0 19 rt1 if this bit is 1, tc1 is reset by a channel 1 capture event. 0 20 rt2 if this bit is 1, tc2 is reset by a channel 2 capture event. 0 21 hnfcap0 hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in section 27.9.4 . 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 729 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.2.2 mcpwm capture control set address writing ones to this write-only address sets the corresponding bits in capcon. 27.8.2.3 mcpwm capture control clear address writing ones to this write-only address clears the corresponding bits in mccapcon. 22 hnfcap1 hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in section 27.9.4 . 0 23 hnfcap2 hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in section 27.9.4 . 0 31:24 - reserved. - table 573. mcpwm capture control read address (capcon - 0x400b 800c) bit description bit symbol description reset value table 574. mcpwm capture control set address (capcon_set - 0x400b 8010) bit description bit symbol description reset value 0 cap0mci0_re_set writing a one sets the corresponding bits in the capcon register. - 1 cap0mci0_fe_set writing a one sets the corresponding bits in the capcon register. - 2 cap0mci1_re_set writing a one sets the corresponding bits in the capcon register. - 3 cap0mci1_fe_set writing a one sets the corresponding bits in the capcon register. - 4 cap0mci2_re_set writing a one sets the corresponding bits in the capcon register. - 5 cap0mci2_fe_set writing a one sets the corresponding bits in the capcon register. - 6 cap1mci0_re_set writing a one sets the corresponding bits in the capcon register. - 7 cap1mci0_fe_set writing a one sets the corresponding bits in the capcon register. - 8 cap1mci1_re_set writing a one sets the corresponding bits in the capcon register. - 9 cap1mci1_fe_set writing a one sets the corresponding bits in the capcon register. - 10 cap1mci2_re_set writing a one sets the corresponding bits in the capcon register. - 11 cap1mci2_fe_set writing a one sets the corresponding bits in the capcon register. - 12 cap2mci0_re_set writing a one sets the corresponding bits in the capcon register. - 13 cap2mci0_fe_set writing a one sets the corresponding bits in the capcon register. - 14 cap2mci1_re_set writing a one sets the corresponding bits in the capcon register. - 15 cap2mci1_fe_set writing a one sets the corresponding bits in the capcon register. - 16 cap2mci2_re_set writing a one sets the corresponding bits in the capcon register. - 17 cap2mci2_fe_set writing a one sets the corresponding bits in the capcon register. - 18 rt0_set writing a one sets the corresponding bits in the capcon register. - 19 rt1_set writing a one sets the corresponding bits in the capcon register. - 20 rt2_set writing a one sets the corresponding bits in the capcon register. - 21 hnfcap0_set writing a one sets the corresponding bits in the capcon register. - 22 hnfcap1_set writing a one sets the corresponding bits in the capcon register. - 23 hnfcap2_set writing a one sets the corresponding bits in the capcon register. - 31:24 - reserved. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 730 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.3 mcpwm timer/counter 0-2 registers these registers hold the current values of the 32-bit counter/timers for channels 0-2. each value is incremented on every pclk, or by edges on the mci0-2 pins, as selected by cntcon. the timer/counter counts up from 0 until it reaches the value in its corresponding per register (or is stopped by writing to con_clr). a tc register can be read at any time. in order to write to the tc register, its channel must be stopped. if not, the write will not ta ke place, no exception is generated. table 575. mcpwm capture control clear register (capcon_clr - address 0x400b 8014) bit description bit symbol description reset value 0 cap0mci0_re_clr writing a one clears the corresponding bits in the capcon register. - 1 cap0mci0_fe_clr writing a one clears the corresponding bits in the capcon register. - 2 cap0mci1_re_clr writing a one clears the corresponding bits in the capcon register. - 3 cap0mci1_fe_clr writing a one clears the corresponding bits in the capcon register. - 4 cap0mci2_re_clr writing a one clears the corresponding bits in the capcon register. - 5 cap0mci2_fe_clr writing a one clears the corresponding bits in the capcon register. - 6 cap1mci0_re_clr writing a one clears the corresponding bits in the capcon register. - 7 cap1mci0_fe_clr writing a one clears the corresponding bits in the capcon register. - 8 cap1mci1_re_clr writing a one clears the corresponding bits in the capcon register. - 9 cap1mci1_fe_clr writing a one clears the corresponding bits in the capcon register. - 10 cap1mci2_re_clr writing a one clears the corresponding bits in the capcon register. - 11 cap1mci2_fe_clr writing a one clears the corresponding bits in the capcon register. - 12 cap2mci0_re_clr writing a one clears the corresponding bits in the capcon register. - 13 cap2mci0_fe_clr writing a one clears the corresponding bits in the capcon register. - 14 cap2mci1_re_clr writing a one clears the corresponding bits in the capcon register. - 15 cap2mci1_fe_clr writing a one clears the corresponding bits in the capcon register. - 16 cap2mci2_re_clr writing a one clears the corresponding bits in the capcon register. - 17 cap2mci2_fe_clr writing a one clears the corresponding bits in the capcon register. - 18 rt0_clr writing a one clears the corresponding bits in the capcon register. - 19 rt1_clr writing a one clears the corresponding bits in the capcon register. - 20 rt2_clr writing a one clears the corresponding bits in the capcon register. - 21 hnfcap0_clr writing a one clears the corresponding bits in the capcon register. - 22 hnfcap1_clr writing a one clears the corresponding bits in the capcon register. - 23 hnfcap2_clr writing a one clears the corresponding bits in the capcon register. - 31:24 - reserved. - table 576. mcpwm timer/counter 0 to 2 registers (tc[0:2] - 0x400b 8018 (tc0), 0x400b 801c (tc1), 0x400b 8020) (tc2)bit description bit symbol description reset value 31:0 mctc timer/counter value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 731 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.4 mcpwm limi t 0-2 registers these registers hold the limiting values fo r timer/counters 0-2. when a timer/counter reaches its corresponding limiting value: 1) in edge-aligned mode, it is reset and starts over at 0; 2) in center-aligned mode, it begins counting down until it reaches 0, at which time it begins counting up again. if the channel?s center bit in con is 0 selecting edge-aligned mode, the match between tc and lim switches the channel?s a output from ?active? to ?passive? state. if the channel?s center and dte bits in con are both 0, the match simultaneously switches the channel?s b output from ?p assive? to ?active? state. if the channel?s center bit is 0 but the dte bit is 1, the match triggers the channel?s deadtime counter to begin counting -- when the deadtime counter expires, the channel?s b output switches from ?pas sive? to ?active? state. in center-aligned mode, matches between a channel?s tc and lim registers have no effect on its a and b outputs. writing to either a limit or a match ( 27.8.5 ) register loads a ?write ? register, and if the channel is stopped it also loads an ?operating? register that is compared to the tc. if the channel is running and its ?disable update? bi t in con is 0, the operating registers are loaded from the write registers: 1) in ed ge-aligned mode, when the tc matches the operating limit register; 2) in center-aligned mo de, when the tc counts back down to 0. if the channel is running and the ?disable update? bit is 1, the operating registers are not loaded from the write registers until software stops the channel. reading an lim address always returns the operating value. remark: in timer mode, the period of a channel?s modulated mco outputs is determined by its limit register, and the pulse width at the start of the period is determined by its match register. if it suits your way of thinking , consider the limit register to be the ?period register? and the match register to be the ?pulse width register?. 27.8.5 mcpwm match 0-2 registers these registers also have ?write? and ?opera ting? versions as described above for the limit registers, and the operat ing registers are also compared to the channels? tcs. see 27.8.4 above for details of reading and wr iting both limit and match registers. the match and limit registers control the mco0- 2 outputs. if a match register is to have any effect on its channel?s operation, it must contain a smaller value than the corresponding limit register. table 577. mcpwm limit 0 to 2 registers (lim[0:2] - 0x400b 8024 (lim0), 0x400b 8028 (lim1), 0x400b 802c (lim2)) bit description bit symbol description reset value 31:0 mclim limit value. 0xffff ffff table 578. mcpwm match 0 to 2 registers (mat[0:2] - addresses 0x400b 8030 (mat0), 0x400b 8034 (mat1), 0x400b 8038 (mat2)) bit description bit symbol description reset value 31:0 mcmat match value. 0xffff ffff
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 732 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.5.1 match register in edge-aligned mode if the channel?s center bit in con is 0 selecting edge-aligned mode, a match between tc and mat switches the channel?s b output from ?active? to ?passive? state. if the channel?s center and dte bits in con are both 0, the match simultaneously switches the channel?s a output from ?p assive? to ?active? state. if the channel?s center bit is 0 but the dte bit is 1, the match triggers the channel?s deadtime counter to begin counting -- when the deadtime counter expires, the channel?s a output switches from ?pas sive? to ?active? state. 27.8.5.2 match register in center-aligned mode if the channel?s center bit in con is 1 selecting center-aligned mode, a match between tc and mat while the tc is incrementing switches the channel?s b output from ?active? to ?passive? state, and a match while the tc is decrementing switches the a output from ?active? to ?passive?. if the channel?s center bit in con is 1 but the dte bit is 0, a match simultaneously switches the channel?s ot her output in the opposite direction. if the channel?s center and dte bits are both 1, a match between tc and mat triggers the channel?s deadtime counter to begin counting -- when the deadtime counter expires, the channel?s b output switches from ?passive? to ?active? if the tc was counting up at the time of the match, and the channel?s a output sw itches from ?passive? to ?active? if the tc was counting down at the time of the match. 27.8.5.3 0 and 100% duty cycle to lock a channel?s mco outputs at the state ?b active, a passive?, write its match register with a higher value than you write to it s limit register. the match never occurs. to lock a channel?s mco outputs at the opposit e state, ?a active, b passive?, simply write 0 to its match register. 27.8.6 mcpwm dead-time register this register holds the dead-time values for the three channels. if a channel?s dte bit in con is 1 to enable its dead-time counter, the counter counts dow n from this value whenever one its channel?s outputs changes fr om ?active? to ?passive? state. when the dead-time counter reaches 0, the channel changes its other output from ?passive? to ?active? state. the motivation for the dead-time feature is that power transistors, like those driven by the a and b outputs in a motor-control application, take longer to fully turn off than they take to start to turn on. if the a and b transistors are ever turned on at the same time, a wasteful and damaging current will flow between the power rails through the transistors. in such applications, the dead-time r egister should be programmed with the number of pclk periods that is greater than or equal to the transistors? maximum turn -off time minus their minimum turn-on time.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 733 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm [1] if acmode is 1 selecting ac-mode, this fi eld controls the dead time for all three channels. [2] if acmode is 0. 27.8.7 mcpwm communication pattern register this register is used in dc mode only. the internal mcoa0 signal is routed to any or all of the six output pins under the control of the bits in this register. like the match and limit registers, this register has ?wri te? and ?operational? versions. see 27.8.4 and 27.9.2 for more about this subject. 27.8.8 mcpwm capt ure read addresses the capcon register ( table 573 ) allows software to select any edges on any of the mci0-2 inputs as a capture event for each channel. when a channel?s capture event occurs, the current tc value for that channel is stored in its read-only capture register. these addresses are read-only, but the underlying registers ca n be cleared by writing to the cap_clr address table 579. mcpwm dead-time register (dt - address 0x400b 803c) bit description bit symbol description reset value 9:0 dt0 dead time for channel 0. [1] 0x3ff 19:10 dt1 dead time for channel 1. [2] 0x3ff 29:20 dt2 dead time for channel 2. [2] 0x3ff 31:30 - reserved table 580. mcpwm communication pattern register (cp - address 0x400b 8040) bit description bit symbol value description reset value 0 ccpa0 communication pattern output a, channel 0. 0 0 mcoa0 passive. 1 internal mcoa0. 1 ccpb0 communication pattern output b, channel 0. 0 0 mcob0 passive. 1 mcob0 tracks internal mcoa0. 2 ccpa1 communication pattern output a, channel 1. 0 0 mcoa1 passive. 1 mcoa1 tracks internal mcoa0. 3 ccpb1 communication pattern output b, channel 1. 0 0 mcob1 passive. 1 mcob1 tracks internal mcoa0. 4 ccpa2 communication pattern output a, channel 2. 0 0 mcoa2 passive. 1 mcoa2 tracks internal mcoa0. 5 ccpb2 communication pattern output b, channel 2. 0 0 mcob2 passive. 1 mcob2 tracks internal mcoa0. 31:6 - reserved.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 734 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.9 mcpwm interrupt registers the motor control pwm module includes the following interrupt sources: 8.9.1 mcpwm interrupt enable read address the inten register controls which of the mc pwm interrupts are enabl ed. this address is read-only, but the underlying register can be modified by writing to addresses inten_set and inten_clr. table 581. mcpwm capture read addresses (cap[0:2] - 0x400b 8044 (cap0), 0x400b 8048 (cap1), 0x400b 804c (cap2)) bit description bit symbol description reset value 31:0 cap current tc value at a capture event. 0x0000 0000 table 582. motor control pwm interrupts symbol description ilim0/1/2 limit interrupts for channels 0, 1, 2. imat0/1/2 match interrupts for channels 0, 1, 2. icap0/1/2 capture interrupts for channels 0, 1, 2. abort fast abort interrupt table 583. mcpwm interrupt enable read address (inten - 0x400b 8050) bit description bit symbol value description reset value 0 ilim0 limit interrupt for channel 0. 0 0 interrupt disabled. 1 interrupt enabled. 1 imat0 match interrupt for channel 0. 0 0 interrupt disabled. 1 interrupt enabled. 2 icap0 capture interrupt for channel 0. 0 0 interrupt disabled. 1 interrupt enabled. 3- reserved. - 4 ilim1 limit interrupt for channel 1. 0 0 interrupt disabled. 1 interrupt enabled. 5 imat1 match interrupt for channel 1. 0 0 interrupt disabled. 1 interrupt enabled. 6 icap1 capture interrupt for channel 1. 0 0 interrupt disabled. 1 interrupt enabled. 7- reserved. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 735 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.9.2 mcpwm interrupt enable set address writing ones to this write-only address sets the corresponding bits in inten, thus enabling interrupts. 27.8.9.3 mcpwm interrupt enable clear address writing ones to this write-only address clears the corresponding bits in inten, thus disabling interrupts. 8 ilim2 limit interrupt for channel 2. 0 0 interrupt disabled. 1 interrupt enabled. 9 imat2 match interrupt for channel 2. 0 0 interrupt disabled. 1 interrupt enabled. 10 icap2 capture interrupt for channel 2. 0 0 interrupt disabled. 1 interrupt enabled. 14:11 - reserved. - 15 abort fast abort interrupt. 0 0 interrupt disabled. 1 interrupt enabled. 31:16 - reserved. - table 583. mcpwm interrupt enable read address (inten - 0x400b 8050) bit description bit symbol value description reset value table 584. mcpwm interrupt enable set register (inten_set - address 0x400b 8054) bit description bit symbol description reset value 0 ilim0_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 1 imat0_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 2 icap0_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 3- reserved. - 4 ilim1_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 5 imat1_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 6 icap1_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 7- reserved. - 9 ilim2_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 10 imat2_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 11 icap2_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 14:12 - reserved. - 15 abort_set writing a one sets the corresponding bit in inten, thus enabling the interrupt. - 31:16 - reserved. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 736 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.10 mcpwm count control register 27.8.10.1 mcpwm count control read address the cntcon register controls whether t he mcpwm channels are in timer or counter mode, and in coun ter mode whether the coun ter advances on rising and/or falling edges on any or all of the three mci inputs. if timer mode is selected, the counter advances based on the pclk clock. this address is read-only. to set or cl ear the register bits, write ones to the cntcon_set or cntcon_clr address. table 585. pwm interrupt enable clear register (inten_clr - address 0x400b 8058) bit description bit symbol description reset value 0 ilim0_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 1 imat0_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 2 icap0_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 3- reserved. - 4 ilim1_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 5 imat1_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 6 icap1_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 7- reserved. - 8 ilim2_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 9 imat2_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 10 icap2_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 14:11 - reserved. - 15 abort_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 31:16 - reserved. - table 586. mcpwm count control read address (cntcon - 0x400b 805c) bit description bit symbol value description reset value 0 tc0mci0_re counter 0 rising edge mode, channel 0. 0 0 a rising edge on mci0 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a rising edge on mci0. 1 tc0mci0_fe counter 0 falling edge mode, channel 0. 0 0 a falling edge on mci0 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a falling edge on mci0. 2 tc0mci1_re counter 0 rising edge mode, channel 1. 0 0 a rising edge on mci1 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a rising edge on mci1. 3 tc0mci1_fe counter 0 falling edge mode, channel 1. 0 0 a falling edge on mci1 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a falling edge on mci1.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 737 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 4 tc0mci2_re counter 0 rising edge mode, channel 2. 0 0 a rising edge on mci0 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a rising edge on mci2. 5 tc0mci2_fe counter 0 falling edge mode, channel 2. 0 0 a falling edge on mci0 does not affect counter 0. 1 if mode0 is 1, counter 0 advances on a falling edge on mci2. 6 tc1mci0_re counter 1 rising edge mode, channel 0. 0 0 a rising edge on mci0 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a rising edge on mci0. 7 tc1mci0_fe counter 1 falling edge mode, channel 0. 0 0 a falling edge on mci0 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a falling edge on mci0. 8 tc1mci1_re counter 1 rising edge mode, channel 1. 0 0 a rising edge on mci1 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a rising edge on mci1. 9 tc1mci1_fe counter 1 falling edge mode, channel 1. 0 0 a falling edge on mci0 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a falling edge on mci1. 10 tc1mci2_re counter 1 rising edge mode, channel 2. 0 0 a rising edge on mci2 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a rising edge on mci2. 11 tc1mci2_fe counter 1 falling edge mode, channel 2. 0 0 a falling edge on mci2 does not affect counter 1. 1 if mode1 is 1, counter 1 advances on a falling edge on mci2. 12 tc2mci0_re counter 2 rising edge mode, channel 0. 0 0 a rising edge on mci0 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a rising edge on mci0. 13 tc2mci0_fe counter 2 falling edge mode, channel 0. 0 0 a falling edge on mci0 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a falling edge on mci0. 14 tc2mci1_re counter 2 rising edge mode, channel 1. 0 0 a rising edge on mci1 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a rising edge on mci1. 15 tc2mci1_fe counter 2 falling edge mode, channel 1. 0 0 a falling edge on mci1 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a falling edge on mci1. 16 tc2mci2_re counter 2 rising edge mode, channel 2. 0 0 a rising edge on mci2 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a rising edge on mci2. table 586. mcpwm count control read address (cntcon - 0x400b 805c) bit description bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 738 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.10.2 mcpwm count control set address writing ones to this write-only address sets the corresponding bits in cntcon. 17 tc2mci2_fe counter 2 falling edge mode, channel 2. 0 0 a falling edge on mci2 does not affect counter 2. 1 if mode2 is 1, counter 2 advances on a falling edge on mci2. 28:18 - - reserved. - 29 cntr0 channel 0 counter/timer mode. 0 0 channel 0 is in timer mode. 1 channel 0 is in counter mode. 30 cntr1 channel 1 counter/timer mode. 0 0 channel 1 is in timer mode. 1 channel 1 is in counter mode. 31 cntr2 channel 2 counter/timer mode. 0 0 channel 2 is in timer mode. 1 channel 2 is in counter mode. table 586. mcpwm count control read address (cntcon - 0x400b 805c) bit description bit symbol value description reset value table 587. mcpwm count control set address (cntcon_set - 0x400b 8060) bit description bit symbol description reset value 0 tc0mci0_re_set writing a one sets the corresponding bit in the cntcon register. - 1 tc0mci0_fe_set writing a one sets the corresponding bit in the cntcon register. - 2 tc0mci1_re_set writing a one sets the corresponding bit in the cntcon register. - 3 tc0mci1_fe_set writing a one sets the corresponding bit in the cntcon register. - 4 tc0mci2_re_set writing a one sets the corresponding bit in the cntcon register. - 5 tc0mci2_fe_set writing a one sets the corresponding bit in the cntcon register. - 6 tc1mci0_re_set writing a one sets the corresponding bit in the cntcon register. - 7 tc1mci0_fe_set writing a one sets the corresponding bit in the cntcon register. - 8 tc1mci1_re_set writing a one sets the corresponding bit in the cntcon register. - 9 tc1mci1_fe_set writing a one sets the corresponding bit in the cntcon register. - 10 tc1mci2_re_set writing a one sets the corresponding bit in the cntcon register. - 11 tc1mci2_fe_set writing a one sets the corresponding bit in the cntcon register. - 12 tc2mci0_re_set writing a one sets the corresponding bit in the cntcon register. - 13 tc2mci0_fe_set writing a one sets the corresponding bit in the cntcon register. - 14 tc2mci1_re_set writing a one sets the corresponding bit in the cntcon register. - 15 tc2mci1_fe_set writing a one sets the corresponding bit in the cntcon register. - 16 tc2mci2_re_set writing a one sets the corresponding bit in the cntcon register. - 17 tc2mci2_fe_set writing a one sets the corresponding bit in the cntcon register. - 28:18 - reserved.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 739 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.10.3 mcpwm count control clear address writing ones to this write-only address clears the corresponding bits in cntcon. 27.8.11 mcpwm interrupt flag registers 27.8.11.1 mcpwm interrupt flags read address the intf register includes all mcpwm interrupt flags, which are set when the corresponding hardware event occurs, or when ones are written to the intf_set address. when corresponding bits in this register and inten are both 1, the mcpwm asserts its interrupt request to the interrupt controller module. this address is read-only, but the bits in the underlying register can be modified by writing ones to addresses intf_set and intf_clr. 29 cntr0_set writing a one sets the corresponding bit in the cntcon register. - 30 cntr1_set writing a one sets the corresponding bit in the cntcon register. - 31 cntr2_set writing a one sets the corresponding bit in the cntcon register. - table 587. mcpwm count control set address (cntcon_set - 0x400b 8060) bit description bit symbol description reset value table 588. mcpwm count control clear address (cntcon_clr - 0x400b 8064) bit description bit symbol description reset value 0 tc0mci0_re_clr writing a one clears the corresponding bit in the cntcon register. - 1 tc0mci0_fe_clr writing a one clears the corresponding bit in the cntcon register. - 2 tc0mci1_re_clr writing a one clears the corresponding bit in the cntcon register. - 3 tc0mci1_fe_clr writing a one clears the corresponding bit in the cntcon register. - 4 tc0mci2_re writing a one clears the corresponding bit in the cntcon register. - 5 tc0mci2_fe_clr writing a one clears the corresponding bit in the cntcon register. - 6 tc1mci0_re_clr writing a one clears the corresponding bit in the cntcon register. - 7 tc1mci0_fe_clr writing a one clears the corresponding bit in the cntcon register. - 8 tc1mci1_re_clr writing a one clears the corresponding bit in the cntcon register. - 9 tc1mci1_fe_clr writing a one clears the corresponding bit in the cntcon register. - 10 tc1mci2_re_clr writing a one clears the corresponding bit in the cntcon register. - 11 tc1mci2_fe_clr writing a one clears the corresponding bit in the cntcon register. - 12 tc2mci0_re_clr writing a one clears the corresponding bit in the cntcon register. - 13 tc2mci0_fe_clr writing a one clears the corresponding bit in the cntcon register. - 14 tc2mci1_re_clr writing a one clears the corresponding bit in the cntcon register. - 15 tc2mci1_fe_clr writing a one clears the corresponding bit in the cntcon register. - 16 tc2mci2_re_clr writing a one clears the corresponding bit in the cntcon register. - 17 tc2mci2_fe_clr writing a one clears the corresponding bit in the cntcon register. - 28:18 - reserved. 29 cntr0_clr writing a one clears the corresponding bit in the cntcon register. - 30 cntr1_clr writing a one clears the corresponding bit in the cntcon register. - 31 cntr2_clr writing a one clears the corresponding bit in the cntcon register. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 740 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm table 589. mcpwm interrupt flags read address (intf - 0x400b 8068) bit description bit symbol value description reset value 0 ilim0_f limit interrupt flag for channel 0. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 1 imat0_f match interrupt flag for channel 0. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 2 icap0_f capture interrupt flag for channel 0. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 3 - reserved. - 4 ilim1_f limit interrupt flag for channel 1. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 5 imat1_f match interrupt flag for channel 1. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 6 icap1_f capture interrupt flag for channel 1. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 7 - reserved. - 8 ilim2_f limit interrupt flag for channel 2. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 9 imat2_f match interrupt flag for channel 2. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 10 icap2_f capture interrupt flag for channel 2. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 14:11 - reserved. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 741 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.11.2 mcpwm interrupt flags set address writing ones to this write-only address sets the corresponding bits in intf, thus possibly simulating hardware interrupts. 27.8.11.3 mcpwm interrupt flags clear address writing ones to this write-only address sets the corresponding bits in intf, thus clearing the corresponding interrupt requests. this is typically done in interr upt service routines. 15 abort_f fast abort interrupt flag. 0 0 this interrupt source is not contributing to the mcpwm interrupt request. 1 if the corresponding bit in inten is 1, the mcpwm module is asserting its interrupt request to the interrupt controller. 31:16 - reserved. - table 589. mcpwm interrupt flags read address (intf - 0x400b 8068) bit description bit symbol value description reset value table 590. mcpwm interrupt flags set address (intf_set - 0x400b 806c) bit description bit symbol description reset value 0 ilim0_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 1 imat0_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 2 icap0_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 3 - reserved. - 4 ilim1_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 5 imat1_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 6 icap1_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 7 - reserved. - 8 ilim2_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 9 imat2_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 10 icap2_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 14:11 - reserved. - 15 abort_f_set writing a one sets the corresponding bit in the intf register, thus possibly simulating hardware interrupt. - 31:16 - reserved. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 742 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.8.12 mcpwm capture clear address writing ones to this write-only addre ss clears the selected cap registers. table 591. mcpwm interrupt flags clear address (intf_clr - 0x400b 8070) bit description bit symbol description reset value 0 ilim0_f_clr writing a one clears the corresponding bit in the intf register, thus clearing the corresponding interrupt request. - 1 imat0_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 2 icap0_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 3- reserved. - 4 ilim1_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 5 imat1_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 6 icap1_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 7- reserved. - 8 ilim2_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 9 imat2_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 10 icap2_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 14:11 - writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 15 abort_f_clr writing a one clears the corresponding bit in inten, thus disabling the interrupt. - 31:16 - reserved. - table 592. mcpwm capture clear address (cap_clr - 0x400b 8074) bit description bit symbol description 0 cap_clr0 writing a 1 to this bit clears the cap0 register. 1 cap_clr1 writing a 1 to this bit clears the cap1 register. 2 cap_clr2 writing a 1 to this bit clears the cap2 register. 31:3 - reserved
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 743 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.9 pwm operation 27.9.1 pulse-width modulation each channel of the mcpwm has two outputs, a and b, that can drive a pair of transistors to switch a controlled point between two power rails. most of the time the two outputs have opposite polarity, but a dead-time feature can be enabled (on a per-channel basis) to delay both signals? transitions from ?passive? to ?active? state so that the transistors are never both turned on simultaneously. in a more general view, the states of each output pair can be thought of ?high?, ?low?, and ?f loating? or ?up?, ?down?, and ?center-off?. each channel?s mapping from ?active? and ?pa ssive? to ?high? and ?low? is programmable. after reset, the three a outputs are passive/low, and the b outputs are active/high. the mcpwm can perform edge-aligned and center-aligned pulse-width modulation. note: in timer mode, the period of a channel?s modulated mc_a and mc_b outputs is de- termined by its limit register, and the pulse wi dth at the start of the period is determined by its match register. if it suits your way of thinki ng, consider the limit register to be the ?period register? and the match register to be the ?pulse width register?. edge-aligned pwm without dead-time in this mode the timer tc counts up from 0 to the value in the lim register. as shown in figure 146 , the output pin state is ?a passive? unt il the tc matches the match register, at which point it changes to ?a active?. when the tc matches the limit register, the output pin state changes back to ?a passive?, and the tc is reset and starts counting up again. center-aligned pwm without dead-time in this mode the timer tc counts up from 0 to the value in the lim register, then counts back down to 0 and repeats. as shown in figure 147 , while the timer counts up, the output pin state is ?a passive? until the tc matches the match register, at which point it changes to ?a active?. when the tc matches the limi t register it starts counting down. when the tc matches the match register on the way down, the output pin state changes back to ?a passive?. fig 146. edge-aligned pwm waveform without dead time, pola = 0 mat mat lim lim 0 pola = 0 timer reset timer reset mcoa mcob active active passive passive passive passive active active
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 744 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm dead-time counter when the a channel?s dte bit is set in mccon, the dead-time counter delays the passive-to-active transitions of both output pins. the dead-time counter starts counting down, from the channel?s dt value (in the mcdt register) to 0, whenever the channel?s a or b output changes from active to passive. th e transition of the other output from passive to active is delayed until the dead-time co unter reaches 0. during the dead time, the mc_a and mc_b output levels are both passive. figure 148 shows operation in edge aligned mode with dead time, and figure 149 shows center-aligned operation with dead time. fig 147. center-aligned pwm waveform without dead time, pola = 0 fig 148. edge-aligned pwm waveform with dead time, pola = 0 mat mat lim lim 0 0 pola = 0 mcoa mcob active active passive passive passive passive active active mat mat lim lim 0 pola = 0 timer reset timer reset mcoa mcob active active passive passive passive passive active active dt dt dt dt
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 745 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.9.2 shadow registers and simultaneous updates the limit, match, and commutation pattern registers (mclim, mcmat, and mccp) are implemented as register pairs, each consisti ng of a write register and an operational register. software writes into the write regi sters. the operational registers control the actual operation of each channel and are loaded with the current value in the write registers when the tc starts counting up from 0. updating of the functional registers can be di sabled by setting a channel?s disup bit in the mccon register. if the disup bits are se t, the functional registers are not updated until software stops the channel. if a channel is not running when software writes to its lim or mat register, the functional register is updated immediately. software can write to a tc register only when its channel is stopped. 27.9.3 fast abort (abort) the mcpwm has an external input mc_abort . when this input goes low, all six output pins assume their ?a passive? states, and the abort interrupt is generated if enabled. the outputs remain locked in ?a passive? state until the abort interrupt flag is cleared or the abort interrupt is disabled. the abort flag may not be cleared before the mc_abort input goes high. in order to clear an abort flag, a 1 must be written to bit 15 of the mcintf_clr register. this will remove the interrupt re quest. the interrupt can also be disabled by writing a 1 to bit 15 of the mcinten_clr register. 27.9.4 capture events each pwm channel can take a snapshot of its tc when an input signal transitions. any channel may use any combination of rising and/or falling edges on any or all of the mc_fb0-2 inputs as a capture event, under co ntrol of the mccapcon register. rising or falling edges on the inputs are detected synchro nously with respect to pclk. fig 149. center-aligned waveform with dead time, pola = 0 mat mat lim lim 0 0 pola = 0 mcoa mcob active active passive passive passive passive active active dt dt dt
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 746 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm if a channel?s hnf bit in the mccapcon regist er is set to enable ?noise filtering?, a selected edge on an mc_fb pin starts the dead-time counter for that channel, and the capture event actions described below are de layed until the dead-time counter reaches 0. this function is targeted specifically fo r performing three-phase brushless dc motor control with hall sensors. a capture event on a channel (possibly delayed by hnf) causes the following: ? the current value of the tc is stored in the capture register (cap). ? if the channel?s capture event interrupt is enabled (see ta b l e 5 8 3 ), the capture event interrupt flag is set. ? if the channel?s rt bit is set in the mccapcon register, enabling reset on a capture event, the input event has the same effect as matching the channel?s tc to its lim register. this includes resetting the tc and switching the output pins in edge-aligned mode as described in 27.8.4 and 27.9.1 . 27.9.5 external event c ounting (counter mode) if a channel?s mode bit is 1 in mccntcon, its tc is incremented by rising and/or falling edges (synchronously detected) on the mc_fb0-2 inputs, rather than by pclk. the pwm functions and capture functions are unaffected. 27.9.6 three-phase dc mode the three-phase dc mode is selected by setting the dcmode bit in the mccon register. in this mode, the internal mc_0a signal can be routed to any or all of the output pins. each output pin is masked by a bit in the current commutation pattern register mccp. if a bit in the mccp register is 0, its output pin has the logic level for the passive state of output mc_0a. the polarity of the off state is determined by the pola0 bit. all output pins that have 1 bits in the mccp register are controlled by the internal mc_0a signal. the three mc_b output pins are inverted when the invbdc bit is 1 in the mccon register. this feature accommodates bridge-dri vers that have active-low inputs for the low-side switches. the mccp register is implemented as a shad ow register pair, so that changes to the active commutation pattern occur at the beginning of a new pwm cycle. see 27.8.4 and 27.9.2 for more about writing and reading such registers. figure 150 shows sample waveforms of the output pins in three-phase dc mode. bits 1 and 3 in the mccp register (corresponding to outputs mc_1b and mc_0b) are set to 0 so that these outputs are masked and in the off state. their logic level is determined by the pola0 bit (here, pola0 = 0 so the passive state is logic low). the invbdc bit is set to 0 (logic level not inverted) so that the b output have the same polarity as the a outputs. note that this mode differs from othe r modes in that the mc_b outputs are not the opposite of the mc_a outputs. in the situation shown in figure 150 , bits 0, 2, 4, and 5 in the mccp register are set to 1. that means that mc_1a and both output pins for channel 2 follow the mc_0a signal.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 747 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.9.7 three phase ac mode the three-phase ac-mode is se lected by setting the acmode bit in the mccon register. in this mode, the value of channel 0?s tc is routed to all channels for comparison with their mat registers. (the lim1 -2 registers are not used.) each channel controls its output pins by comparing its mat value to tc0. figure 151 shows sample waveforms for the six out put pins in three-phase ac mode. the pola bits are set to 0 for all three channels, so that for all output pins the active levels are high and the passive levels are low. each channel has a different mat value which is compared to the mctc0 value. in this mode the period value is identical for all three channels and is determined by mclim0. the dead-time mode is disabled. fig 150. three-phase dc mode sample waveforms pola0 = 0, invbdc = 0 mcoa2 mcob1 mcoa1 mcob0 mcoa0 mcob2 ccpb1 = 0, off-state ccpb0 = 0, off-state ccpa0 = 1, on-state ccpa2 = 1, on-state ccpa1 = 1, on-state ccpb2 = 1, on-state
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 748 of 942 nxp semiconductors UM10562 chapter 27: lpc408x/407x motor control pwm 27.9.8 interrupts the mcpwm includes 10 possible interrupt sources: ? when any channel?s tc matches its match register. ? when any channel?s tc matches its limit register. ? when any channel captures the value of its tc into its capture register, because a selected edge occurs on any of mc_fb0-2. ? when all three channels? outputs are forced to ?a passive? state because the mc_abort pin goes low. section 27.8.9 ? mcpwm interrupt registers ? explains how to enable these interrupts, and section 27.8.2 ? pwm capture control register ? describes how to map edges on the mc_fb0-2 inputs to ?capture events? on the three channels. fig 151. three-phase ac mode sample waveforms, edge aligned pwm mode pola0 = 0 pola2 = 0 pola1 = 0 mcoa2 mcob1 mcoa1 mcob0 mcoa0 mcob2 mat0 mat1 mat1 mat2 mat2 lim0 lim0 0 timer reset timer reset
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 749 of 942 28.1 how to read this chapter the qei is available on most lpc408x/407x devices, see section 1.4 for details. 28.2 basic configuration the qei is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcqei. remark: on reset, the qei is disabled (pcqei = 0). 2. peripheral clock: the qei operates from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . 3. pins: select qei pins through and pin modes for port pins with qei functions through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: see section 28.7.4 . the qei interrupt is enabled in the nvic using the appropriate interrupt set enable register. 28.3 features this quadrature encoder interface (qei) has the following features: ? tracks encoder position. ? increments/ decrements depending on direction. ? programmable for 2x or 4x position counting. ? velocity capture using built-in timer. ? velocity compare function with less than interrupt. ? uses 32-bit registers for position and velocity. ? three position compare registers with interrupts. ? index counter for revolution counting. ? index compare register with interrupts. ? can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. ? digital filter with programmable delays for encoder input signals. ? can accept decoded signal inputs (clock and direction). UM10562 chapter 28: lpc408x/407x qu adrature encoder interface (qei) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 750 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.4 introduction a quadrature encoder, also know n as a 2-channel incremental encoder, converts angular displacement into two pulse signals. by mo nitoring both the number of pulses and the relative phase of the two signals, position, direction of rotation, and velocity can be tracked. in addition, a third channel, or index signal, can be used to reset the position counter. this quadrature encoder interfac e module decodes the digital pulses from a quadrature encoder wheel to integrate positi on over time and determine direction of rotation. in addition, it can captur e the velocity of the encoder wheel. fig 152.encoder interface block diagram 100517 maxpos_int rev1_int rev0_int rev2_int pos1_int pos0_int pos2_int pos0rev_int pos1rev_int pos2rev_int position compare maxpos compare position counter index counter index compare velocity capture veclocity compare velc_int velocity counter velocity timer tim_int velocity reload inx_int err_int dir_int enclk_int windowing digital filter quadrature decoder overflow load reset load reset clock clock clock clock pulse index pulse dir qei_idx (mc_fb2) qei_phb (mc_fb1) qei_pha (mc_fb0)
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 751 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.5 functional description the qei module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture the velocity of the encoder wheel. 28.5.1 input signals the qei module supports two modes of sign al operation: quadrature phase mode and clock/direction mode. in quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relation ship is used to determine the direction of rotation. in clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation.). this mode is determined by the sigmode bit of the qei configuration register (qeiconf) register (see table 599 ). when the sigmode bit = 1, the quadrature decoder is bypassed and the pha pin functions as the direction signal and phb pin functions as the clock signal for the counters, etc. when the sigmode bit = 0, the pha pin and phb pins are decoded by the quadrature decoder. in this mode the quadrature decoder produces the direction and clock signals for the counters, etc. in both modes the direction signal is subject to the effects of the directio n invert (dirinv) bit. 28.5.1.1 quadrature input signals when edges on pha lead edges on phb, the position counter is incremented. when edges on phb lead edges on pha, the position counter is decremented. when a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. [1] all other state transitions are illegal and should set the err bit. table 593. encoder states phase a phase b state 101 112 013 004 table 594. encoder state transitions [1] from state to state direction 1 2 positive 23 34 41 4 3 negative 32 21 14
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 752 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) interchanging of the pha and phb input signals are compensated by complementing the dir bit. when set = 1, the direction inversion bit (dirinv) complements the dir bit. figure 153 shows how quadrature encoder signals equate to direction and count. 28.5.1.2 digital input filtering all three encoder inputs (pha, phb, and index) require digital filtering. the number of sample clocks is user programmable from 1 to 4,294,967,295 (0xffff ffff). in order for a transition to be accepted, the input signal must remain in new state for the programmed number of sample clocks. 28.5.2 position capture the capture mode for the position integrator can be set to update the position counter on every edge of the pha signal or to update on every edge of both pha and phb. updating the position counter on every pha and phb provid es more positional resolution at the cost of less range in the positional counter. the position integrator and velocity captur e can be independently enabled. alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. the position counter is automatically reset on one of three conditions. incrementing past the maximum position value (q eimaxpos) will reset the posi tion counter to zero. if the reset on index bit (respi) is set, sensing the index pulse for the first time will once reset the position counter to zero after the next positional increase (calibrate). if the continuously reset on in dex bit (crespi) is se t, sensing the index pul se will continuously reset the position counter to zero after the next positional increase (recalibrate). table 595. encoder direction dir bit dirinv bit direction 00f o r w a r d 10r e v e r s e 01r e v e r s e 11f o r w a r d fig 153.quadrature encoder basic operation pha phb direction position -1 -1 -1 -1 -1-1 -1 -1 -1 -1-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 753 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.5.3 velocity capture the velocity capture has a programmable timer and a capture register. it counts the number of phase edges (using the same confi guration as for the position integrator) in a given time period. when the velocity time r (qeitime) overflows the contents of the velocity counter (qeivel) are transferred to the capture (qeicap) register. the velocity counter is then cleared. the velocity timer is loaded with the contents of the velocity reload register (qeiload). finally, the velo city interrupt (tim_i nt) is asserted. the number of edges counted in a given time period is directly proportional to the velocity of the encoder. note that the ve locity counter counts up regardless of the direction of rotation, and whether the direction changes. setting the reset velocity bi t (resv) will clear the velocity counter, reset the velocity capture register to 0xffff ffff, load the velocity timer with the contents of the velocity reload register (qeiload). the following equation converts the velocity counter value into an rpm value: rpm = (pclk * qeicap * 60) (qeiload * ppr * edges) where: ? pclk is the peripheral clock rate for the qei block. see section 3.3.3.5 for more on the possibilities for pclk). ? qeicap is the captured velocity counter valu e for the last velocity timer period. ? qeiload is the velocity timer reload value. ? ppr is the number of pulses per revolution of the physical encoder used in the application ? edges is 2 or 4, based on the capture mode set in the qeicon register (2 for capmode set to 0 and 4 for capmode set to 1) for example, consider a motor running at 600 rpm. a 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution (ppr * edges). this results in 81,920 pulses per second (the motor turns 10 times per second at 600 rpm and there are 8192 edges per revolution). if the timer were clocked at 10,000 hz, and the qeiload was 2,500 (corresponding to ? of a second), it would count 20,480 pulses per update. using the above equation: rpm = (10000 * 1 * 20480 * 60) (2500 * 2048 * 4) = 600 rpm now, consider that the motor is sped up to 3000 rpm. this results in 409,600 pulses per second, or 102,400 every ? of a sec ond. again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) (2500 * 2048 * 4) = 3000 rpm these are simple examples, real-world values will have a higher rate for pclk, and probably a larger value for qeiload as well. 28.5.4 velocity compare in addition to velocity capture, the velocity measurement system includes a programmable velocity compare register. after every velocity capture event the contents of the velocity capture register (qeicap) is compared with the contents of the velocity
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 754 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) compare register (velcomp). if the captured velocity is less than the compare value, an interrupt is asserted provided th at the velocity compare interrupt enable bit is set. this can be used to determine if a motor shaft is either stalled or moving too slow. 28.6 pin description [1] the quadrature encoder interface uses the same pin functions as the motor control pwm feedback inputs. if used as part of motor control, the qei can be used as an alternative to feedback directly to the mcpwm. table 596. qei pin description pin name i/o description mc_fb0 [1] i used as the phase a (pha) input to the quadrature encoder interface. mc_fb1 [1] i used as the phase b (phb) input to the quadrature encoder interface. mc_fb2 [1] i used as the index (idx) input to the quadrature encoder interface.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 755 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7 register description 28.7.1 register summary table 597. register overview: qei (base address 0x400b c000) symbol access address description reset value table control registers con wo 0x000 control register na 598 conf r/w 0x008 configuration register 0 599 stat ro 0x004 status register 0 600 position, index, and timer registers pos ro 0x00c position register 0 601 maxpos r/w 0x010 maximum position register 0 602 cmpos0 r/w 0x014 position compare register 0 0xffff ffff 603 cmpos1 r/w 0x018 position compare register 1 0xffff ffff 604 cmpos2 r/w 0x01c position compare register 2 0xffff ffff 605 inxcnt ro 0x020 index count register 0 0 606 inxcmp0 r/w 0x024 index compare register 0 0xffff ffff 607 inxcmp1 r/w 0x04c index compare register 1 0xffff ffff 617 inxcmp2 r/w 0x050 index compare register 2 0xffff ffff 618 load r/w 0x028 velocity timer reload register 0 608 time ro 0x02c velocity timer register 0 609 vel ro 0x030 velocity counter register 0 610 cap ro 0x034 velocity capture register 0xffff ffff 611 velcomp r/w 0x038 velocity compare register 0 612 filterpha r/w 0x03c digital filter register on pha 0 613 filterphb r/w 0x040 digital filter register on phb 0 614 filterinx r/w 0x044 digital filter register on idx 0 615 window r/w 0x048 index acceptance window register 0xf 616 interrupt registers intstat ro 0xfe0 interrupt status register 0 619 set wo 0xfec interrupt status set register na 620 clr wo 0xfe8 interrupt status clear register na 621 ie ro 0xfe4 interrupt enable register 0 622 ies wo 0xfdc interrupt enable set register na 623 iec wo 0xfd8 interrupt enable clear register na 624
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 756 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.2 control registers 28.7.2.1 qei control register this register contains bits which control the operation of the position and velocity counters of the qei module. 28.7.2.2 qei configuration register this register contains the configuration of the qei module. 28.7.2.3 qei status register this register provides the st atus of the encoder interface. table 598: qei control register (con - address 0x400b c000) bit description bit symbol description 0 resp reset position counter. when 1 is written, resets the position counter to all zeros. 1 respi reset position counter on index. when 1 is written, resets the position counter to all zeros once only the first time an index pulse occurs. 2 resv reset velocity. when 1 is written, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. 3 resi reset index counter. when 1 is written, resets the index counter to all zeros. 31:4 - reserved. read value is undefined, only zero should be written. table 599: qei configuration register (conf - address 0x400b c008) bit description bit symbol description reset value 0 dirinv direction invert. when 1, complements the dir bit. 0 1 sigmode signal mode. when 0, pha and phb function as quadrature encoder inputs. when 1, pha functions as the direction signal and phb functions as the clock signal. 0 2 capmode capture mode. when 0, only pha edges are counted (2x). when 1, both pha and phb edges are counted (4x), increasing resolution but decreasing range. 0 3 invinx invert index. when 1, inverts the sense of the index input. 0 4 crespi continuously reset the position counter on index. when 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration). 0 15:5 - reserved. read value is undefined, only zero should be written. na 19:16 inxgate index gating configuration: when inxgate[16] = 1, pass the index when pha = 1 and phb = 0, otherwise block index. when inxgate[17] = 1, pass the index when pha = 1 and phb = 1, otherwise block index. when inxgate[18] = 1, pass the index when pha = 0 and phb = 1, otherwise block index. when inxgate[19] = 1, pass the index when pha = 0 and phb = 0, otherwise block index. 0xf 31:20 - reserved. read value is undefined, only zero should be written. na table 600: qei status register (stat - address 0x400b c004) bit description bit symbol description reset value 0 dir direction bit. in combination with dirinv bit indicates forward or reverse direction. see ta b l e 5 9 5 . 0 31:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 757 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.3 position, index and timer registers 28.7.3.1 qei position register this register contains the current value of th e encoder position. increments or decrements when encoder counts occur, depending on the direction of rotation. 28.7.3.2 qei maximum position register this register contains the maximum value of the encoder position. in forward rotation the position register resets to zero when the pos ition register exceeds this value. in reverse rotation the position register resets to th is value when the position register decrements from zero. 28.7.3.3 qei position compare register 0 this register contains a position compare value. this value is compared against the current value of the position register. an interrupt can be generated when the compare value is equal to the current value of the position register. the compare value must take into account the fact that the starting position is zero. 28.7.3.4 qei position compare register 1 this register contains a position compare value. this value is compared against the current value of the position register. an interrupt can be generated when the compare value is equal to the current value of the position register. the compare value must take into account the fact that the starting position is zero. table 601: qei position register (pos - address 0x400b c00c) bit description bit symbol description reset value 31:0 pos current position value. 0 table 602: qei maximum position register (maxpos - address 0x400b c010) bit description bit symbol description reset value 31:0 maxpos current maximum position value. 0 table 603: qei position compare register 0 (cmpos0 - address 0x400b c014) bit description bit symbol description reset value 31:0 pcmp0 position compare value 0. 0 table 604: qei position compare register 1 (cmpos1 - address 0x400b c018) bit description bit symbol description reset value 31:0 pcmp1 position compare value 1. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 758 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.3.5 qei position compare register 2 this register contains a position compare value. this value is compared against the current value of the position register. an interrupt can be generated when the compare value is equal to the current value of the position register. the compare value must take into account the fact that the starting position is zero. 28.7.3.6 qei index count register this register contains the current value of the index counter. it is updated when an index count occurs. this can be an increment when the position counter overflows the maxpos value or a decrement when the position counter underflows zero, depending on the direction of rotation. in ca se (re)calibration occurs due to an index pulse, the over/underflow is forced internally. 28.7.3.7 qei index compare register 0 this register contains an index compare value. this value is compared against the current value of the index count register. interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. 28.7.3.8 qei velocity timer reload register this register contains the reload value of the velocity timer. when the timer (qeitime) overflows or the resv bit is asserted, this value is loaded into the timer (qeitime). 28.7.3.9 qei velocity timer register this register contains the current value of the velocity timer. when this timer overflows the value of velocity counter (qeivel) is stored in the velocity capture register (qeicap), the velocity counter is reset to zero, the timer is reloaded with the value stored in the velocity reload register (qeiload), and the velo city interrupt (tim_int) is asserted. table 605: qei position compare register 2 (cmpos2 - address 0x400b c01c) bit description bit symbol description reset value 31:0 pcmp2 position compare value 2. 0 table 606: qei index count register (inxcnt - address 0x400b c020) bit description bit symbol description reset value 31:0 encpos current index counter value. 0 table 607: qei index compare register 0 (inxcmp0 - address 0x400b c024) bit description bit symbol description reset value 31:0 icmp0 index compare value 0. 0 table 608: qei timer load register (load - address 0x400b c028) bit description bit symbol description reset value 31:0 velload current velocity timer load value. 0 table 609: qei timer register (time - address 0x400b c02c) bit description bit symbol description reset value 31:0 velval current velocity timer value. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 759 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.3.10 qei velocity register this register contains the running count of velocity pulses for the current time period. when the velocity timer (qeitime) overflows the contents of this register is captured in the velocity capture register (qeicap). after capture, this register is set to zero. this register is also reset when the ve locity reset bit (resv) is asserted. 28.7.3.11 qei velocity capture register this register contains the most recently measured velocity of the encoder. this corresponds to the number of velocity puls es counted in the previous velocity timer period.the current velocity co unt is latched into this register when the velocity timer overflows. 28.7.3.12 qei velocity compare register this register contains a velocity compare value. this value is compared against the captured velocity in the velocity capture regi ster. if the capture velocity is less than the value in this compare register, a velocity comp are interrupt (velc_int) will be asserted, if enabled. 28.7.3.13 qei digital filter on pha this register contains the sampling count for the digital filter. a sampling count of zero bypasses the filter. 28.7.3.14 qei digital filter on phb this register contains the sampling count for the digital filter. a sampling count of zero bypasses the filter. table 610: qei velocity register (vel - address 0x400b c030) bit description bit symbol description reset value 31:0 velpc current velocity pulse count. 0 table 611: qei velocity capture register (cap - address 0x400b c034) bit description bit symbol description reset value 31:0 velcap last velocity capture. 0 table 612: qei velocity compare register (velcomp - address 0x400b c038) bit description bit symbol description reset value 31:0 velpc compare velocity pulse count. 0 table 613: qei digital filter on pha (filterpha - address 0x400b c03c) bit description bit symbol description reset value 31:0 filta digital filter sampling delay for pha. 0 table 614: qei digital filter on phb (filterphb - address 0x400b c040) bit description bit symbol description reset value 31:0 filtb digital filter sampling delay for phb. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 760 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.3.15 qei digital filter on inx this register contains the sampling count for the digital filter. a sampling count of zero bypasses the filter. 28.7.3.16 qei index acceptance window this register contains the width of the index acceptance window, when the index and the phase/clock edges fall nearly together. if the activating phase/clock edge falls before the index, but within the window, th e (re)calibration will be activa ted on that phase/clock edge. 28.7.3.17 qei index compare register 1 this register contains an index compare value. this value is compared against the current value of the index count register. interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. 28.7.3.18 qei index compare register 2 this register contains an index compare value. this value is compared against the current value of the index count register. interrupts can be enabled to interrupt when the compare value is less than, equal to, or greater than the current value of the index count register. table 615: qei digital filter on inx (filterinx - address 0x400b c044) bit description bit symbol description reset value 31:0 fitlinx digital filter sampling delay for the index. 0 table 616: qei index acceptance window (window - address 0x400b c048) bit description bit symbol description reset value 31:0 window index acceptance window width. 0xf table 617: qei index compare register 1 (inxcmp1 - address 0x400b c04c) bit description bit symbol description reset value 31:0 icmp1 index compare value 1. 0 table 618: qei index compare register 2 (inxcmp2 - address 0x400b c050) bit description bit symbol description reset value 31:0 icmp2 index compare value 2. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 761 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4 interrupt registers 28.7.4.1 qei interrupt status register this register provides the status of the enco der interface and the current set of interrupt sources that are asserted to the controller. bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. table 619: qei interrupt status register (intstat - address 0x400b cfe0) bit description bit symbol description reset value 0 inx_int indicates that an index pulse was detected. 0 1 tim_int indicates that a velocity timer overflow occurred 0 2 velc_int indicates that captured velo city is less than compare velocity. 0 3 dir_int indicates that a change of direction was detected. 0 4 err_int indicates that an encoder phase error was detected. 0 5 enclk_int indicates that and encoder clock pulse was detected. 6 pos0_int indicates that the position 0 compare value is equal to the current position. 0 7 pos1_int indicates that the position 1compare value is equal to the current position. 0 8 pos2_int indicates that the position 2 compare value is equal to the current position. 0 9 rev0_int indicates that the index compare 0 value is equal to the current index count. 0 10 pos0rev_int combined position 0 and revolution count interrupt. set when both the pos0_int bit is set and the rev0_int is set. 0 11 pos1rev_int combined position 1 and revolution count interrupt. set when both the pos1_int bit is set and the rev1_int is set. 0 12 pos2rev_int combined position 2 and revolution count interrupt. set when both the pos2_int bit is set and the rev2_int is set. 0 13 rev1_int indicates that the index compare 1value is equal to the current index count. 0 14 rev2_int indicates that the index compare 2 value is equal to the current index count. 0 15 maxpos_int indicates that the current position count goes throug h the maxpos value to zero in the forward direction, or through zero to maxpos in the reverse direction. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 762 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4.2 qei interrupt set register writing a one to a bit in this register sets th e corresponding bit in th e qei interrupt status register (qeistat). table 620: qei interrupt set register (set - address 0x400b cfec) bit description bit symbol description 0 inx_int writing a 1 sets the inx_int bit in qeiintstat. 1 tim_int writing a 1 sets the tin_int bit in qeiintstat. 2 velc_int writing a 1 sets the velc_int bit in qeiintstat. 3 dir_int writing a 1 sets the dir_int bit in qeiintstat. 4 err_int writing a 1 sets the err_int bit in qeiintstat. 5 enclk_int writing a 1 sets the enclk_int bit in qeiintstat. 6 pos0_int writing a 1 sets the pos0_int bit in qeiintstat. 7 pos1_int writing a 1 sets the pos1_int bit in qeiintstat. 8 pos2_int writing a 1 sets the pos2_int bit in qeiintstat. 9 rev0_int writing a 1 sets the rev0_int bit in qeiintstat. 10 pos0rev_int writing a 1 sets th e pos0rev_int bit in qeiintstat. 11 pos1rev_int writing a 1 sets th e pos1rev_int bit in qeiintstat. 12 pos2rev_int writing a 1 sets th e pos2rev_int bit in qeiintstat. 13 rev1_int writing a 1 sets the rev1_int bit in qeiintstat. 14 rev2_int writing a 1 sets the rev2_int bit in qeiintstat. 15 maxpos_int writing a 1 sets th e maxpos_int bit in qeiintstat. 31:16 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 763 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4.3 qei interrupt clear register writing a one to a bit in this register clears the corresponding bit in the qei interrupt status register (qeistat). table 621: qei interrupt clear register (clr - 0x400b cfe8) bit description bit symbol description 0 inx_int writing a 1 clears the inx_int bit in qeiintstat. 1 tim_int writing a 1 clears the tin_int bit in qeiintstat. 2 velc_int writing a 1 clears the velc_int bit in qeiintstat. 3 dir_int writing a 1 clears the dir_int bit in qeiintstat. 4 err_int writing a 1 clears the err_int bit in qeiintstat. 5 enclk_int writing a 1 clears the enclk_int bit in qeiintstat. 6 pos0_int writing a 1 clears the pos0_int bit in qeiintstat. 7 pos1_int writing a 1 clears the pos1_int bit in qeiintstat. 8 pos2_int writing a 1 clears the pos2_int bit in qeiintstat. 9 rev0_int writing a 1 clears the rev0_int bit in qeiintstat. 10 pos0rev_int writing a 1 clears t he pos0rev_int bit in qeiintstat. 11 pos1rev_int writing a 1 clears t he pos1rev_int bit in qeiintstat. 12 pos2rev_int writing a 1 clears t he pos2rev_int bit in qeiintstat. 13 rev1_int writing a 1 clears the rev1_int bit in qeiintstat. 14 rev2_int writing a 1 clears the rev2_int bit in qeiintstat. 15 maxpos_int writing a 1 clears t he maxpos_int bit in qeiintstat. 31:16 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 764 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4.4 qei interrupt enable register this register enables interrupt sources. bits set to 1 enable the corresponding interrupt; a zero bit disables the corresponding interrupt. table 622: qei interrupt enable register (ie - address 0x400b cfe4) bit description bit symbol description reset value 0 inx_int when 1, the inx_int interrupt is enabled. 0 1 tim_int when 1, the tin_int interrupt is enabled. 0 2 velc_int when 1, the velc_int interrupt is enabled. 0 3 dir_int when 1, the dir_int interrupt is enabled. 0 4 err_int when 1, the err_int interrupt is enabled. 0 5 enclk_int when 1, the enclk_int interrupt is enabled. 0 6 pos0_int when 1, the pos0_int interrupt is enabled. 0 7 pos1_int when 1, the pos1_int interrupt is enabled. 0 8 pos2_int when 1, the pos2_int interrupt is enabled. 0 9 rev0_int when 1, the rev0_int interrupt is enabled. 0 10 pos0rev_int when 1, the pos0rev_int interrupt is enabled. 0 11 pos1rev_int when 1, the pos1rev_int interrupt is enabled. 0 12 pos2rev_int when 1, the pos2rev_int interrupt is enabled. 0 13 rev1_int when 1, the rev1_int interrupt is enabled. 0 14 rev2_int when 1, the rev2_int interrupt is enabled. 0 15 maxpos_int when 1, the maxpos_ int interrupt is enabled. 0 31:16 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 765 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4.5 qei interrupt enable set register writing a one to a bit in this register sets t he corresponding bit in the qei interrupt enable register (qeiie). table 623: qei interrupt enable set register (ies - address 0x400b cfdc) bit description bit symbol description 0 inx_int writing a 1 enables the inx_int interrupt in the qeiie register. 1 tim_int writing a 1 enables the tin_int interrupt in the qeiie register. 2 velc_int writing a 1 enables the velc_int interrupt in the qeiie register. 3 dir_int writing a 1 enables the dir_int interrupt in the qeiie register. 4 err_int writing a 1 enables the err_int interrupt in the qeiie register. 5 enclk_int writing a 1 enables the enclk_int interrupt in the qeiie register. 6 pos0_int writing a 1 enables the pos0_int interrupt in the qeiie register. 7 pos1_int writing a 1 enables the pos1_int interrupt in the qeiie register. 8 pos2_int writing a 1 enables the pos2_int interrupt in the qeiie register. 9 rev0_int writing a 1 enables the rev0_int interrupt in the qeiie register. 10 pos0rev_int writing a 1 enables the pos0rev_int interrupt in the qeiie register. 11 pos1rev_int writing a 1 enables the pos1rev_int interrupt in the qeiie register. 12 pos2rev_int writing a 1 enables the pos2rev_int interrupt in the qeiie register. 13 rev1_int writing a 1 enables the rev1_int interrupt in the qeiie register. 14 rev2_int writing a 1 enables the rev2_int interrupt in the qeiie register. 15 maxpos_int writing a 1 enables the maxpo s_int interrupt in the qeiie register. 31:16 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 766 of 942 nxp semiconductors UM10562 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.7.4.6 qei interrupt enable clear register writing a one to a bit in this register clear s the corresponding bit in the qei interrupt enable register (qeiie). table 624: qei interrupt enable clear register (iec - address 0x400b cfd8) bit description bit symbol description 0 inx_int writing a 1 disables the inx_int interrupt in the qeiie register. 1 tim_int writing a 1 disables the tin_int interrupt in the qeiie register. 2 velc_int writing a 1 disables the velc_int interrupt in the qeiie register. 3 dir_int writing a 1 disables the dir_int interrupt in the qeiie register. 4 err_int writing a 1 disables the err_int interrupt in the qeiie register. 5 enclk_int writing a 1 disables the enclk_int interrupt in the qeiie register. 6 pos0_int writing a 1 disables the pos0_int interrupt in the qeiie register. 7 pos1_int writing a 1 disables the pos1_int interrupt in the qeiie register. 8 pos2_int writing a 1 disables the pos2_int interrupt in the qeiie register. 9 rev0_int writing a 1 disables the rev0_int interrupt in the qeiie register. 10 pos0rev_int writing a 1 disables the pos0rev_int interrupt in the qeiie register. 11 pos1rev_int writing a 1 disables the pos1rev_int interrupt in the qeiie register. 12 pos2rev_int writing a 1 disables the pos2rev_int interrupt in the qeiie register. 13 rev1_int writing a 1 disables the rev1_int interrupt in the qeiie register. 14 rev2_int writing a 1 disables the rev2_int interrupt in the qeiie register. 15 maxpos_int writing a 1 disables the maxpo s_int interrupt in the qeiie register. 31:16 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 767 of 942 29.1 basic configuration the rtc is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcrtc (applies to both the rtc and the event recorder). remark: on reset, the rtc is enabled. see section 29.7 for power saving options. 2. clock: the rtc uses the 1 hz clock outpu t from the rtc oscillator as the internal function clock. the peripheral clock is used for access ing rtc registers. 3. interrupts: see section 29.6.1 for rtc interrupt handling. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 29.2 features ? measures the passage of time to maintain a calendar and clock. provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? ultra-low power design to support batt ery powered systems. less than 1 microamp required for battery operation. uses power from the cpu power supply whenever it is greater than v bat . ? 20 bytes of battery-backed storage and rt c operation when power is removed from the cpu. ? dedicated 32 khz ultr a low power oscillator. ? dedicated battery power supply pin. ? rtc power supply is isolated from the rest of the chip. ? calibration counter allows adjustment to better than ? 1 sec/day with 1 sec resolution. ? periodic interrupts can be generated from increments of any field of the time registers. ? alarm interrupt can be generated for a specific date/time. 29.3 description the real time clock (rtc) is a set of count ers for measuring time when system power is on, and optionally when it is off. it uses very little power when its registers are not being accessed by the cpu, especially reduced power modes. the rtc is clocked by a separate 32 khz oscillator that produces a 1 hz internal ti me reference. the rtc is powered by its own power supply pin, v bat , which can be connected to a battery, externally tied to a 3v supply, or left floating. the rtc power domain is shown in conceptual form in figure 154 . a detailed view of the time keeping portion of the rtc is shown in figure 155 . UM10562 chapter 29: lpc408x/407x real time clock (rtc) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 768 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.4 architecture fig 154. rtc domain conceptual diagram v bat pin ultra-low power regulator power selector v dd(reg)(3v3) pin ultra-low power oscillator to main regulator 1 hz clock rtc power backup registers real time clock functional block rtc power domain rtcx1 rtcx2 rtc alarm & interrupt 120601 rtc_alarm pin fig 155. rtc functional block diagram day of year second minute hour day month year alarm compare second minute hour day month year day of week calibration counter calibration compare register calibration control logic calibration compare sign bit match counter reset lsb set lsb out time registers alarm registers calibration alarm out and alarm interrupts counter increment interrupts 1 hz clock 120601
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 769 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.5 pin description 29.6 register description in the register descriptions, for most of th e registers the reset value column shows "nc", meaning that these registers are not changed by a reset. software must initialize these registers between power-on and setting the rt c into operation. the registers are split into five sections by functionality. table 625. rtc pin description name type description rtc_alarm output alarm output from the rtc. this is an active high pin that is asserted when the internal rtc alarm occurs. the output is cleared by writing a 1 to the rtcalf bit in the interrupt location register. this pin is powered by v bat . the pin can alternatively be used to indicate the deep power-down mode status via rtc_pdout in the rtc_aux register. rtcx1 input input to the rtc oscillator circuit. rtcx2 output output from the rtc oscillator circuit. remark: if the rtc is not used, the rtcx1/2 pins can be left floating. v bat input rtc power supply: typically connected to an external 3v battery. if this pin is not powered, the rtc is still powered internally if v dd(reg)(3v3) is present.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 770 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) [1] reset values apply only to a power-up of the rtc block, other types of reset have no effect on this block. since the rtc is powered whenever either of the v dd(reg)(3v3) , or v bat supplies are present, power-up reset occurs only when both supplies were absent and then one is turned on. most registers are not affected by power-up of the rtc and must be initializ ed by software if the rtc is enabled. the reset value reflects the data stored in used bits only. it does not include reserved bits content. table 626. register overview: real-time clock (base address 0x4002 4000) name access address description reset value [1] table miscellaneous registers (see section 29.6.2 ) ilr r/w 0x000 interrupt location register 0 627 ccr r/w 0x008 clock control register nc 627 ciir r/w 0x00c counter increment interrupt register 0 629 amr r/w 0x010 alarm mask register 0 630 consolidated time registers (see section 29.6.3 ) ctime0 ro 0x014 consolidated time register 0 nc 633 ctime1 ro 0x018 consolidated time register 1 nc 634 ctime2 ro 0x01c consolidated time register 2 nc 635 time counter registers (see section 29.6.4 ) sec r/w 0x020 seconds counter nc 637 min r/w 0x024 minutes register nc 637 hrs r/w 0x028 hours register nc 637 dom r/w 0x02c day of month register nc 637 dow r/w 0x030 day of week register nc 637 doy r/w 0x034 day of year register nc 637 month r/w 0x038 months register nc 637 year r/w 0x03c years register nc 637 calibration r/w 0x040 calibration value register nc 646 general purpose registers (see section 29.6.6 ) gpreg0 r/w 0x044 general purpose register 0 nc 647 gpreg1 r/w 0x048 general purpose register 1 nc 647 gpreg2 r/w 0x04c general purpose register 2 nc 647 gpreg3 r/w 0x050 general purpose register 3 nc 647 gpreg4 r/w 0x054 general purpose register 4 nc 647 rtc_aux r/w 0x05c rtc auxiliary control register 0x10 631 rtc_auxen r/w 0x058 rtc auxiliary enable register 0 632 alarm register group (see section 29.6.7 ) asec r/w 0x060 alarm value for seconds nc 648 amin r/w 0x64 alarm value for minutes nc 648 ahrs r/w 0x068 alarm value for hours nc 648 adom r/w 0x06c alarm value for day of month nc 648 adow r/w 0x070 alarm value for day of week nc 648 adoy r/w 0x074 alarm value for day of year nc 648 amon r/w 0x078 alarm value for months nc 648 ayrs r/w 0x07c alarm value for year nc 648
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 771 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.1 rtc interrupts interrupt generation is controlled through the interrupt locati on register (ilr), counter increment interrupt register (ciir), the alarm registers, and the alarm mask register (amr). interrupts are generated only by the transition into the interrupt state. the ilr separately enables ciir and amr interrupts. ea ch bit in ciir corresponds to one of the time counters. if ciir is enabled for a partic ular counter, then ever y time the counter is incremented an interrupt is generated. the alar m registers allow the user to specify a date and time for an interrupt to be generated. the amr provides a mechanism to mask alarm compares. if all non-masked alarm registers match the value in their corresponding time counter, then an interrupt is generated. the rtc and event recorder interrupts are combined, and can bring the microcontroller out of sleep, deep sleep, and power-down modes when the rtc is running and the rtc/event recorder interrupt is enabled in the nvic. for details on the rtc based wake-up process see section 3.12.8 ? wake-up from reduced power modes ? on page 71 and section 3.13 ? wake-up timer ? on page 72 . 29.6.2 miscellaneous register group 29.6.2.1 interrupt location register the interrupt location register is a 2-bit register that specifies which blocks are generating an interrupt (see ta b l e 6 2 7 ). writing a one to the appropriate bit clears the corresponding interrupt. writing a zero has no effect. this allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read. 29.6.2.2 clock control register the clock register is a 4-bit regi ster that controls the operation of the clock divide circuit. each bit of the clock r egister is described in ta b l e 6 2 8 . all nc bits in this register should be initialized when the rtc is first turned on. table 627. interrupt location register (ilr - address 0x4002 4000) bit description bit symbol description reset value 0 rtccif when one, the counter increment interrupt block generated an interrupt. writing a one to this bit location clears the counter increment interrupt. 0 1 rtcalf when one, the alarm registers generated an interrupt. writing a one to this bit location clears the alarm interrupt. 0 31:21 - reserved. read value is undefined, only zero should be written. na table 628. clock control register (ccr - address 0x4002 4008) bit description bit symbol value description reset value 0 clken clock enable. nc 1 the time counters are enabled. 0 the time counters are disabled so that they may be initialized. 1 ctcrst ctc reset. 0 1 when one, the elements in the internal oscillator divider are reset, and remain reset until ccr[1] is changed to zero. this is the divider that generates the 1 hz clock from the 32.768 khz crystal. the state of the divider is not visible to software. 0 no effect.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 772 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.2.3 counter increment interrupt register the counter increment interrupt register (ciir) give s the ability to gene rate an interrupt every time a counter is incremented. this inte rrupt remains valid until cleared by writing a 1 to bit 0 of the interrupt location register (ilr[0]). 29.6.2.4 alarm mask register the alarm mask register (amr) allows the us er to mask any of the alarm registers. table 630 shows the relationship between the bits in the amr and the alarms. for the alarm function, every non-masked alarm register must match the corresponding time counter for an interrupt to be generated. the interrupt is generated only when the counter comparison first changes from no match to match. the interrupt is removed when a one is written to the appropriate bit of the interrupt location register (ilr). if all mask bits are set, then the alarm is disabled. 3:2 - internal test mode controls. these bits must be 0 for normal rtc operation. nc 4 ccalen calibration counter enable. nc 1 the calibration counter is disabled and reset to zero. 0 the calibration counter is enabled and counting, using the 1 hz clock. when the calibration counter is equal to the value of the calibration register, the counter resets and repeats counting up to the value of the calibration register. see section 29.6.4.2 and section 29.6.5 . 31:5 - reserved. read value is undefined, only zero should be written. na table 628. clock control register (ccr - address 0x4002 4008) bit description bit symbol value description reset value table 629. counter increment interrupt register (ciir - address 0x4002 400c) bit description bit symbol description reset value 0 imsec when 1, an increment of the second value generates an interrupt. 0 1 immin when 1, an increment of the minute value generates an interrupt. 0 2 imhour when 1, an increment of the hour value generates an interrupt. 0 3 imdom when 1, an increment of the day of month value generates an interrupt. 0 4 imdow when 1, an increment of the day of week value generates an interrupt. 0 5 imdoy when 1, an increment of the day of year value generates an interrupt. 0 6 immon when 1, an increment of the month value generates an interrupt. 0 7 imyear when 1, an increment of the year value generates an interrupt. 0 31:8 - reserved. read value is undefined, only zero should be written. na table 630. alarm mask register (amr - address 0x4002 4010) bit description bit symbol description reset value 0 amrsec when 1, the second value is not compared for the alarm. 0 1 amrmin when 1, the minutes value is not compared for the alarm. 0 2 amrhour when 1, the hour value is not compared for the alarm. 0 3 amrdom when 1, the day of month value is not compared for the alarm. 0 4 amrdow when 1, the day of week value is not compared for the alarm. 0 5 amrdoy when 1, the day of year value is not compared for the alarm. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 773 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.2.5 rtc auxiliary control register the rtc auxiliary control regist er contains added interrupt fl ags for functions that are not part of the real time clock itself (the part recording the passage of time and generating other time related functions). the only added in terrupt flag for these devices is for failure of the rtc oscillator. 29.6.2.6 rtc auxiliary enable register the rtc auxiliary enab le register controls whethe r additional interrupt sources represented in the rt c auxiliary control re gister are enabled. 29.6.3 consolidated time registers the values of the time counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. the various registers are packed into 32-bit values as shown in ta b l e 6 3 3 , table 634 , and table 635 . the least significant bit of each regist er is read back at bit 0, 8, 16, or 24. the consolidated time registers are read-o nly. to write new values to the time counters, the time counter addresses should be used. 6 amrmon when 1, the month value is not compared for the alarm. 0 7 amryear when 1, the year value is not compared for the alarm. 0 31:8 - reserved. read value is undefined, only zero should be written. na table 630. alarm mask register (amr - address 0x4002 4010) bit description bit symbol description reset value table 631. rtc auxiliary control register (rtc_aux - address 0x4002 405c) bit description bit symbol description reset value 3:0 - reserved. read value is undefined, only zero should be written. na 4 rtc_oscf rtc oscillator fail detect flag. read: this bit is set if the rtc oscillator stops, and when rtc power is first turned on. an interrupt will occur when this bit is set, the rtc_oscfen bit in rtc_auxen is a 1, and the rtc interrupt is enabled in the nvic. write: writing a 1 to this bit clears the flag. 1 5 - reserved. read value is undefined, only zero should be written. na 6 rtc_pdout when 0: the rtc_alarm pin reflects the rtc alarm status. when 1: the rtc_alarm pin indicates deep power-down mode. 0 31:7 - reserved. read value is undefined, only zero should be written. na table 632. rtc auxiliary enable register (rtc_auxen - address 0x4002 4058) bit description bit symbol description reset value 3:0 - reserved. read value is undefined, only zero should be written. na 4 rtc_oscfen oscillator fail detect interrupt enable. when 0: the rtc oscillator fail detect interrupt is disabled. when 1: the rtc oscillator fail detect interrupt is enabled. see section 29.6.2.5 . 0 31:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 774 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.3.1 consolidated time register 0 the consolidated time register 0 contains th e low order time values: seconds, minutes, hours, and day of week. 29.6.3.2 consolidated time register 1 the consolidate time register 1 contains t he day of month, month, and year values. 29.6.3.3 consolidated time register 2 the consolidate time register 2 contains just the day of year value. 29.6.4 time counter group the time value consists of the eight counters shown in table 636 and table 637 . these counters can be read or written at the locations shown in table 637 . table 633. consolidated time register 0 (ctime0 - address 0x4002 4014) bit description bit symbol description reset value 5:0 seconds seconds value in the range of 0 to 59 nc 7:6 - reserved. the value read from a reserved bit is not defined. na 13:8 minutes minutes value in the range of 0 to 59 nc 15:14 - reserved. the value read from a reserved bit is not defined. na 20:16 hours hours value in the range of 0 to 23 nc 23:21 - reserved. the value read from a reserved bit is not defined. nc 26:24 dow day of week value in the range of 0 to 6 na 31:27 - reserved. the value read from a reserved bit is not defined. nc table 634. consolidated time register 1 (ctime1 - address 0x4002 4018) bit description bit symbol description reset value 4:0 dom day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). nc 7:5 - reserved. the value read from a reserved bit is not defined. na 11:8 month month value in the range of 1 to 12. nc 15:12 - reserved. the value read from a reserved bit is not defined. na 27:16 year year value in the range of 0 to 4095. nc 31:28 - reserved. the value read from a reserved bit is not defined. na table 635. consolidated time register 2 (ctime2 - address 0x4002 401c) bit description bit symbol description reset value 11:0 doy day of year value in the range of 1 to 365 (366 for leap years). nc 31:12 - reserved. the value read from a reserved bit is not defined. na table 636. time counter relationships and values counter size enabled by minimum value maximum value second 6 1 hz clock 0 59 minute 6 second 0 59 hour 5 minute 0 23 day of month 5 hour 1 28, 29, 30 or 31
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 775 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) [1] these values are simply incremented at the appropriate intervals and reset at the defined overflow point. they are not calculated and must be correctly initialized in order to be meaningful. day of week 3 hour 0 6 day of year 9 hour 1 365 or 366 (for leap year) month 4 day of month 1 12 year 12 month or day of year 0 4095 table 636. time counter relationships and values counter size enabled by minimum value maximum value table 637. time counter registers name size description access address sec 6 seconds value in the range of 0 to 59 r/w 0x4002 4020 min 6 minutes value in the range of 0 to 59 r/w 0x4002 4024 hrs 5 hours value in the range of 0 to 23 r/w 0x4002 4028 dom 5 day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). [1] r/w 0x4002 402c dow 3 day of week value in the range of 0 to 6 [1] r/w 0x4002 4030 doy 9 day of year value in the range of 1 to 365 (366 for leap years) [1] r/w 0x4002 4034 month 4 month value in the range of 1 to 12 r/w 0x4002 4038 year 12 year value in the range of 0 to 4095 r/w 0x4002 403c table 638. seconds register (sec - address 0x4002 4020) bit description bit symbol description reset value 5:0 seconds seconds value in the range of 0 to 59. the register value is not changed by reset. - 31:6 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 639. minutes register (min - address 0x4002 4024) bit description bit symbol description reset value 5:0 minutes minutes value in the range of 0 to 59. the register value is not changed by reset. - 31:6 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 640. hours register (hrs - address 0x4002 4028) bit description bit symbol description reset value 4:0 hours hours value in the range of 0 to 23. the register value is not changed by reset. - 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 776 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.4.1 leap year calculation the rtc does a simple bit comparison to see if the two lowest order bits of the year counter are zero. if true, then the rtc consider s that year a leap year. the rtc considers all years evenly divisible by 4 as leap years. this algorithm is accurate from the year 1901 through the year 2099, but fails for the year 2 100, which is not a leap year. the only effect of leap year on the rtc is to alter the length of the month of february for the month, day of month, and year counters. 29.6.4.2 calibration register the following register is used to calibrate the time counter. table 641. day of month register (dom - address 0x4002 402c) bit description bit symbol description reset value 4:0 dom day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). - 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 642. day of week register (dow - address 0x4002 4030) bit description bit symbol description reset value 2:0 dow day of week value in the range of 0 to 6. - 31:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 643. day of year register (doy - address 0x4002 4034) bit description bit symbol description reset value 8:0 doy day of year value in the range of 1 to 365 (366 for leap years). - 31:9 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 644. month register (month - address 0x4002 4038) bit description bit symbol description reset value 3:0 month month value in the range of 1 to 12. - 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 645. year register (year - address 0x4002 403c) bit description bit symbol description reset value 11:0 year year value in the range of 0 to 4095. the register value is not changed by reset. - 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 777 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.5 calibration procedure the calibration logic can periodically adjust the time counter either by not incrementing the counter, or by incrementing the counter by 2 instead of 1. this allows calibrating the rtc oscillator under some typi cal voltage and temperature co nditions withou t the need to externally trim the rtc oscillator. a recommended method for determining the calibration value is to use the clkout feature to unintrusively observe the rtc oscillator frequency under the conditions it is to be trimmed for, and calculating th e number of clocks th at will be seen before the time is off by one second. that value is used to determine calval. if the rtc oscillator is trimmed externally, the same method of unintru sively observing the rtc oscillator frequency may be helpful in that process. backward calibration enable the rtc timer and calibration in the ccr register (set bits clken = 1 and ccalen = 0). in the calibration register, set the calibration value calval ? 1 and select caldir = 1. ? the sec timer and the calibration counte r count up for every 1 hz clock cycle. ? when the calibration counter reaches calval, a calibration match occurs and all rtc timers will be stop ped for one clock cycle so that the timers will not increment in the next cycle. ? if an alarm match event occurs in the same cycle as the calibration match, the alarm interrupt will be delayed by one cycle to avoid a double alar m interrupt. forward calibration enable the rtc timer and calibration in the ccr register (set bits clken = 1 and ccalen = 0). in the calibration register, set the calibration value calval ? 1 and select caldir = 0. ? the sec timer and the calibration counte r count up for every 1 hz clock cycle. ? when the calibration counter reaches calv al, a calibration match occurs and the rtc timers are incremented by 2. ? when the calibration event occurs, the lsb of the alsec register is forced to be one so that the alarm interr upt will not be missed when skipping a second. table 646. calibration register (calibration - address 0x4002 4040) bit description bit symbol value description reset value 16:0 calval - if enabled, the calibration counter counts up to this value. the maximum value is 131, 072 corresponding to about 36.4 hours. calibration is disabled if calval = 0. nc 17 caldir calibration direction nc 1 backward calibration. when calval is equal to the calibration counter, the rtc timers will stop incrementing for 1 second. 0 forward calibration. when calval is equal to the calibration counter, the rtc timers will jump by 2 seconds. 31:12 reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 778 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.6.6 general purpose registers 29.6.6.1 general purpose registers 0 to 4 these registers can be used to store important information when the main power supply is off. the value in these registers is not affected by chip reset. 29.6.7 alarm register group the alarm registers are shown in table 648 . the values in these registers are compared with the time counters. if all the unmasked (see section 29.6.2.4 ? alarm mask register ? on page 772 ) alarm registers match their corresponding time counters then an interrupt is generated. the interrupt is cleared when a 1 is written to bit 1 of the interrupt location register (ilr[1]). table 647. general purpose registers (gpreg[0:4] - addresses 0x4002 4044 (gpreg0) to 0x4002 4054 (gpreg4)) bit description bit symbol description reset value 31:0 gp general purpose storage. n/a table 648. alarm registers name size description access address alsec 6 alarm value for seconds r/w 0x4002 4060 almin 6 alarm value for minutes r/w 0x4002 4064 alhour 5 alarm value for hours r/w 0x4002 4068 aldom 5 alarm value for day of month r/w 0x4002 406c aldow 3 alarm value for day of week r/w 0x4002 4070 aldoy 9 alarm value for day of year r/w 0x4002 4074 almon 4 alarm value for months r/w 0x4002 4078 alyear 12 alarm value for years r/w 0x4002 407c table 649. alarm seconds register (asec - address 0x4002 4060) bit description bit symbol description reset value 5:0 seconds seconds value in the range of 0 to 59. the register value is not changed by reset. - 31:6 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 650. alarm minutes register (amin - address 0x4002 4064) bit description bit symbol description reset value 5:0 minutes minutes value in the range of 0 to 59. the register value is not changed by reset. - 31:6 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 779 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) table 651. alarm hours register (ahrs - address 0x4002 4068) bit description bit symbol description reset value 4:0 hours hours value in the range of 0 to 23. the register value is not changed by reset. - 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 652. alarm day of month register (adom - address 0x4002 406c) bit description bit symbol description reset value 4:0 dom day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year). the register value is not changed by reset. - 31:5 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 653. alarm day of week register (adow - address 0x4002 4070) bit description bit symbol description reset value 2:0 dow day of week value in the range of 0 to 6. the register value is not changed by reset. - 31:3 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 654. alarm day of year register (adoy - address 0x4002 4074) bit description bit symbol description reset value 8:0 doy day of year value in the range of 1 to 365 (366 for leap years). the register value is not changed by reset. - 31:9 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 655. alarm month register (amon - address 0x4002 4078) bit description bit symbol description reset value 3:0 month month value in the range of 1 to 12. the register value is not changed by reset. - 31:4 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. - table 656. alarm year register (ayrs - address 0x4002 407c) bit description bit symbol description reset value 11:0 year year value in the range of 0 to 4095. the register value is not changed by reset. - 31:12 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 780 of 942 nxp semiconductors UM10562 chapter 29: lpc408x/407x real time clock (rtc) 29.7 rtc usage notes if the rtc is used, v bat may be connected to an independent power supply (typically an external battery), or left fl oating. the rtc domain will alwa ys be internally powered if v dd(reg)(3v3) is present, even if there is no power applied to v bat . as long as power is available on either v dd(reg)(3v3) or v bat , the rtc will not lose its time value and backup register contents. if both v dd(reg)(3v3) and v bat are not present, all rtc information will be lost. the rtc will stop incrementing or be unpredictable if the clock source is lost, interrupted, or altered. the event recorder is powered in the same manner as the rtc.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 781 of 942 30.1 basic configuration the event monitor/recorder is config ured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcrtc (applies to both the rtc and the event monitor/recorder). remark: on reset, the event monitor/recorder is enabled. 2. clock: the event monitor/recorder uses the 1 hz clock output from the rtc oscillator as the internal function clock. the peripheral clock is used for accessing rtc registers. 3. interrupts: refer to section 29.1 for rtc/event monitor/recorder interrupt handling. interrupts are enabled in the nvic using the appropriate interrupt set enable register. 30.2 features ? three digital event inputs in the vbat power domain. ? an event is a level change at the digital event inputs. ? for each event channel, two timestamps mark the first and the last occurrence of an event. each channel also has a dedicated counter tracking the total number of events. timestamp values are taken from the rtc. ? runs in vbat power domain, independent of system power supply. can therefore run in deep power down mode. ? very low-power consumption. ? interrupt available if system is up. ? a qualified event can be used as a wake-up trigger. ? state of event inputs accessible by software through general purpose i/o. 30.3 applications recording of tampering events in sealed prod uct enclosures. sensor s report any attempt to open the enclosure, or to tamper with the device in any other way. the primary purpose of the event monitor/recorder is to store records of such events when the device is powered only by the backup battery. UM10562 chapter 30: lpc408x/407x event monitor/recorder rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 782 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder 30.4 description the event monitor/recorder relies on vbat to be present at all times. a loss or dip of vbat voltage causes the real-time clock power fail detector to reset the event recordings. it is therefore important to have a vbat power source that can deliver power for the longest expected mains power outage. once system power is restored, the cpu can check for recorded tamper events. if there were tamper events, the timestamp registers for the first and the last event would indicate the period over which they occurred. an edge on an event input is sampled with eith er a 1 khz clock, a 64 hz clock, or a 16 hz clock. a transition in either direction must be captured by two successive edges of this clock in order to be recognized as a valid transi tion. this provides a 1- 2 ms rejection filter in case of the 1 khz sample clock, a 15.6-31.2 ms rejection filter in case of the 64 hz sample clock, and a 62.5-125ms rejection filter in case of the 16 hz sample clock. -such an event will set the evx bit in the erstatus register on the next rising edge of the 1 hz clock. if an event occurs, a timestamp will be taken from the rtc and stored in the erlaststampx register. this timestamp w ill be updated with every new event. the event will also update the erfirs tstampx register if this is the first event to occur since the last time the evx bit in the status register was cleared. in addition to taking the timestamp( s), a 3-bit co unter (ercounterx) will be incremented on the rising edge of the 1 hz clock (i.e. coincident with the erlaststampx register being updated). the counter stops co unting and holds when it reaches a count of seven. it will be cleared automat ically when the software clea rs the evx bit in the status register. an event can be enabled to clear the backup registers in the rtc block asynchronously. this works even when the 32 khz oscillator is not running or when event monitor/recorder clocks are disabled. the following figure shows a block di agram of the event monitor/recorder.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 783 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder the cpu may at any time check the erstatus register for events. if, for instance the ev0 bit is set, the corresponding erfirststamp0 and erlaststamp0 registers contain valid timestamps. the ercounter0 will also contain a valid count of the total number of events on channel 0 (up to a maximum of seven). once the (private) timestamps have been read, the cpu can clear the erstatus.evx bits by writing a 1 to it. the cpu should ignore the timestamp registers if the erstatus.evx bit is cleared. there is no mechanism to clear or invalidate the timestamps after the event flag in the status register has been clea red. the timestamp registers w ill keep their old values until a new qualified event up dates them. such a qualified event will set the erstatus.evx bit and inform the cpu that the timestamp registers contain new values. an event channel can be qualified as a wake-up trigger signal by setting the intwake_enax bit in the erco ntrol register. an event in that channel w ill then wake up the device from a power saving mode. fig 156. event monitor/recorder block diagram 120531 rtc_ev0 rtc_ev2 rtc_ev1 timestamp value doy:h:m:s to wake-up/ interrupt control block ercontrol rtc ercounters erstatus erfirststamp0 erlaststamp0 erfirststamp1 erlaststamp1 erfirststamp2 erlaststamp2
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 784 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder 30.5 pin description 30.6 register description in the register descriptions, the reset value shown applies only to a power-up of the rtc domain, meaning that these registers are not changed by a device reset. [1] reset values apply only to a power-up of the event monitor/recorder block, other types of reset have no effect on this block. since the event monitor/ recorder is powered whenever either of the v dd(reg)(3v3) , or v bat supplies are present, power-up reset occurs onl y when both supplies were absent and then one is turned on. the reset value reflects the data stored in used bits only. it does not include reserved bits content. table 657. event monitor/recorder pin description name type description rtc_ev0 input event input for event monitor/recorder channel 0. rtc_ev1 input event input for event monitor/recorder channel 1. rtc_ev2 input event input for event monitor/recorder channel 2. table 658. register overview: event monitor/recorder (base address 0x4002 4000) name access address description value [1] table ercontrol r/w 0x084 event monitor/recorder control register. contains bits that control actions for the event channels as well as for event monitor/recorder setup. 0 659 erstatus r/w 0x080 event monitor/recorder status register. contains status flags for event channels and other event monitor/recorder conditions. 0 660 ercounters ro 0x088 event monitor/recorder counters register. allows reading the counters associated with the event channels. 0 661 erfirststamp0 ro 0x090 event monitor/recorder first stamp register for channel 0. retains the time stamp for the first event on channel 0. na 662 erfirststamp1 ro 0x094 event monitor/recorder first stamp register for channel 1 (see erfirststamp0 description). na 662 erfirststamp2 ro 0x098 event monitor/recorder first stamp register for channel 2 (see erfirststamp0 description). na 662 erlaststamp0 ro 0x0a0 event monitor/recorder last stamp register for channel 0. retains the time stamp for the last (i.e. most recent) event on channel 0. na 663 erlaststamp1 ro 0x0a4 event monitor/recorder last stamp register for channel 1 (see erlaststamp0 description). na 663 erlaststamp2 ro 0x0a8 event monitor/recorder last stamp register for channel 2 (see erlaststamp0 description). na 663
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 785 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder 30.6.1 event monitor/recorder control register the event monitor/recorder control register allows setup of the event monitor/recorder and individual control over aspects of each channel?s operation. table 659. event monitor/recorder control register (ercontrol - 0x4002 4084) bit description bit symbol value description reset value 0 intwake_en0 interrupt and wake-up enable for channel 0. 0 0 no interrupt or wake-up will be generated by event channel 0. 1 an event in channel 0 will trigger an (rtc) interrupt and a wake-up request. 1 gpclear_en0 enables automatically clearing the rtc general purpose registers when an event occurs on channel 0. 0 0 channel 0 has no influence on the general purpose registers. 1 an event in channel 0 will clear the general purpose registers asynchronously. 2 pol0 selects the polarity of an event on input pin rtc_ev0. 0 0 a channel 0 event is defined as a negative edge on rtc_ev0. 1 a channel 0 event is defined as a positive edge on rtc_ev0. 3 ev0_input_en event enable control for channel 0. [1] 0 0 event 0 input is disabled and forced high internally. 1 event 0 input is enabled. 9:4 - reserved. read value is undefined, only zero should be written. na 10 intwake_en1 interrupt and wake-up enable for channel 1. 0 0 no interrupt or wake-up will be generated by event channel 1. 1 an event in channel 1 will trigger an (rtc) interrupt and a wake-up request. 11 gpclear_en1 enables automatically clearing the rtc general purpose registers when an event occurs on channel 1. 0 0 channel 1 has no influence on the general purpose registers. 1 a n event in channel 1 will clear the general purpose registers asynchronously. 12 pol1 selects the polarity of an event on input pin rtc_ev1. 0 0 a channel 1 event is defined as a negative edge on rtc_ev1. 1 a channel 1 event is defined as a positive edge on rtc_ev1. 13 ev1_input_en event enable control for channel 1. [1] 0 0 event 1 input is disabled and forced high internally. 1 event 1 input is enabled. 19:14 - reserved. read value is undefined, only zero should be written. na 20 intwake_en2 interrupt and wake-up enable for channel 2. 0 no interrupt or wake-up will be generated by event channel 2. 1 an event in channel 2 will trigger an (rtc) interrupt and a wake-up request. 21 gpclear_en2 enables automatically clearing the rtc general purpose registers when an event occurs on channel 2. 0 0 channel 2 has no influence on the general purpose registers. 1 an event in channel 2 will clear the general purpose registers asynchronously.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 786 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder [1] event inputs should remain disabled when not bei ng used for event detection, particularly if the associated pin is being used for some other function. [2] event monitor/recorder registers can always be wri tten to regardless of the st ate of these bits. events occurring during the 1-sec interval immediately foll owing enabling of the clocks may not be recognized. 22 pol2 selects the polarity of an event on input pin rtc_ev2. 0 0 a channel 2 event is defined as a negative edge on rtc_ev2. 1 a channel 2 event is defined as a positive edge on rtc_ev2. 23 ev2_input_en event enable control for channel 2. [1] 0 0 event 2 input is disabled and forced high internally. 1 event 2 input is enabled. 29:24 - reserved. read value is undefined, only zero should be written. na 31:30 ermode controls enabling the event monitor/recorder and selecting its operating frequency. [2] 0 00 event monitor/record er clocks are disabled. operation of the event monitor/recorder is disabled except for asynchronous clearing of gp registers if selected. 01 enable event monitor/recorder and select a 16 hz sample clock for event input edge detection and glitch suppression. pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out. 10 enable event monitor/recorder and select a 64 hz sample clock for event input edge detection and glitch suppression. pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out. 11 enable event monitor/recorder and select a 1 khz sample clock for event input edge detection and glitch suppression. pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out. table 659. event monitor/recorder control register (ercontrol - 0x4002 4084) bit description bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 787 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder 30.6.2 event monitor/recorder status register the event monitor/recorder status register contains flags for the 3 event channels, general purpose register clear fl ag, and the interrupt/wake-up flag. table 660. event monitor/recorder status register (erstatus - 0x4002 4080) bit description bit symbol value description reset value 0 ev0 event flag for channel 0 (rtc_ev0 pin). set at the end of any second if there has been an event during the preceding second. th is bit is cleared by writing a 1 to it. writing 0 has no effect. 0 0 no event change on channel 0. 1 at least one event has occurred on channel 0. 1 ev1 event flag for channel 1 (rtc_ev1 pin). set at the end of any second if there has been an event during the preceding second. th is bit is cleared by writing a 1 to it. writing 0 has no effect. 0 0 no event change on channel 1. 1 at least one event has occurred on channel 1. 2 ev2 event flag for channel 2 (rtc_ev2 pin). set at the end of any second if there has been an event during the preceding second. th is bit is cleared by writing a 1 to it. writing 0 has no effect. 0 0 no event change on channel 2. 1 at least one event has occurred on channel 2. 3 gp_cleared general purpose register asynchronous clear flag. this bit is cleared by writing a 1 to it. writing 0 has no effect. 0 0 general purpose registers have not been asynchronous cleared. 1 general purpose registers have been asynchronous cleared. 30:4 - reserved. read value is undefined, only zero should be written. na 31 wakeup interrupt/wake-up request flag (read-only). this bit is cleared by writing a 1 to it. writing 0 has no effect. 0 0 no interrupt/wake-up request is pending 1 an interrupt/wake-up request is pending.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 788 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder 30.6.3 event monitor/reco rder counters register the event monitor/recorder counters register is a read-only register that allows reading counters that record the number of events on each event monitor/recorder channel. 30.6.4 event monitor/recorder first stamp register the read-only event monitor/recorder first stamp registers record a timestamp (from the rtc) of the first event that occurs on ea ch event monitor/recorder channel. this is when the corresponding evx bit in the erst atus register becomes set. once that has happened, these registers will not change until software clea rs the corresponding evx bit in the erstatus register. contents of these register are only valid if the corresponding evx bit in the erstatus register = 1. 30.6.5 event monitor/recorder last stamp register the read-only event monitor/recorder last stamp registers record a timestamp (from the rtc) whenever an event occurs on each event monitor/recorder channel. contents of these register are only valid if the corresponding evx bit in the erstatus register = 1. table 661. event monitor/recorder counters register (ercounters - 0x4002 4088) bit description bit symbol description reset value 2:0 counter0 value of the counter for event 0. if the counter reaches full count (the value 7), it remains there if additional events occur. this counter is cleared when the corresponding evx bit in the erstatus register is cleared by software. 0 7:3 - reserved. the value read from a reserved bit is not defined. na 10:8 counter1 value of the counter for event 1. see description for counter0. 0 15:11 - reserved. the value read from a reserved bit is not defined. na 18:16 counter2 value of the counter for event 2. see description for counter0. 0 31:19 - reserved. the value read from a reserved bit is not defined. na table 662. event monitor/recorder first stamp register (erfirststamp0 - 0x0x4002 4090, erfirststamp1 - 0x0x4002 4094, erfirststamp2 - 0x4002 4098) bit description bit symbol description reset value 5:0 sec seconds value in the range of 0 to 59. na 11:6 min minutes value in the range of 0 to 59. na 16:12 hour hours value in the range of 0 to 23. na 25:17 doy day of year value in the range of 1 to 366. na 31:26 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 789 of 942 nxp semiconductors UM10562 chapter 30: lpc408x/407x event monitor/recorder note that after a first event on any ch annel, the contents of the corresponding erfirststamp and erlaststamp registers w ill be the same (the first event and the most recent event being the same). the values will dive rge if a second event occurs on the same channel table 663. event monitor/recorder last stamp register (erlaststamp0 - 0x0x4002 40a0, erlaststamp1 - 0x0x4002 40a4, erlaststamp2 - 0x4002 40a8) bit description bit symbol description reset value 5:0 sec seconds value in the range of 0 to 59. na 11:6 min minutes value in the range of 0 to 59. na 16:12 hour hours value in the range of 0 to 23. na 25:17 doy day of year value in the range of 1 to 366. na 31:26 - reserved. the value read from a reserved bit is not defined. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 790 of 942 31.1 features ? internally resets chip if not reloaded during the programmable timeout period. ? optional windowed operation requires reload to occur between a minimum and maximum timeout period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog timeout. ? programmable 24 bit timer with internal fixed pre-scaler. ? selectable time period from 1,024 watchdog clocks (t wdclk ? 256 ? 4) to over 67 million watchdog clocks (t wdclk ? 2 24 ? 4) in increments of 4 watchdog clocks. ? ?safe? watchdog operation. once enabled, requires a hardware reset or a watchdog reset to be disabled. ? a dedicated on-chip watchdog osc illator provides a reliable clock source that cannot be turned off when the watchdog timer is running. ? incorrect feed sequence causes immediate watchdog reset if the watchdog is enabled. ? the watchdog reload value can optionally be protected such that it can only be changed after the ?warning interrupt? time is reached. ? flag to indicate watchdog reset. 31.2 applications the purpose of the watchdog timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. when enabled, a watc hdog event will be generated if the user progra m fails to "feed" (or relo ad) the watchdog within a predetermined amoun t of time. the watchdog event will cause a chip reset if configured to do so. when a watchdog window is programmed, an early watchdog feed is also treated as a watchdog event. this allows preventing situat ions where a system failure may still feed the watchdog. for example, application code co uld be stuck in an interrupt service that contains a watchdog feed. setting the window such that this would result in an early feed will generate a watchdog event, a llowing for system recovery. for interaction of the on-chip watchdog and other peripherals, especially the reset and boot-up procedures, please refer to section 3.4 . UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 791 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.3 description the watchdog consists of a fixed divide by 4 pre-scaler and a 24 bit counter which decrements when clocked. the minimum value from which the counter decrements is 0xff. setting a value lower than 0xff causes 0xff to be loaded in the counter. hence the minimum watchdog interval is (t wdclk ? 256 ? 4) and the maximum watchdog interval is (t wdclk ? 2 24 ? 4) in multiples of (t wdclk ? 4). the watchdog should be used in the following manner: ? set the watchdog timer constant reload value in wdtc register. ? setup the watchdog timer operating mode in wdmod register. ? set a value for the watchdog window ti me in wdwindow register if windowed operation is required. ? set a value for the watchdog warning inte rrupt in the wdwarnint register if a warning interrupt is required. ? enable the watchdog by writing 0xaa fo llowed by 0x55 to the wdfeed register. ? the watchdog must be fed again before the watchdog counter reaches zero in order to prevent a watchdog event. if a window value is programmed, the feed must also occur after the watchdog co unter passes that value. when the watchdog timer is co nfigured so that a watchdog event will caus e a reset and the counter reaches zero, the cpu will be rese t, loading the stack pointer and program counter from the vector table as in the case of external reset. the watchdog time-out flag (wdtof) can be examined to determine if the watchdog has caused the reset condition. the wdtof flag must be cleared by software. when the watchdog timer is configured to gene rate a warning interrupt, the interrupt will occur when the counter matches the value defined by the wdwarnint register. the watchdog timer block uses two clocks: pclk and wdclk. pclk is used for the apb accesses to the watchdog registers. wdclk runs the watchdog timer counter. this clock comes for a dedicated oscillator that is always on when the watchdog timer is enabled. this oscillator has a typical frequency of 500 khz (see section 3.8.4 ). there is some synchronization logic betw een these two clock domains. when the wdmod and wdtc registers are updated by apb operations , the new value will take effect on the logic in the wdclk clock doma in in 3 wdclk cycles. when the watchdog timer is counting, the synchronization logic will first lock the va lue of the counter on wdclk and then synchronize it with the pclk when the wdtv register is read by the cpu. the block diagram of the watchdog is shown below in the figure 157 . the synchronization logic (pclk - wdclk) is not shown in the block diagram.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 792 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) fig 157. watchdog timer block diagram watchdog interrupt wdreset (wdmod[1]) wdtof (wdmod[2]) wdint (wdmod[3]) wden (wdmod[0]) chip reset 4 feed error feed ok enable count wdmod register compare wdtv compare in range underflow feed sequence detect and protection wdfeed feed ok feed ok compare 0 interrupt compare 24-bit down counter wdintval wdwind wdtc shadow bit wdprotect (wdmod[4]) wdtc write 120601 wd_clk dedicated watchdog oscillator
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 793 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.4 register description [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 664. register overview: watchdog (base address 0x4000 0000) name access address description reset value [1] table mod r/w 0x000 watchdog mode register. this register determines the basic mode and status of the watchdog timer. 0 665 tc r/w 0x004 watchdog timer constant register. the value in this register determines the time-out value. 0xff 667 feed wo 0x008 watchdog feed sequence register. writing 0xaa followed by 0x55 to this register reloads the watchdog timer with the value contained in wdtc. na 668 tv ro 0x00c watchdog timer value register. this register reads out the current value of the watchdog timer. 0xff 669 warnint r/w 0x014 watchdog warning interrupt compare value. 0 670 window r/w 0x018 watchdog window compare value. 0xff ffff 671
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 794 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.4.1 watchdog mode register the wdmod register controls the operation of the watchdog as per the combination of wden and reset bits. note that a watchdog feed must be performed before any changes to the wdmod register take effect. once the wden , wdprotect , or wdreset bits are set they can not be cleared by software. these flags are cleared by an external reset or a watchdog timer reset. watchdog reset or interrupt will occur any time the watchdog is running. if a watchdog interrupt occurs in sleep or deep sleep mode, it will wake up the device. wdtof the watchdog time-out flag is set when th e watchdog times out, when a feed error occurs, or when wdprotect =1 and an attemp t is made to write to the wdtc register. this flag is cleared by software writing a 0 to this bit. wdint the watchdog interrupt flag is set when the watchdog counter reaches the value specified by wdwarnint. this flag is cleared when any reset occurs, and is cleared by software by writing a 1 to this bit. wdprotect this provides additional protection by essent ially only allowing the watchdog reload value to be changed during the interrupt service of the watchdog. the watchdog must be running (set up and the first feed performed) before wdprotect is set. table 665: watchdog mode register (mod - 0x4000 0000) bit description bit symbol value description reset value 0 wden watchdog enable bit. this bit is set only. see table 666 .0 0 the watchdog timer is stopped. 1 the watchdog timer is running. 1 wdreset watchdog reset enable bi t. this bit is set only. see table 666 .0 0 a watchdog timeout will not cause a chip reset. 1 a watchdog timeout will cause a chip reset. 2 wdtof watchdog time-out flag. set when the watchdog timer times out, by a feed error, or by events associated with wdprotect, cleared by software. causes a chip reset if wdreset = 1. see section ? wdtof ? . 0 (only after external reset) 3 wdint watchdog interrupt flag. set when the timer reaches the value in wdwarnint. cleared by software. see section ? wdint ? . 0 4 wdprotect watchdog update mode. this bit is set only. see section ? wdprotect ? .0 0 the watchdog reload value (wdtc) can be changed at any time. 1 the watchdog reload value (wdtc) can be changed only after the counter is below the value of wdwarnint and wdwindow. note : this mode is intended for use only when wdreset =1. 7:5 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 795 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.4.2 watchdog timer constant register the wdtc register determines the time-out value. every time a feed sequence occurs the wdtc content is reloaded in to the watchdog timer. this is pre-loaded with the value 0x00 00ff upon reset. writing values below 0xff will cause 0x00 00ff to be loaded into the wdtc. thus the minimum time-out interval is t wdclk ? 256 ? 4. if the wdprotect bit in wdmod = 1, an at tempt to change the value of wdtc before the watchdog counter is below the values of wdwar nint and wdwindow will cause a watchdog reset and set the wdtof flag. 31.4.3 watchdog feed register writing 0xaa followed by 0x55 to this register will reload the watchdog timer with the wdtc value. this operation will also start the watchdog if it is enabled via the wdmod register. setting the wden bit in the wdmod register is not sufficient to enable the watchdog. a valid feed sequence must be completed after setting wden before the watchdog is capable of generat ing a reset. until then, th e watchdog will ignore feed errors. after writing 0xaa to wdfeed, access to any watchdog register other than writing 0x55 to wdfeed causes an immediate reset/i nterrupt when the watchdog is enabled, and sets the wdtof flag. the reset will be ge nerated during the se cond pclk following an incorrect access to a watchdog register during a feed sequence. table 666. watchdog operating modes selection wden wdreset mode of operation 0 x (0 or 1) debug/operate without the watchdog running. 1 0 watchdog interrupt mode: the watchdog warning interrupt will be generated but watchdog reset will not. when this mode is selected, the watchdog counter reaching the value specified by wdwarnint will set the wdint flag and the watchdog interrupt request will be generated. 1 1 watchdog reset mode: both the watchdog interrupt and watchdog reset are enabled. when this mode is selected, the watchdog counter reaching the value specified by wdwarnint will set the wdint flag and the watchdog interrupt request will be generated, and the watchdog counter reaching zero will reset the microcontroller. a watchdog feed prior to reaching the value of wdwindow will also cause a watchdog reset. table 667: watchdog timer constant register (tc - address 0x4000 0004) bit description bit symbol description reset value 23:0 count watchdog time-out interval. 0x00 00ff 31:24 - reserved. read value is undefined, only zero should be written. na table 668: watchdog feed register (feed - address 0x4000 0008) bit description bit symbol description 7:0 feed feed value should be 0xaa followed by 0x55.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 796 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.4.4 watchdog timer value register the wdtv register is used to read th e current value of watchdog timer counter. when reading the value of the 24 bit counter, the lock and synchronization procedure takes up to 6 wdclk cycles plus 6 pclk cycles, so the value of wdtv is older than the actual value of the timer when it's being read by the cpu. 31.4.5 watchdog timer warning interrupt register the wdwarnint register de termines the watchdog time r counter value that will generate a watchdog interrupt. when the wa tchdog timer counter matches the value defined by wdwarnint, an interrupt will be generated after the subsequent wdclk. a match of the watchdog timer counter to wdwarnint occurs when the bottom 10 bits of the counter have the same value as the 10 bits of warnint, and the remaining upper bits of the counter are all 0. this gives a maximum time of 1,023 watchdog timer counts (4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. if warnint is set to 0, the interrupt will occur at the same time as the watchdog event. 31.4.6 watchdog timer window register the wdwindow register determines the highest wdtv value allowed when a watchdog feed is performed. if a feed valid sequence completes prior to wdtv reaching the value in wdwindow, a watchdog event will occur. wdwindow resets to the maximum possible wdtv value, so windowing is not in effect. table 669: watchdog timer value register (tv - address 0x4000 000c) bit description bit symbol description reset value 23:0 count counter timer value. 0x00 00ff 31:24 - reserved. read value is undefined, only zero should be written. na table 670: watchdog timer warn ing interrupt register (warnint - address 0x4000 0014) bit description bit symbol description reset value 9:0 warnint watchdog warning interrupt compare value. 0 31:10 - reserved. read value is undefined, only zero should be written. na table 671: watchdog timer window register (window - address 0x4000 0018) bit description bit symbol description reset value 23:0 window watchdog window value. 0xff ffff 31:24 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 797 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.5 watchdog timing examples the following figures illustrate several aspects of watchdog timer op eration is shown below in the figure 158 . fig 158. early watchdog feed with windowed mode enabled 125a 1258 1259 1257 wdclk / 4 watchdog counter early feed event watchdog reset conditions: wdwindow = 0x1200 wdwarnint = 0x3ff wdtc = 0x2000 fig 159. correct watchdog feed with windowed mode enabled correct feed event 1201 11ff 1200 wdclk / 4 watchdog counter watchdog reset 11fc 11fd 2000 1ffe 1fff 11fe 1ffd 1ffc conditions: wdwindow = 0x1200 wdwarnint = 0x3ff wdtc = 0x2000
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 798 of 942 nxp semiconductors UM10562 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) fig 160. watchdog warning interrupt watchdog interrupt 0403 0401 0402 wdclk / 4 watchdog counter 03fe 03ff 03fd 03fb 03fc 0400 03fa 03f9 conditions: wdwindow = 0x1200 wdwarnint = 0x3ff wdtc = 0x2000
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 799 of 942 32.1 basic configuration the adc is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set the pcadc bit. remark: on reset, the adc is disabled. to enab le the adc, first set the pcadc bit, and then enable the adc in the ad0cr register (bit pdn table 674 ). to disable the adc, first clear the pdn bit, and then clear the pcadc bit. 2. peripheral clock: the adc operates from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . to scale the clock for the adc, see bits clkdiv in table 674 . 3. pins: enable adc0 pins and pin modes for the port pins with adc0 functions through the relevant iocon registers ( section 7.4.1 ). 4. interrupts: to enable in terrupts in the adc, see ta b l e 6 7 8 . interrupts are enabled in the nvic using the appropriate interrup t set enable register. disable the adc interrupt in the nvic using the approp riate interrupt set enable register. 5. dma: see section 32.6.4 . for gpdma system connections, see table 692 . 32.2 features ? 12-bit successive approximation analog to digital converter. ? input multiplexing among 8 pins. ? power-down mode. ? measurement range v ss to v refp (typically 3 v; not to exceed v dda voltage level). ? 12-bit conversion rate of 400 khz. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. UM10562 chapter 32: lpc408x/407x anal og-to-digital converter (adc) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 800 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.3 description basic clocking for the a/d converters is provided by the apb clock. a programmable divider is included in each converter to scale this clock to the clock (maximum 12.4 mhz) needed by the successive approximation process. a fully accurate c onversion requires 31 of these clocks. 32.4 pin description table 672 gives a brief summary of each of adc related pins. fig 161. adc block diagram 101217 digital function selection and pin mode controls port controls from iocon registers analog multi- plexer 12- bit adc vdda vssa vrefp power down clock start ready digital functions to/ from other areas ad0[0] ad0[1] ad0[4] ad0[6] ad0[5] ad0[3] ad0[7] ad0[2] clock divider control pclk pconp[pcadc] channel select interrupt request dma request result registers trigger sources: p1[27] p2[10] t0_mat[1] t0_mat[3] t1_mat[0] t1_mat[1] apb bus table 672. adc pin description pin type description ad0[7] to ad0[0] input analog inputs. the adc cell can measure the voltage on any of these input signals. digital signals are disconnected from the adc input pins when the adc function is selected on that pin in the pin select register. warning: if the adc is used, signal levels on analog input pins must not be above the level of v dda at any time. otherwise, a/d converter readings will be invalid. if the a/d converter is not used in an application then the pins associated with a/d inputs can be used as 5 v tolerant digital io pins. v refp reference voltage reference. this pin provides a voltage reference level for the adc and dac. note: v refp should be tied to vdd(3v3) if the adc and dac are not used. v dda , v ssa power analog power and ground. these should typically be the same voltages as v dd and v ss , but should be isolated to minimize noise and error. note: vdda should be tied to vdd(3v3) and vssa should be tied to vss if the adc and dac are not used.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 801 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5 register description [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. table 673. register overview: adc (base address 0x4003 4000) generic name access address offset description reset value [1] table cr r/w 0x000 a/d control register. the adcr register must be written to select the operating mode before a/d conversion can occur. 1 674 gdr r/w 0x004 a/d global data register. this register contains the adc?s done bit and the result of the most recent a/d conversion. na 675 inten r/w 0x00c a/d interrupt enable register. this register contains enable bits that allow the done flag of each a/d channel to be included or excluded from contributing to the generation of an a/d interrupt. 0x100 676 dr0 ro 0x010 a/d channel 0 data register. this register contains the result of the most recent conversion completed on channel 0. na 677 dr1 ro 0x014 a/d channel 1 data register. this register contains the result of the most recent conversion completed on channel 1. na 677 dr2 ro 0x018 a/d channel 2 data register. this register contains the result of the most recent conversion completed on channel 2. na 677 dr3 ro 0x01c a/d channel 3 data register. this register contains the result of the most recent conversion completed on channel 3. na 677 dr4 ro 0x020 a/d channel 4 data register. this register contains the result of the most recent conversion completed on channel 4. na 677 dr5 ro 0x024 a/d channel 5 data register. this register contains the result of the most recent conversion completed on channel 5. na 677 dr6 ro 0x028 a/d channel 6 data register. this register contains the result of the most recent conversion completed on channel 6. na 677 dr7 ro 0x2c a/d channel 7 data register. this register contains the result of the most recent conversion completed on channel 7. na 677 stat ro 0x030 a/d status register. this register contains done and overrun flags for all of the a/d channels, as well as the a/d interrupt/dma flag. 0 678 trm r/w 0x034 adc trim register. 0 679
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 802 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.1 a/d control register table 674: a/d control register (cr - address 0x4003 4000) bit description bit symbol value description reset value 7:0 sel selects which of the ad0[7:0] pins is (are) to be sampled and converted. for ad0, bit 0 selects pin ad0[0], and bit 7 selects pin ad0[7]. in software-controlled mode, only one of these bits should be 1. in hardware scan mode, any value containing 1 to 8 ones is allowed. all zeroes is equivalent to 0x01. 0x01 15:8 clkdiv the apb clock (pclk) is di vided by (this value plus one) to produce the clock for the a/d converter, which should be less than or equal to 12.4 mhz. typically, software should program the smallest value in this field that yields a clock of 12.4 mhz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. 0 16 burst burst mode 0 0 conversions are software controlled and require 31 clocks. 1 the ad converter does repeated conversions at up to 400 khz, scanning (if necessary) through the pins selected by bits set to ones in the sel field. the first conversion after the start corresponds to the least-significant 1 in the sel field, then higher numbered 1-bits (pins) if applicable. repeated conversions can be terminated by clearing this bit, but the conversion that?s in progress when this bit is cleared will be completed. remark: start bits must be 000 when burst = 1 or conversions will not start. 20:17 - reserved. read value is undefined, only zero should be written. na 21 pdn power down mode 0 0 the a/d converter is in power-down mode. 1 the a/d converter is operational. 23:22 - reserved. read value is undefined, only zero should be written. na 26:24 start when the burst bit is 0, these bits control whether and when an a/d conversion is started: 0 0x0 no start (this value should be used when clearing pdn to 0). 0x1 start conversion now. 0x2 start conversion when the edge selected by bit 27 occurs on the p2[10] pin. 0x3 start conversion when the edge selected by bit 27 occurs on the p1[27] pin. 0x4 start conversion when the edge selected by bit 27 occurs on mat0.1. note that this does not require that the mat0.1 function appear on a device pin. 0x5 start conversion when the edge selected by bit 27 occurs on mat0.3. note that it is not possible to cause the mat0.3 function to appear on a device pin. 0x6 start conversion when the edge selected by bit 27 occurs on mat1.0. note that this does not require that the mat1.0 function appear on a device pin. 0x7 start conversion when the edge selected by bit 27 occurs on mat1.1. note that this does not require that the mat1.1 function appear on a device pin. 27 edge this bit is significant only when the start field contains 010-111. in these cases: 0 1 start conversion on a falling edge on the selected cap/mat signal. 0 start conversion on a rising edge on the selected cap/mat signal. 31:28 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 803 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.2 a/d global data register the a/d global data register holds the result of the most recent a/d conversion that has completed, and also includes copies of the status flags that go with that conversion. results of adc conversion can be read in on e of two ways. one is to use the a/d global data register to read all data from the adc. another is to use the a/d channel data registers . it is important to use one method consistently because the done and overrun flags can otherwise get out of synch between the ad0gdr and the a/d channel data register s, potentially causing erroneou s interrupts or dma activity. table 675: a/d global data register (gdr - address 0x4003 4004) bit description bit symbol description reset value 3:0 - reserved. read value is undefined, only zero should be written. na 15:4 result when done is 1, this field contains a bi nary fraction representing the voltage on the ad0[n] pin selected by the sel field, as it falls within the range of v refp to v ss . zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on v ss , while 0xfff indicates that the voltage on the input was close to, equal to, or greater than that on v refp . na 23:16 - reserved. read value is undefined, only zero should be written. na 26:24 chn these bits contain the channel from which the result bits were converted (e.g. 000 identifies channel 0, 001 channel 1...). na 29:27 - reserved. read value is undefined, only zero should be written. na 30 overrun this bit is 1 in burst mode if the result s of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the result bits. this bit is cleared by reading this register. 0 31 done this bit is set to 1 when an a/d conversion co mpletes. it is cleared when this register is read and when the adcr is written. if the adcr is written while a conv ersion is still in progress, this bit is set and a new conversion is started. 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 804 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.3 a/d interrupt enable register this register allows contro l over which a/d channels generate an interrupt when a conversion is complete. for example, it may be desirable to use some a/d channels to monitor sensors by continuously performi ng conversions on them. the most recent results are read by the application program whenever they are needed. in this case, an interrupt is not desirable at the end of each conversion for some a/d channels. table 676: a/d interrupt enable register (inten - address 0x4003 400c) bit description bit symbol value description reset value 0 adinten0 interrupt enable 0 0 completion of a conversion on adc channel 0 will not generate an interrupt. 1 completion of a conversion on adc channel 0 will generate an interrupt. 1 adinten1 interrupt enable 0 0 completion of a conversion on adc channel 1 will not generate an interrupt. 1 completion of a conversion on adc channel 1 will generate an interrupt. 2 adinten2 interrupt enable 0 0 completion of a conversion on adc channel 2 will not generate an interrupt. 1 completion of a conversion on adc channel 2 will generate an interrupt. 3 adinten3 interrupt enable 0 0 completion of a conversion on adc channel 3 will not generate an interrupt. 1 completion of a conversion on adc channel 3 will generate an interrupt. 4 adinten4 interrupt enable 0 0 completion of a conversion on adc channel 4 will not generate an interrupt. 1 completion of a conversion on adc channel 4 will generate an interrupt. 5 adinten5 interrupt enable 0 0 completion of a conversion on adc channel 5 will not generate an interrupt. 1 completion of a conversion on adc channel 5 will generate an interrupt. 6 adinten6 interrupt enable 0 0 completion of a conversion on adc channel 6 will not generate an interrupt. 1 completion of a conversion on adc channel 6 will generate an interrupt. 7 adinten7 interrupt enable 0 0 completion of a conversion on adc channel 7 will not generate an interrupt. 1 completion of a conversion on adc channel 7 will generate an interrupt. 8 adginten interrupt enable 1 0 only the individual adc channels enabled by adinten7:0 will generate interrupts. 1 the global done flag in addr is enabled to generate an interrupt in addition to any individual adc channels that are enabled to generate interrupts. 31:9 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 805 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.4 a/d data registers the a/d data registers hold the result of t he last conversion for each a/d channel, when an a/d conversion is complete. they also include the flags that indicate when a conversion has been completed and when a conversion overrun has occurred. results of adc conversion can be read in on e of two ways. one is to use the a/d global data register to read all data from the a dc. another is to use the a/d channel data registers. it is important to use one method consistently because the done and overrun flags can otherwise get out of synch between the ad0gdr and the a/d channel data registers, potentially causi ng erroneous interrupts or dma activity. table 677: a/d data registers (dr[0:7] - addresses 0x4003 4010 (dr0) to 0x4003 402c (dr7)) bit description bit symbol description reset value 3:0 - reserved. read value is undefined, only zero should be written. na 15:4 result when done is 1, this field contains a binary fraction representing the voltage on the ad0[n] pin, as it falls within the range of v refp to v ss . zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on v ss , while 0xfff indicates that the voltage on the input was close to, equal to, or greater than that on v refp . na 29:16 - reserved. read value is undefined, only zero should be written. na 30 overrun this bit is 1 in burst mode if the result s of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the result bits.this bit is cleared by reading this register. 31 done this bit is set to 1 when an a/d conversion comp letes. it is cleared when this register is read. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 806 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.5 a/d status register the a/d status register allows checking the status of all a/d channels simultaneously. the done and overrun flags appearing in the addrn register for each a/d channel are mirrored in adstat. the interrupt flag (the logical or of all done flags) is also found in adstat. table 678: a/d status register (stat - address 0x4003 4030) bit description bit symbol description reset value 0 done0 this bit mirrors the done status flag from the result register for a/d channel 0. 0 1 done1 this bit mirrors the done status flag from the result register for a/d channel 1. 0 2 done2 this bit mirrors the done status flag from the result register for a/d channel 2. 0 3 done3 this bit mirrors the done status flag from the result register for a/d channel 3. 0 4 done4 this bit mirrors the done status flag from the result register for a/d channel 4. 0 5 done5 this bit mirrors the done status flag from the result register for a/d channel 5. 0 6 done6 this bit mirrors the done status flag from the result register for a/d channel 6. 0 7 done7 this bit mirrors the done status flag from the result register for a/d channel 7. 0 8 overrun0 this bit mirrors the overrrun status flag from the result register for a/d channel 0. 0 9 overrun1 this bit mirrors the overrrun status flag from the result register for a/d channel 1. 0 10 overrun2 this bit mirrors the overrrun status flag from the result register for a/d channel 2. 0 11 overrun3 this bit mirrors the overrrun status flag from the result register for a/d channel 3. 0 12 overrun4 this bit mirrors the overrrun status flag from the result register for a/d channel 4. 0 13 overrun5 this bit mirrors the overrrun status flag from the result register for a/d channel 5. 0 14 overrun6 this bit mirrors the overrrun status flag from the result register for a/d channel 6. 0 15 overrun7 this bit mirrors the overrrun status flag from the result register for a/d channel 7. 0 16 adint this bit is the a/d interrupt flag. it is one when any of the individual a/d channel done flags is asserted and enabled to contribute to the a/d interrupt via the adinten register. 0 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 807 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.5.6 a/d trim register this register will be set by the bootcode on start-up. it contains the trim values for the dac and the adc. the offset trim values for the ad c can be overwritten by the user. all 12 bits are visible when this register is read. table 679: a/d trim register (trm - address 0x4003 4034) bit description bit symbol description reset value 3:0 - reserved. read value is undefined, only zero should be written. na 7:4 adcoffs offset trim bits for adc operation. initializ ed by the boot code. can be overwritten by the user. 0 11:8 trim written-to by boot code. can not be overwritten by the user. these bits are locked after boot code write. 0 31:12 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 808 of 942 nxp semiconductors UM10562 chapter 32: lpc408x/407x analog- to-digital converter (adc) 32.6 operation once an adc conversion is started, it cannot be interrupted. a new software write to launch a new conversion or a new edge-trigger event will be ignored while the previous conversion is in progress. 32.6.1 hardware-triggered conversion if the burst bit in the adcr is 0 and the start field contains 010-111, the adc will start a conversion when a transition occurs on a selected pin or timer match signal. the choices include conversion on a specified edge of any of 4 match signals, or conversion on a specified edge of either of 2 capture/match pins. the pin state from the selected pad or the selected match signal, xored with a dcr bit 27, is used in the edge detection logic. 32.6.2 interrupts an interrupt request is asserted to the nvic when the done bi t is 1. software can use the interrupt enable bit for the a/ d converter in the nvic to control whether this assertion results in an interrupt. done is negated when the addr is read. 32.6.3 accuracy vs. digital receiver the adc function must be selected via the admode bit in the related iocon registers in order to obtain voltage readings on the monitored pin. the same iocon registers should also be set to the mode for which neither pull-up nor pull-down resistor is enabled. for a pin hosting an adc input, it is not possible to have a have a digital function selected and yet get valid adc readings, the analog input is disabled when a digital function is selected on the pin. 32.6.4 dma control a dma transfer request is generated from t he adc interrupt request line. to generate a dma transfer the same conditions must be met as the conditions for generating an interrupt (see section 32.6.2 and section 32.5.3 ). remark: if the dma is used, the adc interr upt must be disabled in the nvic. for dma transfers, only burst requests are suppo rted. the burst size can be set to one in the dma channel control register (see section 35.5.19 ). if the number of adc channels is not equal to one of the other dma-supported burst sizes (applicable dma burst sizes are 1, 4, 8 - see section 35.5.19 ), set the burst size to one. the dma transfer size determines when a dma interrupt is generated. the transfer size can be set to the number of adc channels being converted (see section 35.5.19 ). non-contiguous channels can be transferred by the dma using the scatter/gather linked lists (see section 35.5.18 ).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 809 of 942 33.1 basic configuration the dac is configured using the following registers: 1. power: the dac is always connected to v dda . register access is determined by iocon register settings (see below). 2. peripheral clock: the dac operates from the common pclk that clocks both the bus interface and functi onal portion of most apb peripherals. see section 3.3.3.5 . 3. pins: enable the dac pin and select the pin mode for dacout through the relevant iocon register ( section 7.4.1 ). this must be done before accessing any dac registers. 4. dma: the dac can be connected to the gpdma controller (see section 33.5.2 ). for gpdma connections, see table 692 . 33.2 features ? 10-bit digital to analog converter ? resistor string architecture ? buffered output ? power-down mode ? selectable speed vs. power ? maximum update rate of 1 mhz. UM10562 chapter 33: lpc408x/407x digi tal-to-analog converter (dac) rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 810 of 942 nxp semiconductors UM10562 chapter 33: lpc408x/407x digita l-to-analog converter (dac) 33.3 architecture 33.4 pin description table 680 gives a brief summary of each of dac related pins. fig 162. dac control with dma interrupt and timer cntval counter pre-buffer mux dacr ld ld ld en 16 16 pbus pbus set_intrpt dblbuf_ena cnt_ena ena_cnt_and_dblbuf pbus_wr_to_dacr 1 0 pbus pbus pbus_wr_todacr zero dac value 3 2 1 0 s c set_intrpt pbus pbus_wr_to_dacr dma_ena intrptdma_req table 680. d/a pin description pin type description dac_out output analog output. after the selected settling time after the dacr is written with a new value, the voltage on this pin (with respect to v ssa ) is value ? ((v refp - v refn )/1024) + v refn . note that dac_out is disabled when the cpu is in deep-sleep, power-down, or deep power-down modes. v refp reference voltage reference. this pin provides a voltage reference level for the adc and dac. note: v refp should be tied to vdd(3v3) if the adc and dac are not used. v dda , v ssa power analog power and ground. these should typically be the same voltages as v dd and v ss , but should be isolated to minimize noise and error. note: vdda should be tied to vdd(3v3) and vssa should be tied to vss if the adc and dac are not used.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 811 of 942 nxp semiconductors UM10562 chapter 33: lpc408x/407x digita l-to-analog converter (dac) 33.5 register description note that the dac does not have a control bi t in the pconp register. to enable the dac, its output must be selected to appear on the related pin, p0[26], by configuring the relevant iocon register ( section 7.4.1 ). see section 7.4.1 ? i/o configuration register contents (iocon) ? . the dac must be enabled in this manner prior to accessing any dac registers. [1] reset value reflects the data stored in used bits only. it does not include reserved bits content. 33.5.1 d/a converter register this read/write register includes the digital value to be converted to analog, and a bit that trades off performance vs. power. bits 5:0 ar e reserved for future, higher-resolution d/a converters. 33.5.2 d/a converter control register this read/write register enables the dm a operation and controls the dma timer. table 681. register overview : dac (base address 0x4008 c000) name access address offset description reset value [1] table cr r/w 0x000 d/a converter register. this register contains the digital value to be converted to analog and a power control bit. 0 682 ctrl r/w 0x004 dac control register. this register controls dma and timer operation. 0 683 cntval r/w 0x008 dac counter value register. this register contains the reload value for the dac dma/interrupt timer. 0 684 table 682: d/a converter register (cr - address 0x4008 c000) bit description bit symbol value description reset value 5:0 - reserved. read value is undefined, only zero should be written. na 15:6 value after the selected settling time after this field is written with a new value, the voltage on the dac_out pin (with respect to v ssa ) is value ? ((v refp - v refn )/1024) + v refn . 0 16 bias settling time the settling times noted in the description of the bias bit are valid for a capacitance load on the dac_out pin not exceeding 100 pf. a load impedance value greater than that value will cause settling time longer than the specified time. one or more graphs of load impedance vs. settling time will be included in the final data sheet. 0 0 the settling time of the dac is 1 ? s max, and the maximum current is 700 ? a. this allows a maximum update rate of 1 mhz. 1 the settling time of the dac is 2.5 ? s and the maximum current is 350 ? a. this allows a maximum update rate of 400 khz. 31:17 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 812 of 942 nxp semiconductors UM10562 chapter 33: lpc408x/407x digita l-to-analog converter (dac) 33.5.3 d/a converter counter value register this read/write register contains the reload value for the interrupt/dma counter. table 683. d/a control register (ctrl - address 0x4008 c004) bit description bit symbol value description reset value 0 int_dma_req dma interrupt request 0 0 clear on any write to the dacr register. 1 set by hardware when the timer times out. 1 dblbuf_ena double buffering 0 0 disable 1 enable. when this bit and the cnt_ena bit are both set, the double-buffering feature in the dacr register will be enabled. writes to the dacr register are written to a pre-buffer and then transferred to the dacr on the next time-out of the counter. 2 cnt_ena time-out counter operation 0 0 disable 1 enable 3 dma_ena dma access 0 0 disable 1 enable. dma burst request input 7 is enabled for the dac (see table 692 ). 31:4 - reserved. read value is undefined, only zero should be written. na table 684: d/a converter counter value register (cntval - address 0x4008 c008) bit description bit symbol description reset value 15:0 value 16-bit reload value for the dac interrupt/dma timer. 0 31:16 - reserved -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 813 of 942 nxp semiconductors UM10562 chapter 33: lpc408x/407x digita l-to-analog converter (dac) 33.6 operation 33.6.1 dma counter when the counter enab le bit cnt_ena in dacctrl is set, a 16-bit counter will begin counting down, at the rate selected by pclk (see section 3.3.3.5 ), from the value programmed into the daccntval register. the counter is decremented each time the counter reaches zero, the counter will be reloaded by the value of daccntval and the dma request bit int_dma_req will be set in hardware. note that the contents of the dacctrl and daccntval registers are read and write accessible, but the timer itself is not accessible for either read or write. if the dma_ena bit is set in the dacctrl re gister, the dac dma re quest will be routed to the gpdma. when the dma_ena bit is cleared, the default state after a reset, dac dma requests are blocked. 33.6.2 double buffering double-buffering is enabled only if both, the cnt_ena and the dblbuf_ena bits are set in dacctrl. in this case, an y write to the dacr register will only load the pre-buffer, which shares its register address with the da cr register. the dacr itself will be loaded from the pre-buffer whenever the counter reache s zero and the dma request is set. at the same time the counter is reloaded with the countval register value. reading the dacr register will on ly return the contents of the dacr register itself, not the contents of the pre-buffer register. if either the cnt_ena or the dblbuf_ena bits are 0, any writes to the dacr address will go directly to the dacr register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 814 of 942 34.1 how to read this chapter remark: the comparator function is not available on lpc4074 devices. 34.2 basic configuration the comparator block is configur ed using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pccmp. remark: on reset, the comparators are disabled (pccmp = 0). 2. peripheral clock: the comparator block operates from the common pclk that clocks both the bus interface and functional portion of most apb peripherals. see section 3.3.3.5 . 3. pins: select comparator pins and pin modes through the relevant iocon registers ( section 3.3.2.2 ). 4. interrupts: if comparator in terrupts are used, they must be configured in the cmp_ctrl0 and/or cmp_ct rl1 registers, see ta b l e 6 8 8 and table 689 . interrupts are enabled in the nvic using the appropriate interrupt set enable register. 34.3 features ? up to 5 selectable external sources per comparator; fully configurable on either positive or negative co mparator input channels. ? 0.9 v internal bandgap reference voltage se lectable as either positive or negative input on each comparator. ? 32-stage voltage ladder internal reference for selectable voltages on each comparator; configurable on either po sitive or negative comparator input. ? voltage ladder source voltage is selectable from an external pin or the 3.3 v analog voltage supply. ? voltage ladder can be separately powered down for applications only requiring the comparator function. ? relaxation oscillator circuitry output, for a 555 style timer operation. ? individual comparator outputs can be connected to i/o pins. ? separate interrupt for each comparator. ? edge and level comparator outputs connect to two timers allowing edge counting while a level match has been asserted, or me asuring the time between 2 voltage trip points. UM10562 chapter 34: lpc408x/407x comparators rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 815 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.4 architecture two embedded comparators are incorporated on -chip to compare the voltage levels on external pins or against internal voltages (see figure 163 ). up to 4 voltages on external pins and several internal reference voltages are selectable on each comparator. additionally, two of the external inputs can be selected to drive an input common on both comparators.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 816 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators fig 163.comparator block diagram 120905 cmp0_in[3] cmp0_in[2] cmp0_in[1] cmp0_in[0] cmp0_vp 0.9v bandgap reserved cmp1_in[3] cmp1_in[2] cmp1_in[1] cmp1_in[0] 0 1 2 3 4 5 6 7 0.9v bandgap reserved 0 1 2 3 4 5 6 7 cmp_vref vsel0 cmp_rosc cmp_roscctl cmp0_hys vlad0ref vdda vlad0en + - + - 0 1 0 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 cmp0_vm cmp1_vp cmp1_vm vlad1ref cmp0_en cmp0_oe cmp1_oe cmp1_hys cmp1_en cmp0_stat cmp1_stat vsel1 vlad1en cmp0 cmp1 cmp_reset chip_reset cmp_ext_reset 0 1 s rq clr s rq clr cmp0_edge cmp0_level cmp0_out cmp0_sync 0 1 synchro- nizer edge detect cmp0_intedge cmp0_intpol cmp0_inttype cmp0_intclr cmp0 int logic cmp0_int cmp1_edge cmp1_level cmp1_out cmp1_sync 0 1 synchro- nizer edge detect cmp1_intedge cmp1_intpol cmp1_int_type cmp1_intclr cmp1 int logic cmp1_int vref0 vref1 cmp0_wake cmp1_wake vref divider 1 vref divider 0
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 817 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.5 pin description 34.6 register description [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 685: comparator pin description pin type description cmp0_in[3:0] input comparator 0 input sources (cmp10in[0] can also be selected as a comparator 1 input) cmp1_in[3:0] input comparator 1 input sources (cmp1_in[0] can also be selected as a comparator 0 input). cmp0_out output comparator 0 output cmp1_out output comparator 1 output cmp_vref input external reference voltage source for 32-stage voltage ladder cmp_rosc output relaxation oscillator output, intended for 555 timer style applications cmp_reset input reset to the cmp_rosc generation logic. table 686. register overview: comparator (base address 0x4002 0000) name access address offset description reset value [1] table cmp_ctrl r/w 0x000 comparator block control register 0 687 cmp_ctrl0 r/w 0x004 comparator 0 control register 0 688 cmp_ctrl1 r/w 0x008 comparator 1 control register 0 689
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 818 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.6.1 comparator bl ock control register this register controls aspects of the comp arator block that apply to both comparators. table 687. comparator block control register (cmp_ctrl - address 0x4002 0000) bit description bit symbol value description reset value 1:0 cmp_pd_iref controls the current source used by the comparators. the current source must be enabled when either comparator is used. when just enabled, time must be allowed for the current source to stabilize before all comparator functions will operate as expected. 00 0x0 the comparator curr ent source is disabled. 0x1 the comparator current source is disabled in deep sleep and power-down modes and restored automatically when exiting those modes. 0x2 the comparator current source is di sabled in power-down mode and restored automatically when exiting power-down. 0x3 the comparator current source is powered up. 3:2 cmp_pd_vbg controls the bandgap reference source that is used by the comparators. the reference must be enabled when used by either comparator. 00 0x0 the comparator bandgap reference is disabled. 0x1 the comparator bandgap reference is disabled in deep sleep and power-down modes and restored automatically when exiting those modes. 0x2 the comparator bandgap reference is disabled in power-down mode and restored automatically when exiting power-down. 0x3 the comparator bandgap reference is powered up. 7:4 - reserved. na 8 cmp_roscctl selects the inputs for the flip/flops that provide the cmp_rosc output. 0 0 the cmp_rosc output is set by cmp1 and reset by cmp0. 1 the cmp_rosc output is set by cmp0 and reset by cmp1. 9 cmp_ext_reset selects the reset source for the cmp_rosc output. 0 0 the cmp_rosc output is reset by the internal chip reset. 1 the cmp_rosc output is re set by the cmp_reset input. 11:10 - reserved. na 12 cmp_t0cap2 selects the input for timer 0 capture input 2. 0 0 t0cap2 is connected to comparator 0 level output. 1 t0cap2 is connected to comparator 1 level output. 13 cmp_t0cap3 selects the input for timer 0 capture input 3. 0 0 t0cap3 is connected to comparator 0 edge output. 1 t0cap3 is connected to comparator 1 edge output. 14 cmp_t1cap2 selects the input for timer 1 capture input 2. 0 0 t1cap2 is connected to comparator 1 edge output. 1 t1cap2 is connected to comparator 0 level output. 15 cmp_t1cap3 selects the input for timer 1 capture input 3. 0 0 t1cap3 is connected to comparator 1 level output. 1 t1cap3 is connected to comparator 0 edge output. 31:16 - reserved. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 819 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.6.2 comparator 0 control register this register enables and configures ma ny aspects of comparator 0 operation. table 688. comparator 0 control register (cmp_ctrl0 - address 0x4002 0004) bit description bit symbol value description reset value 1:0 cmp0_en comparator 0 enable control. 00 0x0 comparator 0 disabled. 0x1 comparator 0 is disabled in deep sleep and power-down modes and re-enabled automatically when exiting those modes. 0x2 comparator 0 is disabled in power-down mode and re-enabled automatically when exiting power-down. 0x3 comparator 0 is enabled. 2 cmp0_oe comparator 0 output enable. if deep sleep or power-down mode is entered, this bit will be cleared when the device wakes up again. 0 0 comparator 0 output is disabled. 1 comparator 0 output is enabled. 3 cmp0_stat comparator 0 status. this bit reflects the comparator 0 output, and is not affected by cmp0_oe. 0 6:4 cmp0_vm comparator 0 vm input select. 000 0x0 vref divider 0. 0x1 cmp0_in[0]. 0x2 cmp0_in[1]. 0x3 cmp0_in[2]. 0x4 cmp0_in[3]. 0x5 cmp1_in[0]. 0x6 internal 0.9 v band gap reference. 0x7 reserved. 7 - reserved. na 10:8 cmp0_vp comparator 0 vp input select. 000 0x0 vref divider 0. 0x1 cmp0_in[0]. 0x2 cmp0_in[1]. 0x3 cmp0_in[2]. 0x4 cmp0_in[3]. 0x5 cmp1_in[0]. 0x6 internal 0.9 v band gap reference. 0x7 reserved. 11 - reserved. na 12 cmp0_sync comparator 0 output synchronization control. 0 0 the comparator 0 output is used directly. 1 the comparator 0 output is synchronized with the internal bus clock for output to other peripherals.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 820 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 14:13 cmp0_hys comparator 0 hysteresis control. when enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. the difference must be in the direction opposite of the current comparator output. 00 0x0 hysteresis is turned off, comparator output will change as the input voltages cross. 0x1 hysteresis = 5 mv. 0x2 hysteresis = 10 mv. 0x3 hysteresis = 15 mv. 15 cmp0_intpol selects the polarity of the cm p0 output for purposes of generating level interrupts. see table 690 . 0 0 the cmp0 output is used as-is for generating interrupts. 1 the cmp0 output is used inverted for generating interrupts. 16 cmp0_inttype select comparator 0 interrupt type. see table 690 .0 0 comparator 0 interrupt is edge triggered. 1 comparator 0 interrupt is level triggered. 18:17 cmp0_intedge select edge triggered interrupt to be active on either high or low transitions, when cmp0_inttype = 0. see ta b l e 6 9 0 . 0 0x0 comparator 0 interrupt is active on falling edges. 0x1 comparator 0 interrupt is active on rising edges. 0x2 comparator 0 interrupt is active on both edges. 0x3 reserved. 19 cmp0_intflag comparator 0 interrupt flag. 0 0 the comparator 0 interrupt is not pending. 1 the comparator 0 interrupt is pending. writing a 1 to this bit clears the flag. 21:20 cmp0_vladen voltage ladder enable for comparator 0. 00 0x0 the comparator 0 voltage ladder is disabled. 0x1 the comparator 0 voltage ladder is disabled in deep sleep and power-down modes and re-enabled automatically when exiting those modes. 0x2 the comparator 0 voltage ladder is disabled in power-down mode and re-enabled automatically when exiting power-down. 0x3 the comparator 0 voltage ladder is enabled. 22 cmp0_vladref voltage reference select for comparator 0 voltage ladder. 0 0vref_cmp pin. 1v dda pin. table 688. comparator 0 control register (cmp_ctrl0 - address 0x4002 0004) bit description ?continued bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 821 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 23 - reserved. na 28:24 cmp0_vsel voltage ladder value for comparator 0. the reference voltage vref depends on the setting of cmp0_vladref (either v dd(3v3) or voltage on pin vref_cmp). 00000 = vss. 00001 = 1 ? vref0 / 31. 00010 = 2 ? vref0 / 31. ... 11111 = vref0 0x00 31:29 - reserved. na table 688. comparator 0 control register (cmp_ctrl0 - address 0x4002 0004) bit description ?continued bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 822 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.6.3 comparator 1 control register this register enables and configures ma ny aspects of comparator 1 operation. table 689. comparator 1 control register (cmp_ctrl1 - 0x4002 0008) bit description bit symbol value description reset value 1:0 cmp1_en comparator 1 enable control. 00 0x0 comparator 1 disabled. 0x1 comparator 1 is disabled in deep sleep and power-down modes and re-enabled automatically when exiting those modes. 0x2 comparator 1 is disabled in power-down mode and re-enabled automatically when exiting power-down. 0x3 comparator 1 is enabled. 2 cmp1_oe comparator 1 output enable. if deep sleep or power-down mode is entered, this bit will be cleared when the device wakes up again. 0 0 comparator 1 output is disabled. 1 comparator 1 output is enabled. 3 cmp1_stat comparator 1 status. this bit reflects the comparator 1 output, and is not affected by cmp1_oe. 0 6:4 cmp1_vm comparator 1 vm input select. 000 0x0 vref divider 1. 0x1 cmp1_in[0]. 0x2 cmp1_in[1]. 0x3 cmp1_in[2]. 0x4 cmp1_in[3]. 0x5 cmp0_in[0]. 0x6 internal 0.9 v band gap reference. 0x7 reserved. 7 - reserved. na 10:8 cmp1_vp comparator 1 vp input select. 000 0x0 vref divider 0. 0x1 cmp1_in[0]. 0x2 cmp1_in[1]. 0x3 cmp1_in[2]. 0x4 cmp1_in[3]. 0x5 cmp0_in[0]. 0x6 internal 0.9 v band gap reference. 0x7 reserved. 11 - reserved. na 12 cmp1_sync comparator 1 output synchronization control. 0 0 the comparator 1 output is used directly. 1 the comparator 1 output is synchronized with the internal bus clock for output to other peripherals.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 823 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 14:13 cmp1_hys comparator 1 hysteresis contro l. when enabled, hysteresis determines the difference required between the comparator inputs before the comparator output switches. the difference must be in the direction opposite of the current comparator output. 00 0x0 hysteresis is turned off, comparator output will change as the input voltages cross. 0x1 hysteresis = 5 mv. 0x2 hysteresis = 10 mv. 0x3 hysteresis = 15 mv. 15 cmp1_intpol selects the polarity of the cm p1 output for purposes of generating level interrupts. see table 690 . 0 0 the cmp1 output is used as-is for generating interrupts. 1 the cmp1 output is used inverted for generating interrupts. 16 cmp1_inttype select comparator 1 interrupt type. see table 690 .0 0 comparator 1 interrupt is edge triggered. 1 comparator 1 interrupt is level triggered. 18:17 cmp1_intedge select edge triggered interrupt to be active on either high or low transitions, when cmp1_inttype = 0. see table 690 . 0 0x0 comparator 1 interrupt is active on falling edges. 0x1 comparator 1 interrupt is active on rising edges. 0x2 comparator 1 interrupt is active on both edges. 0x3 reserved. 19 cmp1_intflag comparator 1 interrupt flag. 0 0 the comparator 1 interrupt is not pending. 1 the comparator 1 interrupt is pending. writing a 1 to this bit clears the flag. 21:20 cmp1_vladen voltage ladder enable for comparator 1. 00 0x0 the comparator 1 voltage ladder is disabled. 0x1 the comparator 1 voltage ladder is disabled in deep sleep and power-down modes and re-enabled automatically when exiting those modes. 0x2 the comparator 1 voltage ladder is disabled in power-down mode and re-enabled automatically when exiting power-down. 0x3 the comparator 1 voltage ladder is enabled. 22 cmp1_vladref voltage reference select for comparator 1 voltage ladder. 0 0 vref_cmp pin. 1v dda pin. table 689. comparator 1 control register (cmp_ctrl1 - 0x4002 0008) bit description ?continued bit symbol value description reset value
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 824 of 942 nxp semiconductors UM10562 chapter 34: lpc408x/407x comparators 34.6.4 comparator interrupt configurations [1] the same signal goes to timer 0 and 1 (see table 687 , bits 12 through 15) [2] the same signal goes to the wake-up logic. [3] cmpn_intpol has no effect on the comparator interrupt, but can separately select a wake-up polarity. [4] cmpn_intedge has no effect on the comparator interr upt, but can separately select the signal that goes to a timer from the edge output. 23 - reserved. na 28:24 cmp1_vsel voltage ladder value for comparator 1. the reference voltage vref depends on the setting of cmp1_vladref (either v dd(3v3) or voltage on pin vref_cmp). 00000 = vss. 00001 = 1 ? vref1 / 31. 00010 = 2 ? vref1 / 31. ... 11111 = vref1. 0x00 31:29 - reserved. na table 689. comparator 1 control register (cmp_ctrl1 - 0x4002 0008) bit description ?continued bit symbol value description reset value table 690: interrupt configurations intedge inttype intpol interrupt function 00 0 see table note [3] falling edge interrupt. see table note [1] 01 0 see table note [3] rising edge interrupt. see table note [1] 1x 0 see table note [3] interrupt on both edges. see table note [1] see table note [4] 1 0 high level interrupt. see table note [2] see table note [4] 1 1 low level interrupt. see table note [2]
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 825 of 942 35.1 basic configuration the gpdma is configured using the following registers: 1. power: in the pconp register ( section 3.3.2.2 ), set bit pcgpdma. remark: on reset, the gpdma is disabled (pcgpdma = 0). 2. clock: the gpdma operates at the ahb bus rate, which is the same as the cpu clock rate (cclk). 3. interrupts: inte rrupts are enabled in the nvic using the appropriate interrupt set enable register. 4. programming: see section 35.6 . 5. select the dma channel alternate requests in the dma channel request select register in the system control block. see section 3.3.7.6 . 35.2 introduction the dma controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions . each dma stream provides unidirectional serial dma transfers for a single source and destination. for example, a bidirectional port requires one stream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral. UM10562 chapter 35: lpc408x/407x gene ral purpose dm a controller rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 826 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.3 features ? eight dma channels. each channel can support one unidir ectional transfer. ? 16 dma request lines. ? memory-to-memory, memory-to- peripheral, and peripheral -to-memory transfers are supported. ? gpdma supports the sd card interface, all ssps, the i 2 s, all uarts, the a/d converter, and the d/a converter peripherals. dma can also be triggered by selected timer match conditions. memory -to-memory transfers and tr ansfers to or from gpio are also supported. ? scatter or gather dma is sup ported through the use of lin ked lists. this means that the source and destination areas do not hav e to occupy contiguous areas of memory. ? hardware dma ch annel priority. ? ahb slave dma programming interface. the dma controller is programmed by writing to the dma control registers over the ahb slave interface. ? one ahb bus master for transferring data. the interface transfers data when a dma request goes active. ? 32-bit ahb master bus width. ? incrementing or non-incrementing addressing for source and destination. ? programmable dma burst size. the dma burst size can be programmed to more efficiently transfer data. ? internal four-word fifo per channel. ? supports 8-bit, 16-bit, and 32-bit wide transactions. ? big-endian and little-endian support. the dma controller defaults to little-endian mode on reset. ? an interrupt to the processor can be generated on a dma completion or when a dma error has occurred. ? raw interrupt status. the dma error and dma count raw interrupt status can be read prior to masking. ? dma can operate in sleep mode. (note that in sleep mode the gpdma cannot access the flash memory or the main sram).
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 827 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.4 functional description this section describes the major functional blocks of the dma controller. 35.4.1 dma controller functional description the dma controller enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. each dma stream provides unidirectional serial dma transfer s for a single source and destination. for example, a bidirectional port requires one stream for transmit and one for receive. the source and destination areas can each be either a memory region or a peripheral, and can be accessed through the ahb master. figure 164 shows a block diagram of the dma controller. the functions of the dma controller are described in the following sections. 35.4.1.1 ahb slave interface all transactions to dma contro ller registers on the ahb slave interface are 32 bits wide. 8-bit and 16-bit accesses are not suppor ted and will result in an exception. 35.4.1.2 control logic and register bank the register block stores data written or to be read across the ahb interface. 35.4.1.3 dma request and response interface see section 35.4.2 for information on the dma request and response interface. 35.4.1.4 channel logic and channel register bank the channel logic and channel register bank c ontains registers and logic required for each dma channel. fig 164. dma controller block diagram gpdma ahb slave interface control logic and registers dma request and response interface channel logic and registers interrupt request dma requests dma responses dma interrupts ahb bus ahb master interface ahb bus
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 828 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.4.1.5 interrupt request the interrupt request generates th e interrupt to the arm processor. 35.4.1.6 ahb master interface the dma controller contains one ahb master interface. the ahb master is capable of dealing with all types of ahb transactions, including: ? split, retry, and error responses from slaves. if a peripheral performs a split or retry, the dma controller stalls and waits until the transaction can complete. ? locked transfers for source and destination of each stream. ? setting of protection bits for transfers on each stream. 35.4.1.6.1 bus and transfer widths the physical width of the ahb bus is 32 bits. source and destination transfers can be of differing widths and can be the same width or narrower than the physical bus width. the dma controller packs or unpacks data as appropriate. 35.4.1.6.2 endian behavior the dma controller can cope with both little-endian and big-endian addressing. internally the dma contro ller treats all data as a stream of bytes instead of 16-bit or 32-bit quantities. this means that when performing mixed-endian activity, where the endianness of the source and destination are different, by te swapping of the data within the 32-bit data bus is observed. note: if byte swapping is not required, then use of different endianness between the source and destination addresses must be avoided. table 691 shows endian behavior for different source and destination combinations. table 691. endian behavior source endian destination endian source width destination width source transfer no/byte lane source data destination transfer no/byte lane destination data little little 8 8 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21 43 65 87 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21212121 43434343 65656565 87878787 little little 8 16 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21 43 65 87 1/[15:0] 2/[31:16] 43214321 87658765 little little 8 32 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21 43 65 87 1/[31:0] 87654321
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 829 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller little little 16 8 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 21 43 65 87 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21212121 43434343 65656565 87878787 little little 16 16 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 21 43 65 87 1/[15:0] 2/[31:16] 43214321 87658765 little little 16 32 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24] 21 43 65 87 1/[31:0] 87654321 little little 32 8 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] 21 43 65 87 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24] 21212121 43434343 65656565 87878787 little little 32 16 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] 21 43 65 87 1/[15:0] 2/[31:16] 43214321 87658765 little little 32 32 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24] 21 43 65 87 1/[31:0] 87654321 big big 8 8 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12 34 56 78 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12121212 34343434 56565656 78787878 big big 8 16 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12 34 56 78 1/[15:0] 2/[31:16] 12341234 56785678 big big 8 32 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12 34 56 78 1/[31:0] 12345678 big big 16 8 1/[31:24] 1/[23:16] 2/[15:8] 2 /[7:0 ] 12 34 56 78 1/ [31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12121212 34343434 56565656 78787878 table 691. endian behavior ?continued source endian destination endian source width destination width source transfer no/byte lane source data destination transfer no/byte lane destination data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 830 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.4.1.6.3 error conditions an error during a dma transfer is flagged directly by the peripheral by asserting an error response on the ahb bus during the transfer. the dma controller automatically disables the dma stream after the current transfer has completed, and can optionally generate an error interrupt to the cpu. this error interrupt can be masked. 35.4.1.7 channel hardware each stream is supported by a dedicated hardware channel, including source and destination controllers, as well as a fifo. this enables better latency than a dma controller with only a single hardware channel shared between several dma streams and simplifies the control logic. 35.4.1.8 dma request priority dma channel priority is fixed. dma channel 0 has the highest priority and dma channel 7 has the lowest priority. if the dma controller is transferring data for th e lower priority channel and then the higher priority channel goes active, it completes the number of transfers delegated to the master interface by the lower priority channel before sw itching over to transfer data for the higher priority channel. transfers delegated to the master interface are staged in the dma channel fifo, so the amount of data that ne eds to transfer could be as large as a 4 words. big big 16 16 1/[31:24] 1/[23:16] 2/[15:8] 2/[7:0] 12 34 56 78 1/[15:0] 2/[31:16] 12341234 56785678 big big 16 32 1/[31:24] 1/[23:16] 2/[15:8] 2/[7:0] 12 34 56 78 1/[31:0] 12345678 big big 32 8 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] 12 34 56 78 1/[31:24] 2/[23:16] 3/[15:8] 4/[7:0] 12121212 34343434 56565656 78787878 big big 32 16 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] 12 34 56 78 1/[15:0] 2/[31:16] 12341234 56785678 big big 32 32 1/[31:24] 1/[23:16] 1/[15:8] 1/[7:0] 12 34 56 78 1/[31:0] 12345678 table 691. endian behavior ?continued source endian destination endian source width destination width source transfer no/byte lane source data destination transfer no/byte lane destination data
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 831 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller it is recommended that memory -to-memory transactions use th e lowest priority channel. 35.4.1.9 interrupt generation a combined interrupt output is generated as an or function of the individual interrupt requests of the dma controller and is connected to the interrupt controller. 35.4.2 dma system connections 35.4.2.1 dma request signals the dma request signals are used by peripherals to request a data transfer. the dma request signals indicate whether a single or burst transfer of data is required. the dma available request signals are: dmacbreq[15:0] ? burst request signals. these cause a programmed burst number of data to be transferred. dmacsreq[15:0] ? single transfer request signals. these cause a single data to be transferred. the dma controller transfers a single transfer to or from the peripheral. dmaclbreq[15:0] ? last burst request signals. dmaclsreq[15:0] ? last single transfer request signals. note that most peripherals do not support ?l ast? request types, and many peripherals do not support the single request type. see section 35.4.2.3 . 35.4.2.2 dma response signals the dma response signals indicate whether the transfer initiated by the dma request signal has completed. the response signals can also be used to indicate whether a complete packet has been transferred. the dma response signals from the dma controller are: dmacclr[15:0] ? dma clear or acknowledge signals. the dmacclr signal is used by the dma controller to acknowledge a dma request from the peripheral. dmactc[15:0] ? dma terminal count signals. the dmactc signal can be used by the dma controller to indicate to the peripheral that the dma transfer is complete. 35.4.2.3 dma request connections the connection of the gpdma to the support ed peripheral devices depends on the dma functions implemented in those peripherals. table 692 shows the dma request numbers used by the supported peripherals. alternativ e requests on channels 0 through 7 and 10 through 15 are chosen via the dmareqsel register, see section 3.3.7.6 . table 692. dma connections dma request burst request single request last burst request last single request comment 0 (unused) / t0_mat[0] - - - dedicated dma request 1 sd card / t0_mat[1] sd card only sd card only sd card only dedicated dma request 2 ssp0 tx / t1_mat[0] ssp0 tx only - - dedicated dma request 3 ssp0 rx / t1_mat[1] ssp0 rx only - - dedicated dma request 4 ssp1 tx / t2_mat[0] ssp1 tx only - - dedicated dma request
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 832 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller [1] generates an interrupt and/or dma request depending on software setup. 5 ssp1 rx / t2_mat[1] ssp1 rx only - - dedicated dma request 6 ssp2 tx / i 2 s channel 0 ssp2 tx only - - dedicated dma request 7 ssp2 rx / i 2 s channel 1 ssp2 rx only - - dedicated dma request 8 adc - - - adc interrupt request [1] 9 dac - - - dedicated dma request 10 uart0 tx / uart3 tx - - - dedicated dma request 11 uart0 rx / uart3 rx - - - dedicated dma request 12 uart1 tx / uart4 tx - - - dedicated dma request 13 uart1 rx / uart4 rx - - - dedicated dma request 14 uart2 tx / t3_mat[0] - - - dedicated dma request 15 uart2 rx / t3_mat[1] - - - dedicated dma request table 692. dma connections dma request burst request single request last burst request last single request comment
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 833 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5 register description the dma controller supports 8 channels. each channel has registers specific to the operation of that channel. ot her registers controls aspects of how source peripherals relate to the dma controller. there are also global dma control and status registers. the dma controller registers are shown in table 693 . in addition, the dma request select register is located in the system control block. see section 3.3.7.6 . table 693. register overview: gpdma (base address 0x2008 0000) name access address offset description reset value table general registers intstat ro 0x000 dma interrupt status register 0 694 inttcstat ro 0x004 dma interrupt terminal count request status register 0 695 inttcclear wo 0x008 dma interrupt terminal count request clear register - 696 interrstat ro 0x00c dma interrupt error status register 0 697 interrclr wo 0x010 dma interrupt error clear register - 698 rawinttcstat ro 0x014 dma raw interrupt terminal count status register 0 699 rawinterrstat ro 0x018 dma raw error interrupt status register 0 700 enbldchns ro 0x01c dma enabled channel register 0 701 softbreq r/w 0x020 dma software burst request register 0 702 softsreq r/w 0x024 dma software single request register 0 703 softlbreq r/w 0x028 dma software last burst request register 0 704 softlsreq r/w 0x02c dma software last single request register 0 705 config r/w 0x030 dma configuration register 0 706 sync r/w 0x034 dma synchronization register 0 707 channel 0 registers srcaddr0 r/w 0x100 dma channel 0 source address register 0 708 destaddr0 r/w 0x104 dma channel 0 destination address register 0 709 lli0 r/w 0x108 dma channel 0 linked list item register 0 710 control0 r/w 0x10c dma channel 0 control register 0 711 config0 r/w 0x110 dma channel 0 configuration register [1] 0 712 channel 1 registers srcaddr1 r/w 0x120 dma channel 1 source address register 0 708 destaddr1 r/w 0x124 dma channel 1 destination address register 0 709 lli1 r/w 0x128 dma channel 1 linked list item register 0 710 control1 r/w 0x12c dma channel 1 control register 0 711 config1 r/w 0x130 dma channel 1 configuration register [1] 0 712 channel 2 registers srcaddr2 r/w 0x140 dma channel 2 source address register 0 708 destaddr2 r/w 0x144 dma channel 2 destination address register 0 709 lli2 r/w 0x148 dma channel 2 linked list item register 0 710 control2 r/w 0x14c dma channel 2 control register 0 711 config2 r/w 0x150 dma channel 2 configuration register [1] 0 712
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 834 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller [1] bit 17 of this register is a read-only status flag. channel 3 registers srcaddr3 r/w 0x160 dma channel 3 source address register 0 708 destaddr3 r/w 0x164 dma channel 3 destination address register 0 709 lli3 r/w 0x168 dma channel 3 linked list item register 0 710 control3 r/w 0x16c dma channel 3 control register 0 711 config3 r/w 0x170 dma channel 3 configuration register [1] 0 712 channel 4 registers srcaddr4 r/w 0x180 dma channel 4 source address register 0 708 destaddr4 r/w 0x184 dma channel 4 destination address register 0 709 lli4 r/w 0x188 dma channel 4 linked list item register 0 710 control4 r/w 0x18c dma channel 4 control register 0 711 config4 r/w 0x190 dma channel 4 configuration register [1] 0 712 channel 5 registers srcaddr5 r/w 0x1a0 dma channel 5 source address register 0 708 destaddr5 r/w 0x1a4 dma channel 5 destination address register 0 709 lli5 r/w 0x1a8 dma channel 5 linked list item register 0 710 control5 r/w 0x1ac dma channel 5 control register 0 711 config5 r/w 0x1b0 dma channel 5 configuration register [1] 0 712 channel 6 registers srcaddr6 r/w 0x1c0 dma channel 6 source address register 0 708 destaddr6 r/w 0x1c4 dma channel 6 destination address register 0 709 lli6 r/w 0x1c8 dma channel 6 linked list item register 0 710 control6 r/w 01cc dma channel 6 control register 0 711 config6 r/w 0x1d0 dma channel 6 configuration register [1] 0 712 channel 7 registers srcaddr7 r/w 0x1e0 dma channel 7 source address register 0 708 destaddr7 r/w 0x1e4 dma channel 7 destination address register 0 709 lli7 r/w 0x1e8 dma channel 7 linked list item register 0 710 control7 r/w 0x1ec dma channel 7 control register 0 711 config7 r/w 0x1f0 dma channel 7 configuration register [1] 0 712 table 693. register overview: gpdma (base address 0x2008 0000) name access address offset description reset value table
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 835 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.1 dma interrupt status register the dmacintstat register is read-only and shows the status of the interrupts after masking. a 1 bit indicates that a specific dma channel interrupt request is active. the request can be generated from either the er ror or terminal count interrupt requests. table 694 shows the bit assignments of the dmacintstat register. 35.5.2 dma interrupt terminal co unt request status register the dmacinttcstat register is read-only and indicates the status of the terminal count after masking. table 695 shows the bit assignments of the dmacinttcstat register. 35.5.3 dma interrupt terminal count request clear register the dmacinttcclear register is write-only and clears one or more terminal count interrupt requests. when writing to this register, each data bit that contains a 1 causes the corresponding bit in the status register (dmaci nttcstat) to be cleared. data bits that are 0 have no effect. table 696 shows the bit assignments of the dmacinttcclear register. 35.5.4 dma interrupt error status register the dmacinterrstat register is read-only an d indicates the status of the error request after masking. table 697 shows the bit assignments of the dmacinterrstat register. table 694. dma interrupt status register (intstat, address 0x2008 0000) bit description bit symbol description 7:0 intstat status of dma channel interrupts after masking. each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request. 31:8 - reserved. the value read from a reserved bit is not defined. table 695. ma interrupt terminal count request status register (inttcstat, address 0x2008 0004) bit description bit symbol description 7:0 inttcstat terminal count interrupt request status for dma channels. each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. 31:8 - reserved. the value read from a reserved bit is not defined. table 696. dma interrupt terminal count request clear register (inttcclear, address 0x2008 0008) bit description bit symbol description 7:0 inttcclear allows clearing the terminal count interrupt request (inttcstat) for dma channels. each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt. 31:8 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 836 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.5 dma interrupt e rror clear register the dmacinterrclr register is write-only an d clears the error interrupt requests. when writing to this register, each data bit that is 1 causes the corresponding bit in the status register to be cleared. data bits that are 0 have no effect on the corresponding bit in the register. table 698 shows the bit assignments of the dmacinterrclr register. 35.5.6 dma raw interrupt termin al count status register the dmacrawinttcstat register is read- only and indicates which dma channel is requesting a transfer complete (terminal c ount interrupt) prior to masking. (note: the dmacinttcstat register contains the same information after masking.) a 1 bit indicates that the terminal count interrupt re quest is active prior to masking. table 699 shows the bit assignments of the dmacrawinttcstat register. table 697. dma interrupt error status register (interrstat, address 0x2008 000c) bit description bit symbol description 7:0 interrstat interrupt error status for dma channels. each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. 31:8 - reserved. the value read from a reserved bit is not defined. table 698. dma interrupt error clear register (interrclr, address 0x2008 0010) bit description bit symbol description 7:0 interrclr writing a 1 clears the error interrupt request (interrstat) for dma channels. each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt. 31:8 - reserved. read value is undefined, only zero should be written. table 699. dma raw interrupt terminal count status register (rawinttcstat, address 0x2008 0014) bit description bit symbol description 7:0 rawinttcstat status of the terminal count interrupt for dma channels prior to masking. each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request. 31:8 - reserved. the value read from a reserved bit is not defined.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 837 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.7 dma raw error inte rrupt status register the dmacrawinterrstat register is read- only and indicates which dma channel is requesting an error interrupt prior to maski ng. (note: the dmacin terrstat register contains the same information after masking.) a 1 bit indicates that the error interrupt request is active prior to masking. table 700 shows the bit assignments of register of the dmacrawinterrstat register. 35.5.8 dma enabled channel register the dmacenbldchns register is read-only and indicates which dma channels are enabled, as indicated by the enable bit in the config register. a 1 bit indicates that a dma channel is enabled. a bit is cleared on completion of the dma transfer. table 701 shows the bit assignments of the dmacenbldchns register. 35.5.9 dma software burst request register the dmacsoftbreq register is read/write and enables dma burst requests to be generated by software. a dma request can be generated for each source by writing a 1 to the corresponding register bit. a register bit is cleared when the transaction has completed. reading the register indicates which sources are requesting dma burst transfers. a request can be generated from ei ther a peripheral or the software request register. each bit is cleared when th e related transaction has completed. table 702 shows the bit assignments of the dmacsoftbreq register. table 700. dma raw error interrupt status register (rawinterrstat, address 0x2008 0018) bit description bit symbol description 7:0 rawinterrstat status of the error interrupt for dma channels prior to masking. each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request. 31:8 - reserved. the value read from a reserved bit is not defined. table 701. dma enabled channel register (enbl dchns, address 0x2008 001c) bit description bit symbol description 7:0 enabledchannels enable status for dma channels. each bit represents one channel: 0 - dma channel is disabled. 1 - dma channel is enabled. 31:8 - reserved. the value read from a reserved bit is not defined.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 838 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller note: it is recommended that software and hardware peripheral requests are not used at the same time. 35.5.10 dma software single request register the dmacsoftsreq register is read/write an d enables dma single transfer requests to be generated by software. a dma request can be generated for each source by writing a 1 to the corresponding register bit. a regist er bit is cleared when the transaction has completed. reading the register indicates which sources are requesting single dma transfers. a request can be generated from ei ther a peripheral or the software request register. table 703 shows the bit assignments of the dmacsoftsreq register. 35.5.11 dma software last burst request register the dmacsoftlbreq register is read/write and enables dma last burst requests to be generated by software. a dma request can be generated for each source by writing a 1 to the corresponding register bit. a register bit is cleared when the transaction has completed. reading the register indicates which sources are requesting last burst dma transfers. a request can be generated from ei ther a peripheral or the software request register. table 704 shows the bit assignments of the dmacsoftlbreq register. table 702. dma software burst request register (softbreq, address 0x2008 0020) bit description bit symbol description 15:0 softbreq software burst request flags for each of 16 possible sources. each bit represents one dma request line or peripheral description (refer to table 692 for peripheral hardware connections to the dma controller): 0 - writing 0 has no effect. 1 - writing 1 generates a dma burst request for the corresponding request line. 31:16 - reserved. read value is undefined, only zero should be written. table 703. dma software single request register bit description bit symbol description 15:0 softsreq software single transfer request flags for each of 16 possible sources. each bit represents one dma request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a dma single transfer request for the corresponding request line. 31:16 - reserved. read value is undefined, only zero should be written. table 704. dma software last burst request register (softlbreq, address 0x2008 0028) bit description bit symbol description 15:0 softlbreq software last burst request flags for each of 16 possible sources. each bit represents one dma request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a dma last burst request for the corresponding request line. 31:16 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 839 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.12 dma software last single request register the dmacsoftlsreq register is read/write and enables dma last single requests to be generated by software. a dma request can be generated for each source by writing a 1 to the corresponding register bit. a register bit is cleared when the transaction has completed. reading the register indicates which sources are requesting last single dma transfers. a request can be generated from ei ther a peripheral or the software request register. table 705 shows the bit assignments of the dmacsoftlsreq register. 35.5.13 dma config uration register the config register is read/write and configures the operation of the dma controller. the endianness of the ahb master interface can be altered by writing to the m bit of this register. the ahb master interface is set to little-endian mode on reset. table 706 shows the bit assignments of the config register. 35.5.14 dma synchronization register the sync register is read/write and enable s or disables synchronization logic for the dma request signals. the dma request signal s consist of the breq[15:0], sreq[15:0], lbreq[15:0], and lsreq[15:0]. a bit set to 0 enables the synchronization logic for a particular group of dma requests. a bit set to 1 disables the synchronization logic for a particular group of dma requests. this regist er is reset to 0, enabling synchronization logic by default. ta b l e 7 0 7 shows the bit assignments of the sync register. table 705. dma software last single request register (softlsreq, address 0x2008 002c) bit description bit symbol description 15:0 softlsreq software last single transfer request flags fo r each of 16 possible sources. each bit represents one dma request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a dma last single transfer request for the corresponding request line. 31:16 - reserved. read value is undefined, only zero should be written. table 706. dma configuration register (config, address 0x2008 0030) bit description bit symbo l description 0 e dma controller enable: 0 = disabled (default). disabling the dma controller reduces power consumption. 1 = enabled. 1 m ahb master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode. 31:2 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 840 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.15 dma channel registers the channel registers are used to progra m the eight dma channels. these registers consist of: ? eight srcaddr registers. ? eight destaddr registers. ? eight lli registers. ? eight control registers. ? eight config registers. when performing scatter/gather dma, the firs t four of these are automatically updated. 35.5.16 dma channel s ource address registers the eight read/write srcaddr registers contai n the current source address (byte-aligned) of the data to be transferred. each register is programmed directly by software before the appropriate channel is enabled. when the dma channel is enabled this register is updated: ? as the source address is incremented. ? by following the linked list when a comple te packet of data has been transferred. reading the register when the channel is active does not provide useful information. this is because by the time software has processed the value read, the address may have progressed. it is intended to be read-only when the channel has stopped, in which case it shows the source address of the last item read. note: the source and destination addresses must be aligned to the source and destination widths. table 707. dma synchronization register (sync, address 0x2008 0034) bit description bit symbol description 15:0 dmacsync controls the synchronization logic for dma request signals. each bit represents one set of dma request lines as described in the preceding text: 0 - synchronization logic for the corresponding dma request signals are enabled. 1 - synchronization logic for the corresponding dma request signals are disabled. 31:16 - reserved. read value is undefined, only zero should be written. table 708. dma channel source addr ess registers (srcaddr[0:7], 0x2008 0100 (srcaddr0) to 0x2008 01e0 (srcaddr7)) bit description bit symbol description 31:0 srcaddr dma source address. reading this re gister will return the current source address.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 841 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.17 dma channel destin ation address registers the eight read/write destaddr registers contain the current destination address (byte-aligned) of the data to be transferred. each register is programmed directly by software before the channel is enabled. when the dma channel is enabled the register is updated as the destination address is increm ented and by following the linked list when a complete packet of data has been transferred. reading the register when the channel is active does not provide useful information. this is because by the time that software has processed the value read, the address may have progressed. it is intended to be read-only when a channel has stopped, in whic h case it shows the destination address of the last item read. 35.5.18 dma channel linked list item registers the eight read/write lli registers contain a word-aligned address of the next linked list item (lli). if the lli is 0, then the current lli is the last in the chain, and the dma channel is disabled when all dma transfers associated with it are complete d. programming this register when the dma channel is enabled may have unpredictable side effects. 35.5.19 dma channel control registers the eight read/write control registers contain dma channel control information such as the transfer size, burst size, an d transfer width. each register is programmed directly by software before the dma channel is enabled. when the channel is enabled the register is updated by following the linked list when a comp lete packet of data has been transferred. reading the register while the channel is active does not give useful information. this is because by the time software has proce ssed the value read, the channel may have advanced. it is intended to be read-only when a channel has stopped. ta b l e 7 11 shows the bit assignments of the control register. 35.5.19.1 protection and access information ahb access information is prov ided to the source and/or destination peripherals when a transfer occurs, although on these devices this has no effect. the transfer information is provided by programming the dma channel (the prot bits of the control register, and the table 709. dma channel destination address registers (destaddr[0:7], 0x2008 0104 (destaddr0) to 0x2008 01e4 (destaddr7)) bit description bit symbol description 31:0 destaddr dma destination address. reading this register will return the current destination address. table 710. dma channel linked list item registers (lli[0:7], 0x2008 0108 (lli0) to 0x2008 01e8 (lli7)) bit description bit symbo l description 1:0 - reserved, and must be written as 0. 31:2 lli linked list item. bits [31:2] of the address for the next lli. address bits [1:0] are 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 842 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller lock bit of the config register). these bits are programmed by software, and can be used by peripherals. three bits of informatio n are provided, and are used as shown in ta b l e 7 11 . table 711. dma channel control registers (control[0:7], 0x2008 010c (control0) to 0x2008 01ec (control7)) bit description bit symbol description 11:0 transfersize transfer size. this field sets the size of the transfer when the dma controller is the flow controller, in which case the value must be set before the channel is enabled. transfer size is updated as data transfers are completed. a read from this field indicates the number of transfers completed on the destination bus. reading the register when the channel is active d oes not give useful information because by the time that the software has processed the value read, the channel might have progressed. it is intended to be used only when a channel is enabled and then disabled. the transfer size value is not used if a peripheral is the flow controller. 14:12 sbsize source burst size . indicates the number of transfers that make up a source burst. this value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. the burst size is the amount of data that is transferred when the dmacbreq signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 17:15 dbsize destination burst size. indicates the number of transfers that make up a destination burst transfer request. this value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. the burst size is the amount of data that is transferred when the dmacbreq signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256 20:18 swidth source transfer width. the source and destination widths can be different from each other. the hardware automatically packs and unpacks the data as required. 000 - byte (8-bit) 001 - halfword (16-bit) 010 - word (32-bit) 011 to 111 - reserved
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 843 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 23:21 dwidth destination transfer width. the source and destination widths can be different from each other. the hardware automatically packs and unpacks the data as required. 000 - byte (8-bit) 001 - halfword (16-bit) 010 - word (32-bit) 011 to 111 - reserved 25:24 - reserved, and must be written as 0. 26 si source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer. 27 di destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer. 28 prot1 this is provided to the peripheral during a dma bus access and indicates that the access is in user mode or privileged mode. this information is not used on these devices. 0 - access is in user mode. 1 - access is in privileged mode. 29 prot2 this is provided to the peripheral during a dma bus access and indicates to the peripheral that the access is bufferable or not bufferable. this information is not used on these devices. 0 - access is not bufferable. 1 - access is bufferable. 30 prot3 this is provided to the peripheral during a dma bus access and indicates to the peripheral that the access is cacheable or not cacheable. this information is not used on these devices. 0 - access is not cacheable. 1 - access is cacheable. 31 i terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled. table 711. dma channel control registers (control[0:7], 0x2008 010c (control0) to 0x2008 01ec (control7)) bit description ?continued bit symbol description
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 844 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.20 dma channel c onfiguration registers the eight config registers are read/write with the exception of bit[17] which is read-only. these registers configure each dma channel. the registers are not updated when a new lli is requested. table 712 shows the bit assignments of the config register. table 712. dma channel configuration registers (config[0:7], 0x2008 0110 (config0) to 0x2008 01f0 (config7)) bit description bit symbol description 0 e channel enable. reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. the channel enable bit status can also be found by reading the dmacenbldchns register. a channel is enabled by setting this bit. a channel can be disabled by clearing the enable bit. this causes the current ahb transfer (if one is in progress) to complete and the channel is then disabled. any data in the fifo of the relevant channel is lost. restarting the channel by setting the channel enable bit has unpredictable effects, the channel must be fully re-initialized. the channel is also disabled, and channel enable bit cleared, when the last lli is reached, the dma transfer is completed, or if a channel error is encountered. if a channel must be disabled without losing data in the fifo, the halt bit must be set so that further dma requests are ignored. the active bit must then be polled until it reaches 0, indicating that there is no data left in the fifo. finally, the channel enable bit can be cleared. remark: it is important to be aware that for memory-to-peripheral or memory-to-memory transfers, the dma controller starts fill ing the related channel fifo as soon as the channel is enabled. therefore the source data must be set up in memory prior to enabling channels using those transfer types. 5:1 srcperipheral source peripheral. this value selects the dma source request peripheral. this field is ignored if the source of the transfer is from memory. see ta b l e 6 9 2 for peripheral identification. 10:6 destperipheral destination peripheral. this value selects the dma destination request peripheral. this field is ignored if the destination of the transfer is to memory. see table 692 for peripheral identification. 13:11 transfertype this value indicates the type of transfer and specifies the flow controller. the transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. flow can be controlled by the dma controller, the source peripheral, or the destination peripheral. refer to table 713 for the encoding of this field. 14 ie interrupt e rror mask. when cleared, this bit masks ou t the error interrupt of the relevant channel. 15 itc terminal count interrupt mask. when clea red, this bit masks out the terminal count interrupt of the relevant channel. 16 l lock. when set, this bit enables locked transfers. this information is not used on these devices.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 845 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.5.20.1 lock control the lock control may set the lock bit by writing a 1 to bit 16 of the config register. when a burst occurs, the ahb arbiter will not de-grant the master during the burst until the lock is de-asserted. the dma controller can be locked for a a single burst such as a long source fetch burst or a long destination drain burst. the dma controller does not usually assert the lock continuously for a source fetch burst followed by a destination drain burst. there are situations when the dma contro ller asserts the lock for source transfers followed by destination transfers. this is po ssible when internal conditions in the dma controller permit it to perform a source fetc h followed by a destination drain back-to-back. 35.5.20.2 transfer type table 713 lists the bit values of the tran sfer type bits identified in table 712 . 17 a active: 0 = there is no data in the fifo of the channel. 1 = the channel fifo has data. this value can be used with the halt and channel enable bits to cleanly disable a dma channel. this is a read-only bit. 18 h halt: 0 = enable dma requests. 1 = ignore further source dma requests. the contents of the channel fifo are drained. this value can be used with the active and channel enable bits to cleanly disable a dma channel. 31:19 - reserved. read value is undefined, only zero should be written. table 712. dma channel configuration registers (config[0:7], 0x2008 0110 (config0) to 0x2008 01f0 (config7)) bit description ?continued bit symbol description table 713. transfer type bits bit value transfer type flow controller 000 memory to memory dma controller 001 memory to peripheral dma controller 010 peripheral to memory dma controller 011 source peripheral to destination peripheral dma controller 100 source peripheral to destination peripheral destination peripheral 101 memory to peripheral destination peripheral 110 peripheral to memory source peripheral 111 source peripheral to destination peripheral source peripheral
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 846 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.6 using the dma controller 35.6.1 programming the dma controller all accesses to the dma controller internal register must be word (32-bit) reads and writes. 35.6.1.1 enabling the dma controller to enable the dma controller set the enable bit in the config register. 35.6.1.2 disabling the dma controller to disable the dma controller: ? read the enbldchns register and ensure that all the dma channels have been disabled. if any channels are active, see disabling a dma channel. ? disable the dma controller by writing 0 to t he dma enable bit in the config register. 35.6.1.3 enabling a dma channel to enable the dma channel set the channel enable bit in the relevant dma channel configuration register. note that the channel mu st be fully init ialized before it is enabled. 35.6.1.4 disabling a dma channel a dma channel can be disabled in three ways: ? by writing directly to the channel enable bit. any outstanding data in the fifo?s is lost if this method is used. ? by using the active and halt bits in conjunction with the channel enable bit. ? by waiting until the transfer completes. this automa tically clears the channel. disabling a dma channel and losing data in the fifo clear the relevant channel enable bit in the relevant channel configuration register. the current ahb transfer (if one is in progress) completes and the channel is disabled. any data in the fifo is lost. the channel must be fully re-initialized before it is enabled again. disabling the dma channel without losing data in the fifo ? set the halt bit in the relevant channel conf iguration register. this causes any future dma request to be ignored. ? poll the active bit in the relevant channel conf iguration register until it reaches 0. this bit indicates whether there is any data in the channel that has to be transferred. ? clear the channel enable bit in the relevant channel configuration register 35.6.1.5 setting up a new dma transfer to set up a new dma transfer: if the channel is not set as ide for the dma transaction: 1. read the enbldchns controller register and find out which channels are inactive. 2. choose an inactive channel that has the required priority.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 847 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 3. program the dma controller 35.6.1.6 halting a dma channel set the halt bit in the relevant dma channel configuration register. the current source request is serviced. any further source dma request is ignored until the halt bit is cleared. 35.6.1.7 programming a dma channel 1. choose a free dma channel with the priority needed. dma channel 0 has the highest priority and dma channel 7 the lowest priority. 2. clear any pending interrupts on the channel to be used by writing to the inttcclear and interrclear register. the previous channel operation might have left interrupt active. 3. write the source address into the srcaddr register. 4. write the destination address into the destaddr register. 5. write the address of the next lli into the lli register. if the transfer comprises of a single packet of data then 0 must be written into this register. 6. write the control informatio n into the control register. 7. write the channel configuration information in to the config register. if the enable bit is set then the dma channel is automatically enabled. 35.6.2 flow control the device that controls the length of the pa cket is known as the flow controller. the flow controller is usually the dm a controller, where the packet length is programmed by software before the dma channel is enabled. most peripherals are not able to be the flow controller, but when this feature is supported , it can be used by either the source or destination peripheral. when the dma transfer is completed: 1. the dma controller issues an acknowledge to the peripheral in order to indicate that the transfer has finished. 2. a tc interrupt is generated, if enabled. 3. the dma controller moves on to the next lli. the following sections describe the dma controller data flow sequences for the four allowed transfer types: ? memory-to-peripheral. ? peripheral-to-memory. ? memory-to-memory. ? peripheral-to-peripheral. each transfer type other than memory-to-memory can have either the peripheral or the dma controller as the flow controller, resulting in 8 possible control scenarios. table 714 indicates the request signals used for each type of transfer.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 848 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 35.6.2.1 peripheral-to-memory or memory-to-peripheral dma flow for a peripheral-to-memory or memory-to-peripheral dma flow, the following sequence occurs: 1. program and enable the dma channel. 2. wait for a dma request. 3. the dma controller starts transferring data when: ? the dma request goes active. ? the dma stream has the highest pending priority. ? the dma controller is the bus master of the ahb bus. 4. if an error occurs while tr ansferring the data, an error interrupt is generated and disables the dma stream, and the flow sequence ends. 5. decrement the transfer count. 6. if the transfer has completed (indicated by the transfer count reaching 0 if the dma controller is performing flow control, or by the peripheral sending a dma request if the peripheral is performing flow control): ? the dma controller responds with a dma acknowledge. ? the terminal count interrupt is gener ated (this interrupt can be masked). ? if the lli register is not 0, then reload the srcaddr, destaddr, lli, and control registers and go to back to step 2. however, if lli is 0, the dma stream is disabled and the flow sequence ends. 35.6.2.2 peripheral-to-peripheral dma flow for a peripheral-to-peripheral dma fl ow, the following sequence occurs: 1. program and enable the dma channel. 2. wait for a source dma request. 3. the dma controller starts transferring data when: ? the dma request goes active. ? the dma stream has the highest pending priority. ? the dma controller is the bus master of the ahb bus. table 714. dma request signal usage transfer direction request generator flow controller memory-to-peripheral destination peripheral dma controller peripheral-to-memory source peripheral dma controller memory-to-memory dma controller dma controller source peripheral to destination peripheral both s ource and destination peripherals dma controller memory-to-peripheral destination peripheral destination peripheral peripheral-to-memory source peripheral source peripheral source peripheral to destination peripheral both sour ce and destination peripherals source peripheral source peripheral to destination peripheral both source and destination peripherals destination peripheral
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 849 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller 4. if an error occurs while transferring the da ta an error interrupt is generated, the dma stream is disabled, and the flow sequence ends. 5. decrement the transfer count. 6. if the transfer has completed (indicated by the transfer count reaching 0 if the dma controller is performing flow control, or by the peripheral sending a dma request if the peripheral is performing flow control): ? the dma controller responds with a dma acknowledge to the source peripheral. ? further source dma requests are ignored. 7. when the destination dma request goes active and there is data in the dma controller fifo, transfer data into the destination peripheral. 8. if an error occurs while transferring the da ta, an error interrupt is generated, the dma stream is disabled, and the flow sequence ends. 9. if the transfer has completed it is indicated by the transfer count reaching 0 if the dma controller is the flow controller. or by t he peripheral sending a dma request if the peripheral is performing flow control. the following happens: ? the dma controller responds with a dma acknowledge to the destination peripheral. ? the terminal count interrupt is gener ated (this interrupt can be masked). ? if the lli register is not 0, then reload the srcaddr, destaddr, lli, and control registers and go to back to step 2. however, if lli is 0, the dma stream is disabled and the flow sequence ends. 35.6.2.3 memory-to-memory dma flow for a memory-to-memory dma flow the following sequence occurs: 1. program and enable the dma channel. 2. transfer data whenever the dma channel has the highest pending priority and the dma controller gains mastership of the ahb bus. 3. if an error occurs while transferring the data, generate an error interrupt and disable the dma stream. 4. decrement the transfer count. 5. if the count has reached zero: ? generate a terminal count interrupt (the interrupt can be masked). ? if the lli register is not 0, then reload the srcaddr, destaddr, lli, and control registers and go to back to step 2. however, if lli is 0, the dma stream is disabled and the flow sequence ends. note: memory-to-memory transfers should be programmed with a low channel priority, otherwise other dma channels cannot acce ss the bus until the memory-to-memory transfer has finished, or other ahb masters cannot perform any transaction. 35.6.3 interrupt requests interrupt requests can be generated when an ah b error is encountered or at the end of a transfer (terminal count), after all the data corresponding to the current lli has been transferred to the destination. the interrupts can be masked by programming bits in the relevant control and config channel registers. the interrupt requests from all dma
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 850 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller channels can be found in the rawinttcstat and rawinterrstat registers. the masked versions of the dma interrupt data is containe d in the inttcstat and interrstat registers. the intstat register then combines the inttcstat and interrstat requests into a single register to enable the source of an interrupt to be found quickly. writing to the inttcclear or the interrclr registers with a bit set to 1 enables selective clearing of interrupts. 35.6.3.1 hardware interrupt sequence flow when a dma interrupt request occurs, t he interrupt service routine needs to: 1. read the inttcstat register to determine whether the interrupt was generated due to the end of the transfer (terminal count). a 1 bi t indicates that the tr ansfer completed. if more than one request is active, it is reco mmended that the highest priority channels be checked first. 2. read the interrstat register to determine whether the interrupt was generated due to an error occurring. a 1 bit indicates that an error occurred. 3. service the interrupt request. the ch annel that caused the interrupt can be determined by reading the intstat register. if more than one request is active, the one with the highest priority should generally be serviced first. 4. for a terminal count interrupt, write a 1 to the relevant bit of the inttcclr register. for an error interrupt write a 1 to the relevant bit of the interrclr register to clear the interrupt request. 35.6.4 address generation address generation can be either incrementing or non-incrementing (address wrapping is not supported). some devices, especially memories, disallo w burst accesses ac ross certain address boundaries. the dma controller assumes that this is the case with any source or destination area that is configured for incrementing addressing. this boundary is assumed to be aligned with the specified burst size. for example, if the channel is set for 16-transfer burst to a 32-bit wide device then the boundary is 64-bytes aligned (that is address bits [5:0] equal 0). if a dma burst is to cross one of these boundaries, then, instead of a burst, that transfer is sp lit into separate ahb transactions. 35.6.4.1 word-aligned transfers across a boundary the channel is configured fo r 16-transfer bursts, each tr ansfer 32-bits wide, to a destination for which address incrementing is enabled. the start address for the current burst is 0x0c00 0024, the next boundary (calculated from the burst size and transfer width) is 0x0c00 0040. the transfer will be split into two ahb transactions: ? a 7-transfer burst starting at address 0x0c00 0024 ? a 9-transfer burst starting at address 0x0c00 0040. 35.6.5 scatter/gather scatter/gather is supported th rough the use of linked lists. th is means that the source and destination areas do not have to occupy contiguous areas in memory. where scatter/gather is not required, the lli register must be set to 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 851 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller the source and destination data areas are defined by a series of linked lists. each linked list item (lli) controls the transfer of one bl ock of data, and then optionally loads another lli to continue the dma operation, or stops the dma stream. the first lli is programmed into the dma controller. the data to be transferred described by an lli (referred to as the packet of data) usually requires one or more dma bursts (to each of the source and destination). 35.6.5.1 linked list items a linked list item (lli) consists of four wo rds. these words are organized in the following order: 1. srcaddr. 2. destaddr. 3. lli. 4. control. note: the config dma channel configuration regi ster is not part of the linked list item. 35.6.5.1.1 programming the dma controller for scatter/gather dma to program the dma contro ller for scatter/gather dma: 1. write the llis for the complete dma transfer to memory. each linked list item contains four words: ? source address. ? destination address. ? pointer to next lli. ? control word. the last lli has its linked list word pointer set to 0. 2. choose a free dma channel with the priority required. dma channel 0 has the highest priority and dma channel 7 the lowest priority. 3. write the first linked list item, previously written to memory, to the relevant channel in the dma controller. 4. write the channel configuration information to the channel configuration register and set the channel enable bit. the dma controller then transfers the first and then subsequent packets of data as each linked list item is loaded. 5. an interrupt can be generated at the end of each lli depending on the terminal count bit in the control register. if this bit is set an interrupt is generated at the end of the relevant lli. the interrupt request must then be serviced and the relevant bit in the inttcclear register must be set to clear the interrupt. 35.6.5.1.2 example of scatter/gather dma see figure 165 for an example of an lli. a section of memory is to be transferred to a peripheral. the addresses of each lli entry are given, in hexadecimal, at the left-hand side of the figure. in this example, the llis describing the transfer are to be stored contiguously from address 0x2002 0000, but t hey could be located anywhere. the right side of the figure shows the memory containing the data to be transferred.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 852 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller the first lli, stored at 0x2002 0000, defines the first block of data to be transferred, which is the data stored from addr ess 0x2002 a200 to 0x2002 adff: ? source start address 0x2002 a200. ? destination address set to the destination peripheral address. ? transfer width, word (32-bit). ? transfer size, 3072 bytes (0xc00). ? source and destination burst sizes, 16 transfers. ? next lli address, 0x2002 0010. the second lli, stored at 0x2002 0010, describes the next block of data to be transferred: ? source start address 0x2002 b200. ? destination address set to the destination peripheral address. ? transfer width, word (32-bit). ? transfer size, 3072 bytes (0xc00). ? source and destination burst sizes, 16 transfers. ? next lli address, 0x2002 0020. a chain of descriptors is built up, each one pointing to the next in the series. to initialize the dma stream, the first lli, 0x2002 0000, is programmed into the dma controller. when the first packet of data has been transferred the next lli is automatically loaded. the final lli is stored at 0x2002 0070 and contains: fig 165. lli example lli1 0x2002 0000 source address = 0x 2002 a200 destination address = peripheral next lli address = 0x2002 0010 control information = length 3072 source address = 0x 2002 b200 destination address = peripheral next lli address = 0x2002 0020 control information = length 3072 source address = 0x 2002 c200 destination address = peripheral next lli address = 0x2002 0030 control information = length 3072 source address = 0x 2003 1200 destination address = peripheral next lli address = 0 (end of list) control information = length 3072 lli2 0x2002 0010 lli3 0x2002 0020 lli8 0x2002 0070 linked list array 3072 bytes of data 0x2002 a200 0x2002 adff 3072 bytes of data 0x2002 b200 0x2002 bdff 3072 bytes of data 0x2002 c200 0x2002 cdff 3072 bytes of data 0x2003 1200 0x2003 1dff
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 853 of 942 nxp semiconductors UM10562 chapter 35: lpc408x/407x general purpose dma controller ? source start address 0x2003 1200. ? destination address set to the destination peripheral address. ? transfer width, word (32-bit). ? transfer size, 3072 bytes (0xc00). ? source and destination burst sizes, 16 transfers. ? next lli address, 0x0. because the next lli address is set to zero, this is the last descriptor, and the dma channel is disabled after transferring the last item of data. the channel is probably set to generate an interrupt at this point to indicate to the arm processor that the channel can be reprogrammed.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 854 of 942 36.1 introduction the cyclic redundancy check (crc) genera tor with programmable polynomial settings supports several crc standards commonl y used. to save system power and bus bandwidth, the crc engine supports dma transfers in addition to software pio operations using the cpu. 36.2 features ? supports three common polynomials crc-ccitt, crc-16, and crc-32. ? crc-ccitt: x 16 + x 12 + x 5 + 1 ? crc-16: x 16 + x 15 + x 2 + 1 ? crc-32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 ? bit order reverse and 1?s complement programmable setting for input data and crc sum. ? programmable seed number setting. ? supports cpu pio or dma back-to-back transfer. ? accept any size of data widt h per write: 8, 16 or 32-bit. ? 8-bit write: 1-cycle operation ? 16-bit write: 2-cycle op eration (8-bit x 2-cycle) ? 32-bit write: 4-cycle op eration (8-bit x 4-cycle) UM10562 chapter 36: lpc408x/407x crc engine rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 855 of 942 nxp semiconductors UM10562 chapter 36: lpc408x/407x crc engine 36.3 description fig 166. crc block diagram ccitt poly crc-16 poly crc-32 poly crc reg bit reverse 1's comp b3 b2 b1 b0 d e q crc fsm 1's comp bit reverse crc seed crc mode mux mux mux ahb bus crc id crc wr buf crc sum
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 856 of 942 nxp semiconductors UM10562 chapter 36: lpc408x/407x crc engine 36.4 register description [1] reset value reflects the data stored in used bits only. it does not include content of reserved bits. 36.4.1 crc mode register 36.4.2 crc seed register table 715. register overview: crc engine (base address 0x2009 0000) name access address offset description reset value [1] table mode r/w 0x000 crc mode register 0 716 seed r/w 0x004 crc seed register 0xffff 717 sum ro 0x008 crc checksum register 0xffff 718 data wo 0x008 crc data register - 719 table 716. crc mode register (mode - address 0x2009 0000) bit description bit symbol value description reset value 1:0 crc_poly select crc polynomial 0 0x0 crc-ccitt polynomial 0x1 crc-16 polynomial 0x2 crc-32 polynomial 2 bit_rvs_wr select bit order for crc_wr_data 0 0 no bit order reverse for crc_wr_data (per byte) 1 bit order reverse for crc_wr_data (per byte) 3 cmpl_wr select one?s complement for crc_wr_data 0 0 no one?s complement for crc_wr_data 1 one?s complement for crc_wr_data 4 bit_rvs_sum select bit order revers for crc_sum 0 0 no bit order reverse for crc_sum 1 bit order reverse for crc_sum 5 cmpl_sum select one?s complement for crc_sum 0 0 no one?s complement for crc_sum 1 one?s complement for crc_sum 31:6 reserved always ?0? when read 0 table 717. crc s eed register (seed - address 0x2009 0004) bi t description bit symbol description reset value 31:0 crc_seed a write access to this register will load crc seed value to crc_sum register with selected bit order and 1?s complement pre-processes. remark: writing a new seed value to this register essentially starts a new crc with that seed. 0xffff
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 857 of 942 nxp semiconductors UM10562 chapter 36: lpc408x/407x crc engine 36.4.3 crc checksum register this register is a read-only register containing the most recent checksum. 36.4.4 crc data register this register is a wr ite-only register containing the da ta block for which the crc sum will be calculated. table 718. crc checksum register (sum - address 0x2009 0008) bit description bit symbol description reset value 31:0 crc_sum the most recent crc sum can be read thr ough this register with selected bit order and 1?s complement post-processes. 0xffff table 719. crc data register (data - address 0x2009 0008) bit description bit symbol description 31:0 crc_wr_data data written to this register will be taken to perform crc calculation with selected bit order and 1?s complement pre-process. any write size 8, 16 or 32-bit are allowed and accept back-to-back transactions.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 858 of 942 nxp semiconductors UM10562 chapter 36: lpc408x/407x crc engine 36.5 functional description the following sections describe the register settings for each supported crc standard: crc-ccitt set-up polynomial = x 16 + x 12 + x 5 + 1 seed value = 0xffff bit order reverse for data input: no 1's complement for data input: no bit order reverse for crc sum: no 1's complement for crc sum: no crc_mode = 0x0000 0000 crc_seed = 0x0000 ffff crc-16 set-up polynomial = x 16 + x 15 + x 2 + 1 seed value = 0x0000 bit order reverse for data input: yes 1's complement for data input: no bit order reverse for crc sum: yes 1's complement for crc sum: no crc_mode = 0x0000 0015 crc_seed = 0x0000 0000 crc-32 set-up polynomial = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 seed value = 0xffff ffff bit order reverse for data input: yes 1's complement for data input: no bit order reverse for crc sum: yes 1's complement for crc sum: yes crc_mode = 0x0000 0036 crc_seed = 0xffff ffff
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 859 of 942 37.1 basic configuration the eeprom is configured using the following registers: 1. power: the eeprom is enabled after a device reset, but may be turned off if it is not needed., or to save power. see section 37.5.1.7 ). 2. clocking: timing for the eeprom must be set up before it can be used. see section 37.5.1.5 and section 37.5.1.6 . 3. interrupts: interrupts are controlled using a set of registers, see section 37.5.2 . interrupts are enabled in the nvic using the appropriate interrupt set enable register, see ta b l e 5 0 . 37.2 description eeprom is a non-volatile memory mainly us ed for storing relative ly small amounts of data, for example for application settings. the eeprom is indirectly accessed through address and data registers, so the cpu cannot execute code from eeprom memory. all communication with the actual eeprom bl ock is done through the 64 byte page buffer. 37.3 features ? 4,032 bytes eeprom on most devices ? access via address and data registers on the ahb bus ? less than 3 ms erase / program time ? endurance of > 100k erase / program cycles UM10562 chapter 37: lpc408x/407x eeprom memory rev. 1 ? 13 september 2012 user manual fig 167. eeprom block diagram 120503 64 byte page buffer 4,032 byte or 2,048 byte eeprom eeprom registers read write ahb bus 375 khz clock cclk
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 860 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.4 eeprom operation 37.4.1 eeprom device description eeprom is a non-volatile memory mainly us ed for storing relative ly small amounts of data, for example for storing settings. there are three operations for accessi ng the memory: reading, writing and erase/program. "writing" to memory is split up into two separate operations, writing and erase/program. the first operat ion, which will be called "writing" in this document, is not really updating the memory, but only updating the temporary data register called the "page register". the page register needs to be written with a minimum 1 byte and a maximum 64 bytes before the second operation, which is called "erase/program" in this document, can be used to actually update the non-volatile memory. note that the data written to the page register is not "cached"; it cannot be read before it is actually programmed into non-volatile memory. the 64-byte page register is the same size as a page in eeprom memory. the 4,032 bytes eeprom on most devices contains 63 pages. devices with a 2 kb eeprom provide 2,048 bytes on 32 pages. 37.4.2 eeprom operations an eeprom device cannot be pr ogrammed directly. writing data to it and the actual erase/program of the memory ar e two separate steps. the pa ge register (64 bytes) will temporarily hold write data. but as soon as th is data needs to be read from the eeprom or data needs to be written to another page, the contents of the page register first needs to be programmed into the eeprom memory. the following sections explain the eeprom op erations (read, write and erase/program) in more detail. 37.4.2.1 writing the eeprom controller supports writing of 8-bi t, 16-bit, or 32-bit elements. since the eeprom device doesn?t directly support 32-b it write operations, the controller splits the operation into two 16-bit operations. for doing a write operation first an address ne eds to be written into the address register and the kind of write operation needs to be selected in the command register. this can be done in any order. after this the data is written to the write data register, which automatically starts the write operation on the eeprom device.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 861 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory a write operation causes an automatic post -increment of the address. this allows consecutive writes to the page register without the need of writing a new address for every write operation. of course the address regi ster could be written with another address value to write to another location. if the data register is written while a previous eeprom operation is still pending, the write transfer on the system bus is stalled until the previous operation is finished. this can be avoided by polling the inte rrupt status register to see if an operation is st ill pending before starting the write operation. software has to make sure that the following rules are followed: ? overwriting (writing it two times before an erase/program operation) one of the locations in a 64-byte page register is not allowed. it will cause the loss of the previously written data fig 168. starting a write operation write address register write address register - or - write command register write command register write data register write data register write operation on eeprom now starts fig 169. (16-bit) write operations with post-incrementing of address write address register (address a) write address register (address a) - or - write command register (16-bit write) write data register write data register write operation on eeprom now starts write command register (16-bit write) write data register write data register write operation on eeprom now starts write data register write data register write operation on eeprom now starts address a address a+2 address a+4
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 862 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory ? in case the default address post-increment ing is used, the upper boundary of the page register may not be crossed ? the contents of the page register needs to be programmed into non-volatile memory before it can be read back ? write operations to a misaligned address will result in an error response on the write transfer to the write data register (for ex ample a 32-bit write operation to an address other than a multiple of 0x4). th e operation will not be performed. 37.4.2.2 erase/programming after the page register has bee n written with user data, it still has to programmed into non-volatile memory. this is a separate step . only writing to the page register will not write the eeprom memory. programming the page into memory takes a relatively long time, therefore the corresponding interrupt can be enabled, or the interrupt status bit can be polled to avoid stalling of the system bus. an erase/program operation starts by providin g the msbs of the address that selects the page in memory. the 6 lsbs are "don?t care ". the operation is started by writing the command register (selecting the erase/ program operation). before beginning a programming operation, the eeprom status shoul d be polled to insure that the last write operation has been completed. 37.4.2.3 reading the eeprom controller supports reading 8-bit, 16-bit, or 32-bit elements. since the eeprom device doesn?t support 32-bit operat ions the controller split s the operation into two 16-bit operations. for doing a read operation, an address first need s to be written into the address register. then the operation needs to be selected in the command register. writing the command register will automatica lly start the read operat ion on the eeprom device. fig 170. programming a page into memory write address register (msb) write command register (erase/program operation) erase/program oper- ation on eeprom now starts
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 863 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory if the read data register is re ad while the read operation is still pending, then the read transfer on the system bus is stalled until the previous read operation is finished. this can be avoided by polling the interrupt status register to see if the o peration is still pending before reading the read data register. read operations will automatica lly post-increment the addr ess register. this allows consecutive reads from the eepr om memory without the need of writing a new address for every read operation. by setting the read data prefetch bit in the command register, reading from the read data register automatica lly starts up a read operation from the next (incremented) address location. when doing cons ecutive reads in this way, the first read operation is started as result of writin g the command register. the following read operations are started as result of reading the read data register to obtain the result of the previous read operations. read operations from a misaligne d address will result on an error resp onse on the write transfer to the command register (for exampl e a 32-bit read operation from an address other than a multiple of 0x4). the operation will not be performed. 37.4.2.4 exceptions the controller can generate exceptio ns in the following situations: ? writing a read-only register or reading a write-only register ? a transfer to a non-exi sting register location fig 171. starting a read operation (32-bit read from address a) write address register (address a) write command register (32-bit read) operation on eeprom now starts read data register
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 864 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5 register description table 720 shows the registers related to eeprom operation. details of each register follow. [1] reset value reflects the data stored in used bi ts only. it does not include reserved bits content. table 720. register overview: eeprom controller (base address 0x0020 0000) name access address offset description reset value [1] table eeprom registers cmd r/w 0x080 eeprom command register 0 721 addr r/w 0x084 eeprom address register 0 722 wdata wo 0x088 eeprom write data register - 723 rdata ro 0x08c eeprom read data register - 724 wstate r/w 0x090 eeprom wait state register 0 725 clkdiv r/w 0x094 eeprom cl ock divider register 0 726 pwrdwn r/w 0x098 eeprom power-down register 0 727 eeprom interrupt registers: intstat ro 0xfe0 eeprom interrupt status 0 728 intstatclr wo 0xfe8 eeprom interrupt st atus clear - 729 intstatset wo 0xfec eeprom interrupt st atus set - 730 inten ro 0xfe4 eeprom interrupt enable 0 731 intenclr wo 0xfd8 eeprom interrupt enable clear - 732 intenset wo 0xfdc eeprom interrupt enable set - 733
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 865 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.1 eeprom control registers 37.5.1.1 eeprom command register the eeprom command register is used to select and start a read, write or erase/program operation. read and erase/ program operations are started on the eeprom device as a side-effect of writing to th is register. (write operations are started as a side-effect of writing to the write data register). 37.5.1.2 eeprom address register the eeprom address register is used to program the address for read, write or erase/program operations. table 721. eeprom command re gister (cmd - address 0 x0020 0080) bit description bits symbol description reset value 2:0 cmd command. 000: 8-bit read 001: 16-bit read 010: 32-bit read 011: 8-bit write 100: 16-bit write 101: 32-bit write 110: erase/program page 111: reserved 0 3 rdprefetch read data prefetch bit. 0: do not prefetch next read data as result of reading from the read data register. 1: prefetch read data as result of reading from the read data register. when this bit is set multiple consecutive data elements can be read without the need of programming new address values in the address register. the address post-increment and the automatic read data prefetch (if enabled) allow only reading from the read data register to be done to read the data. 0 31:4 - reserved. read value is undefined, only zero should be written. na table 722. eeprom address register (addr - address 0x0020 0084) address description bits symbol description reset value 11:0 addr eeprom address. lower 6 bits are don't care. 0 31:12 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 866 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.1.3 eeprom write data register the eeprom write data register is used to wr ite data into the page register (write operations). writing this register will st art the write operation as a side-effect. th e address is post-incremented, so consecutiv e writes to this register c an be done to write a burst of data, up to a maximum of 64 bytes. the address will be incremented automatically according to the data size of the write operation. if data is written to this register while a previous operation (read, write or an erase/program) is still pending or being processe d, the write comma nd on the ahb is stalled until the previous operation is finis hed. to avoid stalling of the system bus, the interrupt status regi ster can be used for polling the status of pending operations. 37.5.1.4 eeprom read data register the eeprom read data register is used to read data from the non-volatile memory. reading this register will start the next re ad operation, and the address will be post-incremented. consecutive reads from this register can be done to read a burst of data. the address will be increm ented automatically a ccording to the data size of the read operation. if data is read from this register while the read operation is still p ending the read command on the ahb bus is stalled until the pending op eration is finished. to avoid stalling of the system bus, the interrupt stat us register can be used for polling the status of pending operations. table 723. eeprom write data register (wda ta - address 0x0020 0088) bit description bits symbol description 31:0 wdata write data. in case of: 8-bit write operations: bits [7:0] must contain valid write data. 16-bit write operations: bits [15:0] must contain valid write data. 32-bit write operations: bits [31:0] must contain valid write data. table 724. eeprom read data register (rda ta - address 0x0020 008c) bit description bits symbol description 31:0 rdata read data. 8-bit read operations: bits [7:0] contain the valid read data, others are zero. 16-bit read operations: bits [15:0] contain the valid read data, others are zero. 32-bit read operations: bits [31:0] contain the valid read data.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 867 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.1.5 eeprom wait state register the eeprom controller uses the times specifie d by this register to perform various internal timing functions. the user must progr am the wait state fields with appropriate values for proper eeprom erase/ program operation. programming a zero will result in a one cycle wait state. example with cclk=120 mhz: phase3 = ( 15ns * cclk) - 1 = (15ns * 120mhz) - 1 = 1.8 therefore, phase3 = 2 phase2=( 55ns * cclk) - 1 = (55ns * 120mhz) - 1 = 5.8 therefore, phase2 = 6 phase1=( 35ns * cclk) - 1 = (35ns * 120mhz) - 1 = 3.2 therefore, phase3 = 4 37.5.1.6 eeprom clock divider register the eeprom requires a 375 khz 6.67% clock. this clock is generated by dividing the system bus clock. the clock divider register contains the division factor. if the division factor is 0, the clock will be idle to save power. for example, if the cpu clock is 80 mhz: clkdiv = (cclk / 375 khz) - 1 = (80 mhz / 375 khz) - 1 = 212 table 725. eeprom wait state register (wstate - address 0x0020 0090) bit description bits symbol description reset value 7:0 phase3 wait states 3 (minus 1 encoded). the number of system clock periods required to give a minimum time of 15 ns. 0 15:8 phase2 wait states 2 (minus 1 encoded). the number of system clock periods required to give a minimum time of 55 ns. 0 23:16 phase1 wait states 1 (minus 1 encoded). the number of system clock periods required to give a minimum time of 35 ns. 0 31:24 - reserved. read value is undefined, only zero should be written. na clkdiv cclk 375khz ------------------ - 1 ? =
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 868 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.1.7 eeprom power down register the eeprom power-down register can be us ed to put the eeprom in power-down mode. the eeprom may not be put in power-down mode during a pending eeprom operation. after clearing this bit, any eeprom operation has to be suspended for 100 ? s while the eeprom wakes up. table 726. eeprom clock divider register (c lkdiv - address 0x0020 0094) bit description bits symbol value description reset value 15:0 clkdiv eeprom division factor. 0 0 the eeprom clock will be id led in order to save power 1 cclk is divided by 2 2 cclk is divided by 3 :: 0xffff cclk is divided by 65536 31:16 - reserved. read value is undefined, only zero should be written. na table 727. eeprom power down/dcm register (pwrdwn - addre ss 0x0020 0098) bit description bits symbol description reset value 0 pwrdwn power down mode bit. 0: not in power down mode 1: power down mode 0 31:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 869 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.2 interrupt registers these registers control interrupts from the eeprom. 37.5.2.1 interrupt status register the interrupt request output is asserted wh en the bitwise and of intstat and inten is nonzero. for the eeprom read/write operation fi nished interrupt it is better not to enable the interrupt, but to only poll the bit in the intstat register. this is because these operations are relatively fast operations that do not just ify calling a interrupt service subroutine in software. 37.5.2.2 interrupt status clear register table 728. interrupt status register (intstat - address 0x0020 0fe0) bit description bits symbol description reset value 25:0 - reserved. the value read from a reserved bit is not defined. na 26 end_of_rdwr interrupt status bit for eeprom read/write operation finished. this bit is set when this operation has finished or when ?1? is written in the corresponding bit of the intstatset register. this bit is cleared when ?1? is written to the corresponding bit of the intstatclr register. 0 27 - reserved. the value read from a reserved bit is not defined. na 28 end_of_prog1 interrupt status bit for eeprom program operation finished. this bit is set when this operation has finished or when ?1? is written to the corresponding bit of the intstatset register. this bit is cleared when ?1? is written to the corresponding bit of the intstatclr register. 0 31:29 - reserved. the value read from a reserved bit is not defined. na table 729. interrupt status clear register (intstatclr - address 0x0020 0fe8) bit description bits symbol description 25:0 - reserved. read value is undefined, only zero should be written. 26 rdwr_clr_st clear read/write operation finished interrupt status bit for the eeprom. 0 leave corresponding bit unchanged. 1 clear corresponding bit. 27 - reserved. read value is undefined, only zero should be written. 28 prog1_clr_st clear program operation finished interrupt status bit for the eeprom. 0 leave corresponding bit unchanged. 1 clear corresponding bit. 31:29 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 870 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.2.3 interrupt status set 37.5.2.4 interrupt enable register this is a read-only register. changes to this register must be made using the intenset and intenclr registers. the interrupt request output is asserted when the bitwise and of intstat and inten is a non-zero va lue. for eeprom read/write completed operations, it is better not to enable the interr upt, but to poll the bit in the intstat register. this is because these op erations are relatively fast and do not justify ca lling an interrupt service subroutine in software. 37.5.2.5 interrupt enable clear register table 730. interrupt status set register (intstatset - address 0x0020 0fec) bits symbol description 25:0 - reserved. read value is undefined, only zero should be written. 26 rdwr_set_st set read/write operation finished interrupt status bit for the eeprom. 0 leave the corresponding bit in the intstat register unchanged. 1 set the corresponding bit in the intstat register. 27 - reserved. read value is undefined, only zero should be written. 28 prog1_set_st set program o peration finished interrupt status bit for the eeprom. 0 leave the corresponding bit in the intstat register unchanged. 1 set the corresponding bit in the intstat register. 31:29 - reserved. read value is undefined, only zero should be written. table 731. interrupt enable register (inten - address 0x0020 0fe4) bit description bits symbol description reset value 25:0 - reserved. the value read from a reserved bit is not defined. na 26 ee_rw_done interrupt enable bit for eeprom read/write operation finished. this bit is set when ?1? is written to the corresponding bit of the intenset register. this bit is cleared when ?1? is written to the corresponding bit of the intenclr register. 0 27 - reserved. the value read from a reserved bit is not defined. na 28 ee_prog_done interrupt enable bit fo r eeprom program operation finished. this bit is set when ?1? is written to the corresponding bit of the intenset register. this bit is cleared when ?1? is written to the corresponding bit of the intenclr register. 0 31:29 - reserved. the value read from a reserved bit is not defined. na table 732. interrupt enable clear register (intenclr - address 0x0020 0fd8) bit description bits symbol description 25:0 - reserved. read value is undefined, only zero should be written. 26 rdwr_clr_en clear the read/write operation finished interrupt enable bit for the eeprom. 0: leave the corresponding bit in the inten register unchanged. 1: clear the corresponding bit in the inten register.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 871 of 942 nxp semiconductors UM10562 chapter 37: lpc408x/407x eeprom memory 37.5.2.6 interrupt enable set register 27 - reserved. read value is undefined, only zero should be written. 28 prog1_clr_en clear the program operation fi nished interrupt enable bit for the eeprom. 0: leave the corresponding bit in the inten register unchanged. 1: clear the corresponding bit in the inten register. 31:29 - reserved. read value is undefined, only zero should be written. table 732. interrupt enable clear register (intenclr - address 0x0020 0fd8) bit description bits symbol description table 733. interrupt enable set register (intenset - address 0x0020 0fdc) bit description bits symbol description 25:0 - reserved. read value is undefined, only zero should be written. 26 rdwr_set_en set the read/write operation finished interrupt enable bit for the eeprom. 0: leave the corresponding bit in the inten register unchanged. 1: set the corresponding bit in the inten register. 27 - reserved. read value is undefined, only zero should be written. 28 prog1_set_en set the program operation fi nished interrupt enable bit for the eeprom. 0: leave the corresponding bit in the inten register unchanged. 1: set the corresponding bit in the inten register. 31:29 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 872 of 942 38.1 introduction the boot loader controls initial operation after reset and also provides the tools for programming the flash memory. this could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. 38.2 features ? in-system programming: in-system pr ogramming (isp) is programming or reprogramming the on-chip flash memory, us ing the boot loader software and uart0 serial port. this can be done when the part resides in the end-user board. ? in application programming: in-application (iap) programming is performing erase and write operation on the on-chip flash memory, as directed by the end-user application code. ? flash signature generation: built-in hardware can generate a signature for a range of flash addresses, or for the entire flash memory. 38.3 description the flash boot loader code is executed every ti me the part is powered on or reset. the loader can execute the isp command handler or the user application code. a low level after reset at pin p2[10] is considered an external hardware request to start the isp command handler using uart0 pins p0[2] (u0_txd) and p0[3] (u0_rxd). assuming that power supply pins are on their nominal levels when the rising edge on reset pin is generated, it may take up to 3 ms before p2[10] is sampled and the decision on whether to continue with user code or isp handler is made. if p2[10] is sampled low and the watchdog overflow flag is set, the external hardware request to start the isp command handler is ignored. if there is no request for the isp command handl er execution (p2[10] is sampled high after reset), a search is made for a valid user program. if a valid user program is found then the execution control is transferred to it. if a valid user program is not found, the auto-baud routine is invoked. pin p2[10] is used as a hardware request si gnal for isp and therefore requires special attention. since p2[10] is in high impedance mode after reset, it is important that the user provides external hardware (a pull-up resistor or other device) to put the pin in a defined state. otherwise unintended entry into isp mode may occur. when isp mode is entered after a power on reset, the irc frequency of 12 mhz is used to operate the cpu and peripherals. the baud ra tes that can easily be obtained in this case are: 9600 baud, 19200 baud, 38400 baud, 57600 baud, and 115200 baud. a hardware flash signature gener ation capability is built into the flash memory. this feature can be used to create a signature that can then be used to verify flash contents. details of flash signature generation are in section 38.10 . UM10562 chapter 38: lpc408x/407x flash memory rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 873 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.3.1 memory map after any reset when a user program begins execution after re set, the interrupt vector s are set to point to the beginning of flash memory. 38.3.1.1 criterion for valid user code the reserved cortex-m4 exception vector locati on 7 (offset 0x001c in the vector table) should contain the 2?s complement of the check-sum of table entries 0 through 6. this causes the checksum of the first 8 table entries to be 0. the boot loader code checksums the first 8 locations in sector 0 of the flash. if the result is 0, then execution control is transferred to the user code. if the signature is not valid, the auto-baud routin e synchronizes with the host via serial port 0. the host should send a ??? (0x3f) as a synchronization character and wait for a response. the host side serial port settings should be 8 data bits, 1 stop bit and no parity. the auto-baud routine measures the bit time of the received synchronization character in terms of its own frequency and programs the baud rate generator of the serial port. it also sends an ascii string ("synchronized") to the host. in response to this the host should send the same string ("synchronized< cr>"). the auto-baud routine looks at the received characters to verify synchroniz ation. if synchronization is verified then fig 172. map of lower memory
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 874 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory "ok" string is sent to the host. the host should respond by sending the crystal frequency (in khz) at which the part is running. for example, if the part is running at 10 mhz, the response from the host should be "10000". "ok" string is sent to the host after receivin g the crystal frequency. if synchronization is not verified then the auto-baud routine waits again for a synchronization character. for auto-baud to work correctly in case of user invoked isp, the cc lk frequency should be greater than or equal to 10 mhz. for more details on reset, pll and startup/boot code interaction see section 3.10.1 ? pll and startup/boot code interaction ? . once the crystal frequency is received the part is initialized and the isp command handler is invoked. for safety reasons an "unlock" command is required before executing the commands resulting in flash erase/write operations and the "go" command. the rest of the commands can be executed without the unlock command. the unlock command is required to be executed once per isp session. the unlock command is explained in section 38.7 ? isp commands ? on page 881 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 875 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.3.2 communication protocol all isp commands should be sent as single as cii strings. strings should be terminated with carriage return (cr) and/or line fe ed (lf) control characters. extra and characters are ignored. all isp respon ses are sent as terminated ascii strings. data is sent and received in uu-encoded format. 38.3.2.1 isp command format "command parameter_0 parameter_1 ? parameter_n" "data" (data only for write commands). 38.3.2.2 isp response format "return_coderesponse_0response_1 ? response_n" "data" (data only for read commands). 38.3.2.3 isp data format the data stream is in uu-encoded format. the uu-encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ascii ch aracter set. it is more efficient than hex format which converts 1 byte of binary data in to 2 bytes of ascii hex. the sender should send the check-sum after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. the receiver should compare it with the check-sum of the received bytes. if the check-sum matches then the receiver should respond with "ok" to continue further transmission. if the check-sum does not match the receiver should respond with "resend". in response the se nder should retransmit the bytes. 38.3.2.4 isp flow control a software xon/xoff flow control scheme is used to prevent data loss due to buffer overrun. when the data arrives rapidly, the as cii control character dc3 (0x13) is sent to stop the flow of data. data flow is resume d by sending the ascii control character dc1 (0x11). the host should also support the same flow control scheme. 38.3.2.5 isp command abort commands can be aborted by sending the ascii control character "esc" (0x1b). this feature is not documented as a command under "isp commands" section. once the escape code is received the isp command handler waits for a new command. 38.3.2.6 interrupts during iap the on-chip flash memory is not accessib le during iap operations. when the user application code starts executin g, the interrupt vectors from the user flash area are active. the user should either disable interrupts, or en sure that user interrup t vectors are active in ram and that the interrupt handlers reside in ram, before making an iap call (see section 5.4 ? vector table remapping ? ). the iap code does not use or disable interrupts. 38.3.2.7 addresses in iap and isp commands iap and isp commands that reference memory addresses have a limited range. the command descriptions in section 38.7 ? isp commands ? and section 38.8 ? iap commands ? note ram address or flash address or both. ram addresses must be located
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 876 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory in on-chip ram, addresses outside those ranges will be flagg ed as errors. flash addresses must be located in on-chip flash memory, addresses outside that range will be flagged as errors. 38.3.2.8 ram used by isp command isp commands use on-chip ram from 0x1000 0118 to 0x1000 01ff. the user could use this area, but the contents may be lost up on reset. flash programming commands use the top 32 bytes of on-chip ram. the stack is located at ram top - 32. the maximum stack usage is 256 bytes, growing downwards. 38.3.2.9 ram used by boot process prior to entering user program following chip reset, the boot program uses a subset of the ram that is used for isp command handling. this includes location 0x1000 0120 and also parts of the top 32 bytes of on-chip ram. the stack is located at ram top - 32. the maximum stack usage is 32 bytes. if the user program assumes that ram is unchanged during a reset where power is not removed from the device, it is important to be aware of these exceptions. 38.3.2.10 ram used by iap command handler flash programming commands use the top 32 bytes of on-chip ram. the maximum stack usage in the user allocated stack space is 128 bytes, growing downwards.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 877 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.4 boot process flowchart (1) for details on handling the crystal frequency, see section 38.8.9 ? re-invoke isp ? on page 894 (2) for details on available isp commands based on the crp settings see section 38.6 ? code read protection (crp) ? fig 173. boot process flowchart watchdog flag set? crp1/2/3 enabled? yes no initialize reset enable debug yes run isp command handler 2 receive crystal frequency 1 no auto-baud successful? yes run auto-baud user code valid? yes no crp3 enabled? enter isp mode? (p2.10=low) user code valid? yes yes no yes no no a a execute internal user code
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 878 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.5 sector numbers some iap and isp commands operate on "sectors" and specify sector numbers. the following table indicate the correspondence between sector numbers and memory addresses for devices containing 32, 64, 128 , 256 and 512 kb of flash respectively. iap and isp routines are located in the boot rom. table 734. flash sectors details sector number sector size [kb] start address end address 32 kb device 64 kb device 128 kb device 256 kb device 512 kb device 0 4 0x0000 0000 0x0000 0fff x x x x x 1 4 0x0000 1000 0x0000 1fff x x x x x 2 4 0x0000 2000 0x0000 2fff x x x x x 3 4 0x0000 3000 0x0000 3fff x x x x x 4 4 0x0000 4000 0x0000 4fff x x x x x 5 4 0x0000 5000 0x0000 5fff x x x x x 6 4 0x0000 6000 0x0000 6fff x x x x x 7 4 0x0000 7000 0x0000 7fff x x x x x 8 4 0x0000 8000 0x0000 8fff x x x x 9 4 0x0000 9000 0x0000 9fff x x x x 10 (0x0a) 4 0x0000 a000 0x0000 afff x x x x 11 (0x0b) 4 0x0000 b000 0x0000 bfff x x x x 12 (0x0c) 4 0x0000 c000 0x0000 cfff x x x x 13 (0x0d) 4 0x0000 d000 0x0000 dfff x x x x 14 (0x0e) 4 0x0000 e000 0x0000 efff x x x x 15 (0x0f) 4 0x0000 f000 0x0000 ffff x x x x 16 (0x10) 32 0x0001 0000 0x0001 7fff x x x 17 (0x11) 32 0x0001 8000 0x0001 ffff x x x 18 (0x12) 32 0x0002 0000 0x0002 7fff x x 19 (0x13) 32 0x0002 8000 0x0002 ffff x x 20 (0x14) 32 0x0003 0000 0x0003 7fff x x 21 (0x15) 32 0x0003 8000 0x0003 ffff x x 22 (0x16) 32 0x0004 0000 0x0004 7fff x 23 (0x17) 32 0x0004 8000 0x0004 ffff x 24 (0x18) 32 0x0005 0000 0x0005 7fff x 25 (0x19) 32 0x0005 8000 0x0005 ffff x 26 (0x1a) 32 0x0006 0000 0x0006 7fff x 27 (0x1b) 32 0x0006 8000 0x0006 ffff x 28 (0x1c) 32 0x0007 0000 0x0007 7fff x 29 (0x1d) 32 0x0007 8000 0x0007 ffff x
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 879 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.6 code read protection (crp) code read protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip flash and use of the isp can be restricted. when needed, crp is invoked by programming a specific pattern in flash location at 0x0000 02fc. iap commands are not affected by the code read protection. important: any crp change becomes effe ctive only after the device has gone through a power cycle. table 735. code read protection options name pattern programmed in 0x0000 02fc description crp1 0x1234 5678 access to chip via the jtag pins is disabled. this mode allows partial flash update using the following isp commands and restrictions: ? write to ram command can not access ram below 0x1000 0200. this is due to use of the ram by the isp code, see section 38.3.2.8 . ? read memory command: disabled. ? copy ram to flash command: cannot write to sector 0. ? go command: disabled. ? erase sector(s) command: can erase any indivi dual sector except sector 0 only, or can erase all sectors at once. ? compare command: disabled this mode is useful when crp is requir ed and flash field updates are needed but all sectors can not be erased. the compare command is disabled, so in the case of partial flash updates the secondary loader should im plement a checksum mechanism to verify the integrity of the flash. crp2 0x8765 4321 this is similar to crp1 with the following additions: ? write to ram command: disabled. ? copy ram to flash: disabled. ? erase command: only allows erase of all sectors. crp3 0x4321 8765 this is similar to crp2, but isp entry by pulling p2[10] low is disabled if a valid user code is present in flash sector 0. this mode effectively disables isp override using the p2[10] pin. it is up to the user?s application to provide for flash updates by using iap calls or by invoking isp with uart0. caution: if crp3 is selected, no future factory testing can be performed on the device.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 880 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory if any crp mode is enabled and access to the chip is allowed via the isp, an unsupported or restricted isp co mmand will be terminated with return code code_read_protection_enabled. table 736. code read protection hardware/software interaction crp option user code valid p2[10] pin at reset jtag enabled device enters isp mode partial flash update in isp mode none no x yes yes yes yes high yes no na yes low yes yes yes crp1 no x no yes yes yes high no no na yes low no yes yes crp2 no x no yes no yes high no no na yes low no yes no crp3 no x no yes no yes x no no na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 881 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7 isp commands the following commands are accepted by the isp command handler. detailed status codes are supported for each command. the command handler sends the return code invalid_command when an undefined command is received. commands and return codes are in ascii format. cmd_success is sent by isp command handl er only when received isp command has been completely executed and the new isp command can be given by the host. exceptions from this rule are "set baud rate ", "write to ram", "read memory", and "go" commands. 38.7.1 unlock table 737. isp command summary isp command usage described in unlock u ta b l e 7 3 8 set baud rate b ta b l e 7 3 9 echo a ta b l e 7 4 0 write to ram w ta b l e 7 4 1 read memory r

ta b l e 7 4 2 prepare sector(s) for write operation p ta b l e 7 4 3 copy ram to flash c ta b l e 7 4 4 go g

ta b l e 7 4 5 erase sector(s) e ta b l e 7 4 6 blank check sector(s) i ta b l e 7 4 7 read part id j ta b l e 7 4 8 read boot code version k ta b l e 7 5 0 read serial number n ta b l e 7 5 1 compare m ta b l e 7 5 2 table 738. isp unlock command command u input unlock code: 23130 decimal return code cmd_success | invalid_code | param_error description this command is used to unlock flash write, erase, and go commands. example "u 23130" unlocks the flash write/erase & go commands.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 882 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.2 set baud rate when the set baud rate command is used after isp has been re-invoked by a user program (using the ?re-invoke isp? iap command, see section 38.8.9 ), the clocking setup is returned to the initia l state, i.e. running from t he irc with the pll disconnected. 38.7.3 echo 38.7.4 write to ram the host should send the data only after receiving the cmd_success return code. the host should send the check-sum after transmitting 20 uu-encoded lines. the checksum is generated by adding raw data (before uu-encoding) bytes and is reset after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exceed 61 characters (bytes) i.e. it can hold 45 data bytes. when the data fits in less than 20 uu-encoded lines then the ch eck-sum should be of the actual number of bytes sent. the isp command handler compares it with th e check-sum of the received bytes. if the check-sum matches, the isp command handler responds with "ok" to continue further transmission. if the check-sum does not match, the isp command handler responds with "resend". in response the host should retransmit the bytes. table 739. isp set baud rate command command b input baud rate: 9600 | 19200 | 38400 | 57600 | 115200 stop bit: 1 | 2 return code cmd_success | invalid_baud_rate | invalid_stop_bit | param_error description this command is used to change the baud rate. the new baud rate is effective after the command handler sends the cmd_success return code. example "b 57600 1" sets the serial port to baud rate 57600 bps and 1 stop bit. table 740. isp echo command command a input setting: on = 1 | off = 0 return code cmd_success | param_error description the default setting for echo command is on. when on the isp command handler sends the received serial data back to the host. example "a 0" turns echo off.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 883 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.5 read memory the data stream is followed by the command success return code. t he check-sum is sent after transmitting 20 uu-encoded lines. the checksum is generated by adding raw data (before uu-encoding) bytes and is reset after transmitting 20 uu-encoded lines. the length of any uu-encoded line should not exce ed 61 characters (bytes) i.e. it can hold 45 data bytes. when the data fits in less than 20 uu-encoded lines then the check-sum is of actual number of bytes sent. the host sh ould compare it with the checksum of the received bytes. if the check-sum matches then the host should respond with "ok" to continue further transmissi on. if the check-sum does not match then the host should respond with "resend". in response the isp command handler sends the data again. table 741. isp write to ram command command w input start address: ram address where data bytes are to be written. the address should be on a word boundary. the source address must be within an on-chip ram (see section 38.3.2.7 ). number of bytes: number of bytes to be written. count should be a multiple of 4 return code cmd_success | addr_error (address not on word boundary) | addr_not_mapped | count_error (byte count is not multiple of 4) | param_error | code_read_protection_enabled description this command is used to download data to ra m. data should be in uu-encoded format. this command is blocked when code read protection levels crp2 or crp3 are enabled. example "w 268435968 4" writes 4 bytes of data to address 0x1000 0200. table 742. isp read memory command command r input start address: address from where data bytes are to be read. the address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). number of bytes: number of bytes to be read. count should be a multiple of 4. return code cmd_success followed by | addr_error (address not on word boundary) | addr_not_mapped | count_error (byte count is not a multiple of 4) | param_error | code_read_protection_enabled description this command is used to read data from ram or flash memory. this command is blocked when any level of code read protection is enabled. example "r 268435968 4" reads 4 bytes of data from address 0x1000 0200.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 884 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.6 prepare sector(s) for write ope ration this command makes flash write/erase operation a two step process. 38.7.7 copy ram to flash table 743. isp prepare sector(s) for write operation command command p input start sector number end sector number: should be greater than or equal to start sector number. return code cmd_success | busy | invalid_sector | param_error description this command must be executed before executin g "copy ram to flash" or "erase sector(s)" command. successful execution of the "copy ram to flash" or "e rase sector(s)" command causes relevant sectors to be protected again. to prepare a single sector use the same "start" and "end" sector numbers. example "p 0 0" prepares the flash sector 0. table 744. isp copy command command c input flash address(dst): destination flash address where data bytes are to be written. the destination address should be on a 256 byte boundary. the destination address must be within the on-chip flash memory (see section 38.3.2.7 ). ram address(src): source ram address from where data bytes are to be read. the source address must be within an on-chip ram (see section 38.3.2.7 ). number of bytes: number of bytes to be written. should be 256 | 512 | 1024 | 4096. return code cmd_success | src_addr_error (address not on word boundary) | dst_addr_error (address not on correct boundary) | src_addr_not_mapped | dst_addr_not_mapped | count_error (byte count is not 256 | 512 | 1024 | 4096) | sector_not_prepared_for write_operation | busy | cmd_locked | param_error | code_read_protection_enabled description this command is used to program the flash memory. the "prepare sector(s) for write operation" command should precede this command. the affected sectors are automatically protected again once the copy command is successfully executed. this command is blocked when code read protection levels crp2 or crp3 are enabled. when code read protection level crp1 is enabled, individual sectors other than sector 0 can be written. example "c 0 268468224 512" copies 512 bytes from the ram address 0x1000 8000 to the flash address 0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 885 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.8 go
when the go command is used, execution begins at the specified address (assuming it is an executable address) with the device left as it was configured for the isp code. this means that some things are different than th ey would be for entering user code directly following a chip reset. the cpu will be running from the 12 mhz irc with the plls turned off. 38.7.9 erase sector(s) table 745. isp go command command g input address: flash or ram address from which the code execution is to be started. this address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). mode (retained for backward compatibility): t (execute program in thumb mode) | a (not allowed). return code cmd_success | addr_error | addr_not_mapped | cmd_locked | param_error | code_read_protection_enabled description this command is used to execute a program residing in ram or flash memory. it may not be possible to return to the isp command handler once this comma nd is successfully executed. this command is blocked when any level of code read protection is enabled. example "g 0 t" branches to address 0x0000 0000. table 746. isp erase sector command command e input start sector number end sector number: should be greater than or equal to start sector number. return code cmd_success | busy | invalid_sector | sector_not_prepared_for_write_operation | cmd_locked | param_error | code_read_protection_enabled description this command is used to erase one or more se ctor(s) of on-chip flash memory. this command is blocked when code read protection level crp3 is enabled. when code read protection level crp1 is enabled, individual sectors other than sector 0 can be erased. al l sectors can be erased at once in crp1 and crp2. example "e 2 3" erases the flash sectors 2 and 3.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 886 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.10 blank check sector(s) 38.7.11 read part identification number 38.7.12 read boot co de version number table 747. isp blank check sector command command i input start sector number: end sector number: should be greater than or equal to start sector number. return code cmd_success | sector_not_blank (followed by ) | invalid_sector | param_error | description this command is used to blank check one or more sectors of on-chip flash memory. example "i 2 3" blank checks the flash sectors 2 and 3. table 748. isp read part identification command command j input none. return code cmd_success followed by part identification number in ascii (see table 749 ? part identification numbers ? ). description this command is used to read the part identification number. the part identification number maps to a feature subset within a device family. this number will not normally change as a result of technical revisions. table 749. part identification numbers device ascii/dec coding hex coding lpc4088 1209876295 0x481d 3f47 lpc4078 1192836935 0x4719 3f47 lpc4076 1192828739 0x4719 1f43 lpc4074 1191252274 0x4701 1132 table 750. isp read boot code version number command command k input none return code cmd_success followed by 2 byte s of boot code vers ion number in ascii format. it is to be interpreted as .< byte0(minor)>. description this command is used to read the boot code version number.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 887 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.13 read device serial number 38.7.14 compare table 751. isp read device serial number command command n input none. return code cmd_success followed by the device serial number in 4 decimal ascii groups, each representing a 32-bit value. description this command is used to read the device serial num ber. the serial number may be used to uniquely identify a single unit among all devices of the same part number. table 752. isp compare command command m input address1 (dst): starting flash or ram address of data bytes to be compared. the address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). address2 (src): starting flash or ram address of data bytes to be compared. the address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). number of bytes: number of bytes to be compared; should be a multiple of 4. return code cmd_success | (sourc e and destination data are equal) compare_error | (followed by the offset of first mismatch) count_error (byte count is not a multiple of 4) | addr_error | addr_not_mapped | param_error | description this command is used to compare the memory contents at two locations. this command is blocked when any level of code read protection is enabled. example "m 8192 268435968 4" compares 4 bytes from the ram address 0x1000 0200 to the 4 bytes from the flash address 0x2000.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 888 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.7.15 isp return codes table 753. isp return codes summary return code mnemonic description 0 cmd_success command is executed successfully. sent by isp handler only when command given by the host has been completely and successfully executed. 1 invalid_command invalid command. 2 src_addr_error source address is not on word boundary. 3 dst_addr_error destination address is not on a correct boundary. 4 src_addr_not_mapped source address is not mapped in the memory map. count value is taken into consideration where applicable. 5 dst_addr_not_mapped destination address is not mapped in the memory map. count value is taken into consideration where applicable. 6 count_error byte count is not multiple of 4 or is not a permitted value. 7 invalid_sector sector number is invalid or end sector number is greater than start sector number. 8 sector_not_blank sector is not blank. 9 sector_not_prepared_ for_write_operation command to prepare sector for write operation was not executed. 10 compare_error source and destination data not equal. 11 busy flash programming hardware interface is busy. 12 param_error insufficient number of parameters or invalid parameter. 13 addr_error address is not on word boundary. 14 addr_not_mapped address is not mapped in the memory map. count value is taken in to consideration where applicable. 15 cmd_locked command is locked. 16 invalid_code unlock code is invalid. 17 invalid_baud_rate invalid baud rate setting. 18 invalid_stop_bit invalid stop bit setting. 19 code_read_protection_ enabled code read protection enabled.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 889 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.8 iap commands for in application programming the iap routine should be called with a word pointer in register r0 pointing to memory (ram) c ontaining command code and parameters. the result from the iap command is returned in the table pointed to by register r1. the user can reuse the command table for result by passing the same pointer in registers r0 and r1. the parameter table should be big enough to hold all the results in case if number of results are more than number of paramete rs. parameter passing is illustrated in the figure 174 . the number of parameters and results vary according to the iap command. the maximum number of parameters is 5, passed to the "copy ram to flash" command. the maximum number of results is 4, returned by the "read device serial number" command. the command handler sends the status code invalid_command when an undefined command is received. the iap routine resides at location 0x1fff 1ff0. the iap function could be called in the following way using c. define the iap location entry point. bit 0 of the iap location is set since the cortex-m4 uses only thumb mode. #define iap_location 0x1fff1ff1 define data structure or pointers to pass i ap command table and result table to the iap function: unsigned long command[5]; unsigned long output[5]; or unsigned long * command; unsigned long * output; command=(unsigned long *) 0x... output= (unsigned long *) 0x... define a pointer to function type, which take s two parameters and re turns void. note the iap returns the result with the base address of the table residing in r1. typedef void (*iap)(unsigned int [],unsigned int[]); iap iap_entry; setting function pointer: iap_entry=(iap) iap_location; whenever you wish to call iap you could use the following statement. iap_entry (command, output); the iap call could be simplified further by using the symbol definition file feature supported by arm linker in ads (arm deve loper suite). you could also call the iap routine using assembly code. note that the first entry in the command table is the iap command, followed by any required command parameters, starting with param0. the first entry in the output table is the return code, followed by any other results, starting with result0.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 890 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory as per the arm specification (the arm thumb procedure call standard sws espc 0002 a-05) up to 4 parameters can be passed in the r0, r1, r2 and r3 registers respectively. additional parame ters are passed on the stack. up to 4 parameters can be returned in the r0, r1, r2 and r3 registers respectively. additional parameters are returned indirectly via memory. some of the iap calls require more than 4 parameters. if the arm suggested scheme is used for the paramete r passing/returning then it might create problems due to difference in the c compiler implementation from different vendors. the suggested parameter passing scheme reduces such risk. the flash memory is not accessible during a write or erase operation. iap commands, which results in a flash write/erase operation, use 32 bytes of space in the top portion of the on-chip ram for execution. the user program should not be use this space if iap flash programming is permitted in the application. table 754. iap command summary iap command command code described in prepare sector(s) for write operation 50 decimal table 755 copy ram to flash 51 decimal table 756 erase sector(s) 52 decimal table 757 blank check sect or(s) 53 decimal table 758 read part id 54 decimal table 759 read boot code version 55 decimal table 760 read device serial number 58 decimal table 761 compare 56 decimal table 762 reinvoke isp 57 decimal table 763 fig 174. iap parameter passing command code parameter 0 parameter 1 parameter n status code result 0 result 1 result n command parameter table command result table arm register r0 arm register r1
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 891 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.8.1 prepare sector(s) for write operation this command makes flash write/erase operation a two step process. 38.8.2 copy ram to flash table 755. iap prepare sector(s) for write operation command command prepare sector(s) for write operation input command code: 50 decimal param0: start sector number param1: end sector number (should be greater than or equal to start sector number). return code cmd_success | busy | invalid_sector result none description this command must be executed before executin g "copy ram to flash" or "erase sector(s)" command. successful execution of the "copy ram to flash" or "e rase sector(s)" command causes relevant sectors to be protected again. to prepare a single sector use the same "start" and "end" sector numbers. table 756. iap copy ram to flash command command copy ram to flash input command code: 51 decimal param0(dst): destination flash address where data bytes are to be written. this address should be on a 256 byte boundary. the destination address must be within the on-chip flash memory (see section 38.3.2.7 ). param1(src): source ram address from which data bytes are to be read. the address should be on a word boundary. the source address must be within an on-chip ram (see section 38.3.2.7 ). param2: number of bytes to be written. should be 256 | 512 | 1024 | 4096. param3: cpu clock frequency (cclk) in khz. return code cmd_success | src_addr_error (address not a word boundary) | dst_addr_error (address not on correct boundary) | src_addr_not_mapped | dst_addr_not_mapped | count_error (byte count is not 256 | 512 | 1024 | 4096) | sector_not_prepared_for_write_operation | busy | result none description this command is used to program the flash memo ry. the affected sectors should be prepared first by calling "prepare sector for write operation" command. the affected sectors are automatically protected again once the copy command is successfully executed.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 892 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.8.3 erase sector(s) 38.8.4 blank check sector(s) 38.8.5 read part identification number table 757. iap erase sector(s) command command erase sector(s) input command code: 52 decimal param0: start sector number param1: end sector number (should be greater than or equal to start sector number). param2: cpu clock frequency (cclk) in khz. return code cmd_success | busy | sector_not_prepared_for_write_operation | invalid_sector result none description this command is used to erase a sector or multiple sectors of on-chip flash memory. to erase a single sector use the same "start" and "end" sector numbers. table 758. iap blank check sector(s) command command blank check sector(s) input command code: 53 decimal param0: start sector number param1: end sector number (should be greater than or equal to start sector number). return code cmd_success | busy | sector_not_blank | invalid_sector result result0: offset of the first non blank word location if the status code is sector_not_blank. result1: contents of non blank word location. description this command is used to blank check a sector or multiple sectors of on-chip flash memory. to blank check a single sector use the same "start" and "end" sector numbers. table 759. iap read part identification number command command read part identification number input command code: 54 decimal parameters: none return code cmd_success result result0: part identification number. description this command is used to read the part identific ation number. the value returned is the hexadecimal version of the part id. see table 749 ? part identification numbers ? .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 893 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.8.6 read boot code version number 38.8.7 read device serial number 38.8.8 compare table 760. iap read boot code version number command command read boot code version number input command code: 55 decimal parameters: none return code cmd_success result result0: 2 bytes of boot code version number. it is to be interpreted as . description this command is used to read the boot code version number. table 761. iap read device serial number command command read device serial number input command code: 58 decimal parameters: none return code cmd_success result result0: first 32-bit word of device identification number (at the lowest address) result1: second 32-bit word of device identification number result2: third 32-bit word of device identification number result3: fourth 32-bit word of device identification number description this command is used to read the device identification number. the serial number may be used to uniquely identify a single unit among all devices of the same part number. table 762. iap compare command command compare input command code: 56 decimal param0(dst): starting flash or ram address of data bytes to be compared. the address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). param1(src): starting flash or ram address of data bytes to be compared. the address should be on a word boundary. the address must be within on-chip flash or on-chip ram (see section 38.3.2.7 ). param2: number of bytes to be compared; should be a multiple of 4. return code cmd_success | compare_error | count_error (byte count is not a multiple of 4) | addr_error | addr_not_mapped result result0: offset of the first mismatch if the status code is compare_error. description this command is used to compare the memory contents at two locations. the result may not be correct when the source or destination includes any of the first 64 bytes starting from address zero. the first 64 bytes can be re-mapped to ram.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 894 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.8.9 re-invoke isp 38.8.10 iap status codes table 763. re-invoke isp command compare input command code: 57 decimal return code none result none. description this command is used to invoke the boot loader in isp mode. it maps boot vectors, resets the clocking configuration, configures uart0 pins rx and tx, resets timer1 and resets the u0fdr (see section 18.6.11 ). this command may be used when a valid us er program is present in the internal flash memory and the p2[10] pin is not accessible to force the isp mode. table 764. iap status codes summary status code mnemonic description 0 cmd_success command is executed successfully. 1 invalid_command invalid command. 2 src_addr_error source address is not on a word boundary. 3 dst_addr_error destination address is not on a correct boundary. 4 src_addr_not_mapped source address is not mapped in the memory map. count value is taken in to consideration where applicable. 5 dst_addr_not_mapped destination address is not mapped in the memory map. count value is taken in to consideration where applicable. 6 count_error byte count is not multiple of 4 or is not a permitted value. 7 invalid_sector sector number is invalid. 8 sector_not_blank sector is not blank. 9 sector_not_prepared_ for_write_operation command to prepare sector for write operation was not executed. 10 compare_error source and destination data is not same. 11 busy flash programming hardware interface is busy.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 895 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.9 jtag flash programming interface debug tools can write parts of the flash image to the ram and then execute the iap call "copy ram to flash" repeatedly with proper offset. 38.10 flash signature generation the flash module contains a built-in signatu re generator. this generator can produce a 128-bit signature from a range of flash memory. a typical usage is to verify the flashed contents against a calculated signature (e.g. during programming). the address range for generating a signature must be aligned on flash-word boundaries, i.e. 128-bit boundaries. once started, si gnature generation completes independently. while signature generation is in progress, t he flash memory cannot be accessed for other purposes, and an attempted read will cause a wait state to be as serted until signature generation is complete. code outside of the flash (e.g. internal ram) can be executed during signature generation. this can include interrupt services, if the interrupt vector table is re-mapped to memory other than the flash memory. the code that initiates signature generation should also be placed outside of the flash memory. 38.10.1 register descriptio n for signature generation 38.10.1.1 signature generation address and control registers these registers control automatic signature generation. a signature can be generated for any part of the flash memory contents. the address range to be used for generation is defined by writing the start address to the signature start address register (fmsstart) and the stop address to the si gnature stop address register (fmsstop. the start and stop addresses must be aligned to 128-bit boun daries and can be derived by dividing the byte address by 16. signature generation is starte d by setting the sig_start bit in the fmsstop register. setting the sig_start bit is typically combined with the signature stop address in a single write. table 765. register overview: flash controller (base address 0x0020 0000) name access address offset description reset value reference fmsstart r/w 0x020 signature start address register 0 table 766 fmsstop r/w 0x024 signature stop-address register 0 table 767 fmsw0 ro 0x02c 128-bit signature word 0 - table 768 fmsw1 ro 0x030 128-bit signature word 1 - table 769 fmsw2 ro 0x034 128-bit signature word 2 - table 770 fmsw3 ro 0x038 128-bit signature word 3 - table 771 stat ro 0xfe0 signature generation status register 0 table 772 statclr wo 0xfe8 signature generation status clear register - table 773
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 896 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory table 766 and table 767 show the bit assignments in the fmsstart and fmsstop registers respectively. 38.10.1.2 signature generation result registers the signature generation result registers re turn the flash signature produced by the embedded signature generator. the 128-bit signa ture is reflected by the four registers fmsw0, fmsw1, fmsw2 and fmsw3. the generated flash signature can be used to verify the flash memory contents. the generated signature can be compared with an expected signature and thus makes saves time and code space. the method for generating the signature is described in section 38.10.2 . table 771 show bit assignment of the fmsw0 and fmsw1, fmsw2, fmsw3 registers respectively. table 766. flash module signature start register (fmsstart - 0x0020 0020) bit description bit symbol description reset value 16:0 start signature generation start address (corresponds to ahb byte address bits[20:4]). 0 31:17 - reserved. read value is undefined, only zero should be written. na table 767. flash module signature stop register (fmsstop - 0x0020 0024) bit description bit symbol value description reset value 16:0 stop bist stop address divided by 16 (corresponds to ahb byte address [20:4]). 0 17 sig_start start control bit for signature generation. 0 0 signature generation is stopped 1 initiate signature generation 31:18 - reserved. read value is undefined, only zero should be written. na table 768. fmsw0 register bit description (fmsw0, address: 0x0020 002c) bit symbol description reset value 31:0 sw0_31_0 word 0 of 128-bit signature (bits 31 to 0). - table 769. fmsw1 register bit description (fmsw1, address: 0x0020 0030) bit symbol description reset value 31:0 sw1_63_32 word 1 of 128-bit signature (bits 63 to 32). - table 770. fmsw2 register bit description (fmsw2, address: 0x0020 0034) bit symbol description reset value 31:0 sw2_95_64 word 2 of 128-bit signature (bits 95 to 64). - table 771. fmsw3 register bit description (fmsw3, address: 0x0020 0038) bit symbol description reset value 31:0 sw3_127_96 word 3 of 128-bit signature (bits 127 to 96). -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 897 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.10.1.3 flash module status register the read-only fmstat register provides a means of determining when signature generation has comple ted. completion of si gnature generation ca n be checked by polling the sig_done bit in fmstat. sig_done should be cleared via the fmstatclr register before starting a signature genera tion operation, otherwise the status might indicate completion of a previous operation. 38.10.1.4 flash module status clear register the fmstatclr register is used to clear the signature generation completion flag. table 772. flash module status register (stat - 0x0020 0fe0) bit description bit symbol description reset value 1:0 - reserved. the value read from a reserved bit is not defined. na 2 sig_done when 1, a previously started signature generation has completed. see fmstatclr register description for clearing this flag. 0 31:2 - reserved. the value read from a reserved bit is not defined. na table 773. flash module status clear register (statclr - 0x0x0020 0fe8) bit description bit symbol description 1:0 - reserved. read value is undefined, only zero should be written. 2 sig_done_clr writing a 1 to this bits clears the signature generation completion flag (sig_done) in the fmstat register. 31:2 - reserved. read value is undefined, only zero should be written.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 898 of 942 nxp semiconductors UM10562 chapter 38: lpc408x/407x flash memory 38.10.2 algorithm and procedure for signature generation signature generation a signature can be generated for any part of the flash contents. the address range to be used for signature generation is defined by writing the start address to the fmsstart register, and the stop address to the fmsstop register. the signature generation is started by writing a ?1? to fmsstop.misr_start. starting the signature generation is typically combined with defining the stop address, which is done in another field fmsstop.fmsstop of the same register. the time that the signature generation takes is proportional to the address range for which the signature is generated. reading of the flash memory for signature generation uses a self-timed read mechanism and does not de pend on any configurable timing settings for the flash. a safe estimation for the duration of the signature generation is: duration = int( (60 / tcy) + 3 ) x (fmsstop - fmsstart + 1) when signature generation is triggered via software, the duration is in ahb clock cycles, and tcy is the time in ns for one ahb clock. the sig_done bit in fmstat can be polled by software to determine when signature generation is complete. if signature generation is triggered via jtag, the duration is in jtag tck cycles, and tcy is the time in ns for one jtag clock. polling the sig_done bit in fmstat is not possible in this case. after signature generation, a 128-bit signat ure can be read from the fmsw0 to fmsw3 registers. the 128-bit signature reflects the co rrected data read from the flash. the 128-bit signature reflects flash parity bits and check bit values. content verification the signature as it is read from the fmsw 0 to fmsw3 registers must be equal to the reference signature. the algorithms to de rive the reference signature is given in figure 175 . fig 175. algorithm for generating a 128 bit signature sign = 0 for address = fmstart.fmstart to fmstop.fmstop { for i = 0 to 126 nextsign[i] = f_q[address][i] xor sign[i+1] nextsign[127] = f_q[address][127] xor sign[0] xor sign[2] xor sign[27] xor sign[29] sign = nextsign } signature128 = sign
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 899 of 942 39.1 features ? supports both standard jtag and arm serial wire debug modes. ? direct debug access to all memories, registers, and peripherals. ? no target resources are required for the debugging session. ? trace port provides cpu in struction trace capability. ? eight breakpoints. six instruction breakpoints that can also be used to remap instruction addresses for code patches. two data comparators that can be used to remap addresses for patches to literal values. ? four data watchpoints that can also be used as trace triggers. ? instrumentation trace macrocell allows additional software controlled trace capability. 39.2 introduction debug and trace functions are integrated into the arm cortex-m4. serial wire debug and trace functions are supported in addition to a standard jtag debug and parallel trace functions. the arm cortex-m4 is configured to support up to eight breakpoints and four watchpoints. 39.3 description debugging with the lpc408x/407x defaults to jtag. once in the jtag debug mode, the debug tool can switch to serial wire debug mode. instruction trace is supported by a 4-bit parallel interface using 5 pins. note that the trace function available for the cortex-m4 is function ally very different than the trace that was available for previous arm7 based device s, using only 5 pins instead of 10. UM10562 chapter 39: lpc408x/407x jtag, debug, and trace rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 900 of 942 nxp semiconductors UM10562 chapter 39: lpc408x/407x jtag, debug, and trace 39.4 pin description the tables below indicate the various pin func tions related to debug and trace. some of these functions share pins with other functions which therefore may not be used at the same time. use of the jtag port excludes use of serial wire debug and serial wire output. use of the parallel trace requires 5 pins that may be part of the user application, limiting debug possibilitie s for those features. table 774. jtag pin description pin name type description jtag_tck input jtag test clock. this pin is the clock for debug logic when in the jtag debug mode. jtag_tms input jtag test mode select. the tms pin selects the next state in the tap state machine. this pin includes an internal pull-up for compliance with ieee 1149.1. jtag_tdi input jtag test data in. this is the serial data input for the shift register. this pin includes an internal pull-up for compliance with ieee 1149.1. jtag_tdo output jtag test data output. this is the serial data output from the shift register. data is shifted out of the device on the negative edge of the tck signal. jtag_trst input jtag test reset. the jtag_trst pin can be used to reset the test logic within the debug logic. this pin includes an internal pull-up for compliance with ieee 1149.1. table 775. serial wire debug pin description pin name type description swdclk input serial wire clock. this pin is the clock for debug logic when in the serial wire debug mode. this is an internally selected alternate function for the jtag_tck pin. swdio input / output serial wire debug data input/output. the swdio pin is used by an external debug tool to communicate with and control the cortex-m4 cpu. th is is an internally selected alternate function for the jtag_tms pin. swo output serial wire output. the swo pin optionally provides data from the itm and/or the etm for an external debug tool to evaluate. this is an internally selected alternate function for the jtag_tdo pin. table 776. parallel trace pin description pin name type description traceclk input trace clock. this pin provides the sample clock for trace data on the tracedata pins when tracing is enabled by an external debug tool. tracedata[3:0] output trace data bits 3 to 0. these pins provide etm trace data when tracing is enabled by an external debug tool. the debug tool can then interpret the compressed information and make it available to the user.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 901 of 942 nxp semiconductors UM10562 chapter 39: lpc408x/407x jtag, debug, and trace 39.5 debug connections the lpc408x/407x supplies dedicated pins for jtag and serial wire debug (swd). when a debug session is started, the part will be in jtag debug mode as recommended by arm ltd at the time of design. once in debug mode, the debugger can switch the device to swd mode. connections from a target board to the debugger can vary. selecting a debug connector to add to a new board design depends on the de bug tools that will be used. for example, debug tools for arm-based devices in the past have used a standard connection as shown in figure 176 . this diagram has been adapted to fit the lpc408x/407x, taking into account the pins that have built-in pull-ups. newer tools may use a small debug-only connector as shown in figure 177 . if the debug trace feature will be used, th ere is also a debug-with-trace connector spec ification as shown in figure 178 . these 2 connector pinouts are defined in arm ltd?s coresight? components technical reference manual. please note that any debug connection scheme should be checked with the tool ven dor before an application board is designed. fig 176. arm standard jtag connector 101110 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 +3.3v jtag_trstn jtag_tdi jtag_tms jtag_tclk jtag_tdo nreset +3.3v +3.3v 10k to 100k 20-pin 0.10" spacing dual-row header
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 902 of 942 nxp semiconductors UM10562 chapter 39: lpc408x/407x jtag, debug, and trace 39.6 jtag tap identification the jtag tap controller contains device id that can be used by debugging software to identify the general type of device. more detailed device information is available through isp/iap commands (see section 38.7 and section 38.8 ). for the lpc408x/407x family, this id value is 0x410f c241. fig 177. cortex debug connector fig 178. cortex debug & etm connector 101110 1 3 5 7 9 2 4 6 8 10 +3.3v jtag_tms/swdio jtag_tck/swdclk jtag_tdo/swo jtag_tdi nreset 10k to 100k +3.3v key 10-pin 0.05" spacing dual-row header 101110 key 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 +3.3v jtag_tms/swdio jtag_tck/swdclk jtag_tdo/swo jtag_tdi nreset traceclk tracedata[0] tracedata[1] tracedata[2] tracedata[3] +3.3v 10k to 100k 20-pin 0.05" spacing dual-row header
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 903 of 942 nxp semiconductors UM10562 chapter 39: lpc408x/407x jtag, debug, and trace 39.7 debug notes important: the user should be aware of certai n limitations during debugging. the most important is that, due to limitations of the cortex-m4 integration, the device cannot wake up in the usual manner from deep sleep and power-down modes. it is recommended not to use these modes during debug. once an application is downloaded via jt ag/swd interface, the usb to swd/jtag debug adapter should be removed from the targ et board, and thereaf ter, power cycle the device to allow wake-up from deep sleep and power-down modes. another issue is that debug mode changes the way in which reduced power modes are handled by the cortex-m4 cpu. this causes power modes at the debug level to be different from normal mode operation. thes e differences mean that power measurements should not be made while de bugging, the results will be higher than during normal operation in an application. during a debugging session, the system tick timer is automatically stopped whenever the cpu is stopped. other peripherals are not affected. debugging is disabled if code read protection is enabled. 39.8 debug memory re-mapping following chip reset, a portion of the boot rom is mapped to address 0 so that it will be automatically executed. the boot rom switches the map to point to flash memory prior to user code being executed. in this way a user normally does not need to know that this re-mapping occurs. however, when a debugger halts cpu execution immediately following reset, the boot rom is still mapped to addre ss 0 and can cause confusion. ideally, the debugger should correct the mapping automatically in this case, so that a user does not need to deal with it. 39.8.1 memory mapping control register the memmap register allows switch the mapping of the bottom of memory, including default reset and interrupt vectors, between the boot rom and the bottom of on-chip flash memory. table 777. memory mapping control register (memmap - 0x400f c040) bit description bit symbol value description reset value 0 map memory map control. 0 0 boot mode. a portion of the boot rom is mapped to address 0. 1 user mode. the on-chip flash memory is mapped to address 0. 31:1 - reserved. read value is undefined, only zero should be written. na
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 904 of 942 40.1 arm cortex-m4 details arm limited publishes the document ?cortex?-m4 devices generic user guide?, which is available on their website at: ? for the online searchable, hyperlinked version: infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/index.html ? for the adobe pdf formatted file: infocenter.arm.com/help/topic/com.arm.doc.dui0553a/dui0553a_cortex_m4_dgug.pdf this section of this manual describes the cortex-m4 implementation options and any other distinctions that apply for the lpc408x/407x devices. 40.1.1 cortex-m4 implementation options the arm document ?cortex?-m4 devices g eneric user guide? lists a number of implementation options. these options and the selections for the lpc408x/407x are given below. ? inclusion of mpu: lpc408x/407x devices include the mpu. the mpu provides fine grain memory control, enabling applications to implement security privilege levels, separating code, data and stack on a task-by-task basis. ? inclusion of fpu: lpc408x/407x devices include the fpu. the fpu supports single-precision floating-point computation functionality in compliance with the ansi/ieee standard 754-2008. the fpu provides add, subtract, multiply, divide, multiply and accumulate, and square root operations. it also performs a variety of conversions between fixed-point, floating-point, and integer data formats. ? number of interrupts: lpc408x/407x dev ices implement 44 interrupts. not all interrupts are available on all part numbers. ? number of priority bits: lpc408x/407x de vices implement 5 interrupt priority bits. ? inclusion of the wic: lpc408x/407x devices include the wic. ? sleep mode power-saving: nxp microcontro llers extend the number of reduced power modes beyond what is directly supported by the cortex-m4. details all available reduced po wer modes and wake-up possibilit ies on the lpc408x/407x can be found in section 3.12 ? power control ? . ? register reset values: lpc408x/407x device s do not reset the register bank when the device is reset. ? endianness: lpc408x/407x devices use little endian memory organization. specific peripheral blocks (such as an external memory controller, dma controller, or lcd controller) may support little endian organization for special purposes. ? memory features: the memory map for lp c408x/407x devices can be found in section 2.2 ? memory maps ? . ? bit-banding: lpc408x/407x devices include bit bandi ng. apb peripherals and the peripheral srams are located in bit-band space. UM10562 chapter 40: arm cortex-m4 appendix rev. 1 ? 13 september 2012 user manual
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 905 of 942 nxp semiconductors UM10562 chapter 40: arm cortex-m4 appendix ? systick timer: the systick calibration re gister is implemented on lpc408x/407x devices, for details see section 25.5 ? register description ? . in addition, there are debug and trace options: ? debug options: see section 39.1 . ? trace options: see section 39.1 .
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 906 of 942 41.1 abbreviations UM10562 chapter 41: supplementary information rev. 1 ? 13 september 2012 user manual table 778. abbreviations acronym description adc analog-to-digital converter ahb advanced high-performance bus amba advanced microcontroller bus architecture apb advanced peripheral bus bod brownout detection can controller area network dac digital-to-analog converter dma direct memory access emc external memory controller eop end of packet etm embedded trace macrocell gpio general purpose input/output i2c inter-ic control bus i2s inter-ic sound bus irda infrared data association jtag joint test action group mii media independent interface (ethernet related) miim media independent interface management (ethernet related) phy physical la yer interface pll phase-locked loop pwm pulse width modulator qei quadrature encoder interface rmii reduced media independent interface (ethernet related) se0 single ended zero (usb related) spi serial peripheral interface spifi spi flash interface ssi serial synchronous interface ssp synchronous serial port swd serial wire debug uart universal asynchronous receiver/transmitter usb universal serial bus
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 907 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 41.2 legal information 41.2.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 41.2.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. 41.2.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v.
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 908 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 41.3 tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .8 table 2. ordering options for lpc408x/407x parts . . . . .8 table 3. memory usage and details . . . . . . . . . . . . . . . .13 table 4. ahb peripherals and base addresses . . . . . . .16 table 5. apb0 peripherals and base addresses . . . . . .16 table 6. apb1 peripherals and base addresses . . . . . .17 table 7. matrix arbitration register (matrix_arb - 0x400f c188) bit description. . . . . . . . . . . . . . . . . . . . .18 table 8. pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 9. register overview: system control (base address 0x400f c000) . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 10. pll control registers (pllcon[0:1] - addresses 0x400f c080 (pllcon0) and 0x400f c0a0 (pllcon1)) bit description. . . . . . . . . . . . . . . .24 table 11. pll configuration registers (pllcfg[0:1] - addresses 0x400f c084 (pllcfg0) and 0x400f c0a4 (pllcfg1)) bit description . . . .24 table 12. pll status registers (pllstat[0:1] - addresses 0x400f c088 (pllstat0) and 0x400f c0a8 (pllstat1)) bit description . . . . . . . . . . . . . . .25 table 13. pll feed registers (pllfeed[0:1] - addresses 0x400f c08c (pllfeed0) and 0x400f c0ac (pllfeed1)) bit description . . . . . . . . . . . . . . .26 table 14. power mode control register (pcon - address 0x400f c0c0) bit description . . . . . . . . . . . . . .27 table 15. encoding of reduced power modes . . . . . . . . .28 table 16. power control for peripherals register (pconp - address 0x400f c0c4) bit description . . . . . . .29 table 17. power control for peripherals register (pconp1 - address 0x400f c0c8) bit description . . . . . . .30 table 18. power boost control register (pboost - address 0x400f c1b0) bit description . . . . . . . . . . . . . .30 table 19. emc clock selection register (emcclksel - address 0x400f c100) bit description . . . . . . .31 table 20. cpu clock selection register (cclksel - address 0x400f c104) bit description . . . . . . .32 table 21. usb clock selection register (usbclksel - address 0x400f c108) bit description . . . . . . .32 table 22. clock source selection register (clksrcsel - address 0x400f c10c) bit description . . . . . . .33 table 23. peripheral clock selection register (pclksel - address 0x400f c1a8) bit description . . . . . . .33 table 24. spifi clock select ion register (spificlksel - address 0x400f c1b4) bit description . . . . . . .34 table 25. external interrupt flag register (extint - address 0x400f c140) bit description . . . . . . . . . . . . . .35 table 26. external interrupt mode register (extmode - address 0x400f c148) bit description . . . . . . .36 table 27. external interrupt po larity register (extpolar - address 0x400f c14c) bit description . . . . . . .37 table 28. reset source identification register (rsid - address 0x400f c180) bit description . . . . . . .38 table 29. reset control register 0 (rstcon0 - address 0x400f c1cc) bit description. . . . . . . . . . . . . .39 table 30. reset control register 1 (rstcon1 - address 0x400f c1d0) bit description . . . . . . . . . . . . . .40 table 31. delay control register (emcdlyctl - 0x400f c1dc) bit description. . . . . . . . . . . . . . . . . . . . 41 table 32. emc calibration register (emccal - 0x400f c1e0) bit description . . . . . . . . . . . . . . . . . . . . 42 table 33. system controls and status register (scs - address 0x400f c1a0) bit description. . . . . . . 44 table 34. lcd configuration register (lcd_cfg, address - 0x400f c1b8) bit description. . . . . . . . . . . . . . 45 table 35. can sleep clear register (cansleepclr - address 0x400f c110) bit description . . . . . . . 46 table 36. can wake-up flags register (canwakeflags - address 0x400f c114) bit description . . . . . . 46 table 37. usb interrupt status register - (usbintst - address 0x400f c1c0) bit description. . . . . . . 47 table 38. dma request select register bit description . 48 table 39. clock output configuration register (clkoutcfg - 0x400f c1c8) bit description 50 table 40. external interrupt registers. . . . . . . . . . . . . . . . 56 table 41. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) low frequency mode (oscrange = 0, see table 33 ) . . . . . . . . . . . . . . . . . . . . . . . . 58 table 42. recommended values for c x1/x2 in oscillation mode (crystal and external components parameters) high frequency mode (oscrange = 1, see table 33 ) . . . . . . . . . . . . . . . . . . . . . . . . 58 table 43. pll1 registers . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 44. elements determining pll frequency . . . . . . . 64 table 45. pll multiplier values . . . . . . . . . . . . . . . . . . . . 65 table 46. pll divider values . . . . . . . . . . . . . . . . . . . . . . 66 table 47. power control registers . . . . . . . . . . . . . . . . . . 71 table 48. summary of flash accelerator registers . . . . . . 76 table 49. flash accelerator configuration register (flashcfg - address 0x400f c000) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 50. connection of interrupt sources to the vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . 80 table 51. nvic register map . . . . . . . . . . . . . . . . . . . . . 83 table 52. interrupt set-enable register 0 register . . . . . 84 table 53. interrupt set-enable register 1 register . . . . . 85 table 54. interrupt clear-enable register 0 . . . . . . . . . . 86 table 55. interrupt clear-enable register 1 register . . . 87 table 56. interrupt set-pending register 0 register . . . . 88 table 57. interrupt set-pending register 1 register . . . . 89 table 58. interrupt clear-pending register 0 register . . 90 table 59. interrupt clear-pending register 1 register . . 91 table 60. interrupt active bit register 0 . . . . . . . . . . . . . 92 table 61. interrupt active bit register 1 . . . . . . . . . . . . . 93 table 62. interrupt priority register 0 . . . . . . . . . . . . . . . 94 table 63. interrupt priority register 1 . . . . . . . . . . . . . . . 94 table 64. interrupt priority register 2 . . . . . . . . . . . . . . . 94 table 65. interrupt priority register 3 . . . . . . . . . . . . . . . 95 table 66. interrupt priority register 4 . . . . . . . . . . . . . . . 95 table 67. interrupt priority register 5 . . . . . . . . . . . . . . . 95 table 68. interrupt priority register 6 . . . . . . . . . . . . . . . 96 table 69. interrupt priority register 7 . . . . . . . . . . . . . . . 96
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 909 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 70. interrupt priority register 8 . . . . . . . . . . . . . . .96 table 71. interrupt priority register 9 . . . . . . . . . . . . . . .97 table 72. interrupt priority register 10 . . . . . . . . . . . . . .97 table 73. software trigger interrupt register . . . . . . . . .97 table 74. pin description . . . . . . . . . . . . . . . . . . . . . . . . .98 table 75. summary of i/o pin configuration registers . . 119 table 76. i/o control registers for port 0 . . . . . . . . . . . .123 table 77. i/o control registers for port 1 . . . . . . . . . . . .124 table 78. i/o control registers for port 2 . . . . . . . . . . . .125 table 79. i/o control registers for port 3 . . . . . . . . . . . .126 table 80. i/o control registers for port 4 . . . . . . . . . . . .127 table 81. i/o control registers for port 5 . . . . . . . . . . . .128 table 82. type d iocon registers bit description . . . . .130 table 83. type d i/o control registers: func values and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . .131 table 84. type a iocon registers bit description . . . . .136 table 85. type a i/o control registers: func values and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 table 86. type u iocon registers bit description . . . . .138 table 87. type u i/o control registers: func values and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . .138 table 88. type i iocon registers bit description . . . . . .139 table 89. type i i/o control r egisters: func values and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 table 90. type w iocon registers bit description. . . . .140 table 91. type w i/o control registers: func values and pin functions . . . . . . . . . . . . . . . . . . . . . . . . . .141 table 92. gpio pin description . . . . . . . . . . . . . . . . . . .143 table 93. register overview: gpio (base address 0x2009 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 table 94. register overview: gpio interrupt (base address 0x4002 8000) . . . . . . . . . . . . . . . . . . . . . . . . .145 table 95. gpio port direction register (dir[0:5] - addresses 0x2009 8000 (dir0) to 0x200980a0 (dir5)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .146 table 96. fast gpio port mask register (mask[0:5] - addresses 0x2009 8010 (mask0) to 0x2009 80b0 (mask5)) bit description. . . . . .146 table 97. fast gpio port pin value register (pin[0:5] - addresses 0x2009 8014 (pin0) to 0x2009 80b4 (pin5)) bit description . . . . . . . . . . . . . . . . . . .147 table 98. fast gpio port output set register (set[0:5] - addresses 0x2009 8018 (set0) to 0x2009 80b8 (set5)) bit description . . . . . . . . . . . . . . . . . .147 table 99. fast gpio port output clear register (clr[0:5] - addresses 0x2009 801c (clr0) to 0x2009 80bc (clr5)) bit description . . . . . . . . . . . . . . . . . .148 table 100. gpio overall interrupt status register (status - address 0x4002 8080) bit description. . . . . . .149 table 101. gpio interrupt status for port 0 rising edge interrupt (statr0 - 0x4002 8084) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .150 table 102. gpio interrupt status for port 0 falling edge interrupt (statf0 - 0x4002 8088) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .151 table 103. gpio interrupt clear register for port 0 (clr0 - 0x4002 808c) bit description . . . . . . . . . . . . .152 table 104. gpio interrupt enable for port 0 rising edge (enr0 - 0x4002 8090) bit description . . . . . . 153 table 105. gpio interrupt enable for port 0 falling edge (enf0 - address 0x4002 8094) bit description154 table 106. gpio interrupt status for port 2 rising edge interrupt (statr2 - 0x4002 80a4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 107. gpio interrupt status for port 2 falling edge interrupt (statf2 - 0x4002 80a8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 108. gpio interrupt clear register for port 0 (clr2 - 0x4002 80ac) bit description. . . . . . . . . . . . . 157 table 109. gpio interrupt enable for port 2 rising edge (enr2 - 0x4002 80b0) bit description . . . . . 158 table 110. gpio interrupt enable for port 2 falling edge (enf2 - 0x4002 80b4) bit description . . . . . . 159 table 111. emc configuration . . . . . . . . . . . . . . . . . . . . . 161 table 112. memory bank selection . . . . . . . . . . . . . . . . . 169 table 113. pad interface and control signal descriptions 173 table 114. register overview: emc (base address 0x2009 0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 115. emc control register (control - address 0x2009 c000) bit description . . . . . . . . . . . . . 176 table 116. emc status register (status - address 0x2009 c008) bit description . . . . . . . . . . . . . 177 table 117. emc configuration register (config - address 0x2009 c008) bit description . . . . . . . . . . . . . 177 table 118. dynamic control register (dynamiccontrol - address 0x2009 c020) bit description . . . . . . 178 table 119. dynamic memory refresh timer register (dynamicrefresh - address 0x2009 c024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 120. dynamic memory read configuration register (dynamicreadconfig - address 0x2009 c028) bit description . . . . . . . . . . . . . 180 table 121. dynamic memory precharge command period register (dynamicrp - address 0x2009 c030) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 180 table 122. dynamic memory active to precharge command period register (dynamicras - address 0x2009 c034) bit description . . . . . . . . . . . . . 181 table 123. dynamic memory self refresh exit time register (dynamicsrex - address 0x2009 c038) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 124. dynamic memory last data out to active time register (dynamicapr - address 0x2009 c03c) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 182 table 125. dynamic memory data in to active command time register (dynamicdal - address 0x2009 c040) bit description . . . . . . . . . . . . . 182 table 126. dynamic memory write recovery time register (dynamicwr - address 0x2009 c044) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 127. dynamic memory active to active command period register (dynamicrc - address 0x2009 c048) bit description . . . . . . . . . . . . . 183 t ab le 12 8. dynamic memory auto refresh period register (dynamicrfc - address 0x2009 c04c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 910 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 129. dynamic memory exit self refresh register (dynamicxsr - address 0x2009 c050) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .184 table 130. dynamic memory active bank a to active bank b time register (dynamicrrd - address 0x2009 c054) bit description . . . . . . . . . . . . .185 table 131. dynamic memory load mode register to active command time (dynamicmrd - address 0x2009 c058) bit description . . . . . . . . . . . . .185 table 132. static memory extended wait register (staticextendedwait - address 0x2009 c080) bit description . . . . . . . . . . . . .186 table 133. dynamic memory configuration registers (dynamicconfig[0:3], address 0x2009 c100 (dynamicconfig0), 0x2009 c120 (dynamicconfig1), 0x2009 c140 (dynamicconfig2), 0x2009 c160 (dynamicconfig3)) bit description . . . . . .187 table 134. address mapping . . . . . . . . . . . . . . . . . . . . . .188 table 135. dynamic memory rascas delay registers (dynamicrascas[0:3], address 0x2009 c104 (dynamicrascas0), 0x2009 c124 (dynamicrascas1), 0x2009 c144 (dynamicrascas2), 0x2009 c164 (dynamicrascas3)) bit description . . . . . .190 table 136. static memory configuration registers (staticconfig[0:3], address 0x2009 c200 (staticconfig0), 0x2009 c220 (staticconfig1), 0x2009 c240 (staticconfig2), 0x2009 c260 (staticconfig3)) bit description. . . . . . . . .191 table 137. static memory write enable delay registers (staticwaitwen[0:3], address 0x2009 c204 (staticwaitwen0), 0x2009 c224 (staticwaitwen1),0x2009 c244 (staticwaitwen2), 0x2009 c264 (staticwaitwen3)) bit description . . . . . . .192 table 138. static memory output enable delay registers (staticwaitoen[0:3], address 0x2009 c208 (staticwaitoen0), 0x0x2009 c228 (staticwaitoen1), 0x0x2009 c248 (staticwaitoen2), 0x0x2009 c268 (staticwaitoen3)) bit description . . . . . . .193 table 139. static memory read delay registers (staticwaitrd[0:3], address 0x2009 c20c (staticwaitrd0), 0x2009 c22c (staticwaitrd1), 0x2009 c24c (staticwaitrd2), 0x2009 c26c (staticwaitrd3)) bit description. . . . . . . . .193 table 140. static memory page mode read delay registers (staticwaitpage[0:3], address 0x2009 c210 (staticwaitpage0), 2009 c230 (staticwaitpage1), 0x2009 c250 (staticwaitpage2), 0x2009 c270 (staticwaitpage3)) bit description . . . . . .194 table 141. static memory write delay registers (staticwaitwr[0:3], address 0x2009 c214 (staticwaitwr0), 0x2009 c234 (staticwaitwr1), 0x2009 c254 (staticwaitwr2), 0x2009 c274 (staticwaitwr3)) bit description . . . . . . . . 194 table 142. static memory turn-around delay registers (staticwaitturn[0:3], address 0x2009 c218 (staticwaitturn0),0x2009 c238 (staticwaitturn1), 0x2009 c258 (staticwaitturn2), 0x2009 c278 (staticwaitturn3)) bit description . . . . . . 195 table 143. ethernet acronyms, abbreviations, and definitions 200 table 144. example phy devices . . . . . . . . . . . . . . . . . 206 table 145. ethernet mii pin descriptions. . . . . . . . . . . . . 207 table 146. ethernet rmii pin descriptions . . . . . . . . . . . 207 table 147. ethernet miim pin descriptions . . . . . . . . . . . 207 table 148. register overview: ethernet (base address 0x2008 4000) . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 149. mac configuration register 1 (mac1 - address 0x2008 4000) bit description . . . . . . . . . . . . . 210 table 150. mac configuration register 2 (mac2 - address 0x2008 4004) bit description . . . . . . . . . . . . . 211 table 151. pad operation. . . . . . . . . . . . . . . . . . . . . . . . 212 table 152. back-to-back inter-packet-gap register (ipgt - address 0x2008 4008) bit description . . . . . . 212 table 153. non back-to-back inter-packet-gap register (ipgr - address 0x2008 400c) bit description . . 212 table 154. collision window / retry register (clrt - address 0x2008 4010) bit description . . . . . . . . . . . . . 213 table 155. maximum frame register (maxf - address 0x2008 4014) bit description . . . . . . . . . . . . . 213 table 156. phy support register (supp - address 0x2008 4018) bit description . . . . . . . . . . . . . 213 table 157. test register (test - address 0x2008 401c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 158. mii mgmt configuration register (mcfg - address 0x2008 4020) bit description . . . . . . . . . . . . . 214 table 159. clock select encoding . . . . . . . . . . . . . . . . . 215 table 160. mii mgmt command register (mcmd - address 0x2008 4024) bit description . . . . . . . . . . . . . 215 table 161. mii mgmt address register (madr - address 0x2008 4028) bit description . . . . . . . . . . . . . 215 table 162. mii mgmt write data register (mwtd - address 0x2008 402c) bit description . . . . . . . . . . . . . 216 table 163. mii mgmt read data register (mrdd - address 0x2008 4030) bit description . . . . . . . . . . . . . 216 table 164. mii mgmt indicators register (mind - address 0x2008 4034) bit description . . . . . . . . . . . . . 216 table 165. station address register (sa0 - address 0x2008 4040) bit description . . . . . . . . . . . . . 217 table 166. station address register (sa1 - address 0x2008 4044) bit description . . . . . . . . . . . . . 217 table 167. station address register (sa2 - address 0x2008 4048) bit description . . . . . . . . . . . . . 217 table 168. command register (command - address 0x2008 4100) bit description . . . . . . . . . . . . . 218 table 169. status register (status - address 0x2008 4104) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 218
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 911 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 170. receive descriptor base address register (rxdescriptor - address 0x2008 4108) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .219 table 171. receive status base address register (rxstatus - address 0x2008 410c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .219 table 172. receive number of descriptors register (rxdescriptornumber - address 0x2008 4110) bit description. . . . . . . . . . . . . .219 table 173. receive produce index register (rxproduceindex - address 0x2008 4114) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .219 table 174. receive consume index register (rxconsumeindex - address 0x2008 4118) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .220 table 175. transmit descriptor base address register (txdescriptor - address 0x2008 411c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .220 table 176. transmit status base address register (txstatus - address 0x2008 4120) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .220 table 177. transmit number of descriptors register (txdescriptornumber - address 0x2008 4124) bit description . . . . . . . . . . . . .220 table 178. transmit produce index register (txproduceindex - address 0x2008 4128) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .221 table 179. transmit consume index register (txconsumeindex - address 0x2008 412c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .221 table 180. transmit status vector 0 register (tsv0 - address 0x2008 4158) bit description. . . . . . .222 table 181. transmit status vector 1 register (tsv1 - address 0x2008 415c) bit description . . . . . . . . . . . . .223 table 182. receive status vector register (rsv - address 0x2008 4160) bit description . . . . . . . . . . . . .224 table 183. flow control counter register (flowcontrolcounter - address 0x2008 4170) bit description . . . . . . . . . . . . .225 table 184. flow control status register (flowcontrolstatus - address 0x2008 4174) bit description . . . . . . . . . . . . .225 table 185. receive filter control register (rxfilterctrl - address 0x2008 4200) bit description. . . . . . .226 table 186. receive filter wol status register (rxfilterwolstatus - address 0x2008 4204) bit description . . . . . . . . . . . . . . . . . . . . . . . . .226 table 187. receive filter wol clear register (rxfilterwolclear - address 0x2008 4208) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .227 table 188. hash filter table lsbs register (hashfilterl - address 0x2008 4210) bit description. . . . . . .227 table 189. hash filter msbs register (hashfilterh - address 0x2008 4214) bit description. . . . . . .227 table 190. interrupt status register (intstatus - address 0x2008 4fe0) bit description . . . . . . . . . . . . .228 table 191. interrupt enable register (intenable - address 0x2008 4fe4) bit description . . . . . . . . . . . . .229 table 192. interrupt clear register (intclear - address 0x2008 4fe8) bit description . . . . . . . . . . . . . 229 table 193. interrupt set register (intset - address 0x2008 4fec) bit description. . . . . . . . . . . . . 230 table 194. power-down register (powerdown - address 0x2008 4ff4) bit description . . . . . . . . . . . . . 230 table 195. receive descriptor fields . . . . . . . . . . . . . . . 232 table 196. receive descriptor control word . . . . . . . . . 232 table 197. receive status fields . . . . . . . . . . . . . . . . . . 232 table 198. receive status hashcrc word . . . . . . . . . . 233 table 199. receive status information word . . . . . . . . . . 233 table 200. transmit descriptor fields . . . . . . . . . . . . . . . 235 table 201. transmit descriptor control word . . . . . . . . . . 235 table 202. transmit status fields . . . . . . . . . . . . . . . . . . 235 table 203. transmit status information word . . . . . . . . . 236 table 204. lcd controller pins . . . . . . . . . . . . . . . . . . . . 278 table 205. pins used for single panel stn displays . . . . 278 table 206. pins used for dual panel stn displays . . . . . 279 table 207. pins used for tft displays . . . . . . . . . . . . . . 279 table 208. fifo bits for little-endian byte, little-endian pixel order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 209. fifo bits for big-endian byte, big-endian pixel order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 210. fifo bits for little-endian byte, big-endian pixel order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 211. rgb mode data formats . . . . . . . . . . . . . . . . 286 table 212. palette data storage for tft modes. . . . . . . 287 table 213. palette data storage for stn color modes. . . 287 table 214. palette data storage for stn monochrome mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 215. palette data storage for stn monochrome mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 216. addresses for 32 x 32 cursors . . . . . . . . . . . 291 table 217. buffer to pixel mapping for 32 x 32 pixel cursor format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 218. buffer to pixel mapping for 64 x 64 pixel cursor format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 table 219. pixel encoding. . . . . . . . . . . . . . . . . . . . . . . . 293 table 220. color display driven with 2 2/3 pixel data . . . 293 table 221. register overview: lcd controller (base address 0x2008 8000) . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 222. horizontal timing register (timh, address 0x2008 8000) bit description . . . . . . . . . . . . . 298 table 223. vertical timing register (timv, address 0x2008 8004) bit description. . . . . . . . . . . . . . . . . . . . 299 table 224. clock and signal polarity register (pol, address 0x2008 8008) bit description . . . . . . . . . . . . . 300 table 225. line end control register (le, address 0x2008 800c) bit description . . . . . . . . . . . . . . . . . . . 301 table 226. upper panel frame base register (upbase, address 0x2008 8010) bit description . . . . . 302 table 227. lower panel frame base register (lpbase, address 0x2008 8014) bit description . . . . . 302 t ab le 22 8. lcd control register (ctrl, address 0x2008 8018) bit description. . . . . . . . . . . . . . . . . . . . 303 table 229. interrupt mask register (intmsk, address 0x2008 801c) bit description . . . . . . . . . . . . . 305 table 230. raw interrupt status register (intraw, address
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 912 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 0x2008 8020) bit description . . . . . . . . . . . . .306 table 231. masked interrupt status register (intstat, address 0x2008 8024) bit description. . . . . .306 table 232. interrupt clear register (intclr, address 0x2008 8028) bit description . . . . . . . . . . . . .307 table 233. upper panel current address register (upcurr, address 0x2008 802c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .307 table 234. lower panel current address register (lpcurr, address 0x2008 8030) bit description. . . . . .307 table 235. color palette registers (pal[0:127], address 0x2008 8200 (pal0) to 0x2008 83fc (pal127)) bit description . . . . . . . . . . . . . . . . . . . . . . . . .308 table 236. cursor image registers (crsr_img[0:255], address 0x2008 8800 (crsr_img0) to 0x2008 8bfc (crsr_img255)) bit description . . . . .308 table 237. cursor control register (crsr_ctrl, address 0x2008 8c00) bit description . . . . . . . . . . . . .309 table 238. cursor configuration register (crsr_cfg, address 0x2008 8c04) bit description . . . . .309 table 239. cursor palette register 0 (crsr_pal0, address 0x2008 8c08) bit description . . . . . . . . . . . . .310 table 240. cursor palette register 1 (crsr_pal1, address 0x2008 8c0c) bit description . . . . . . . . . . . . .310 table 241. cursor xy position register (crsr_xy, address 0x2008 8c10) bit description . . . . . . . . . . . . . 311 table 242. cursor clip position register (crsr_clip, address 0x2008 8c14) bit description . . . . . 311 table 243. cursor interrupt mask register (crsr_intmsk, rw - 0x2008 8c20) . . . . . . . . . . . . . . . . . . . .312 table 244. cursor interrupt clear register (crsr_intclr, address 0x2008 8c24) bit description . . . . .312 table 245. cursor raw interrupt status register (crsr_intraw, address 0x2008 8c28) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .312 table 246. cursor masked interrupt status register (crsr_intstat, address 0x2008 8c2c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .313 table 247. lcd panel connections for stn single panel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 table 248. lcd panel connections for stn dual panel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 table 249. lcd panel connections for tft panels . . . . .319 table 250. usb related acronyms, abbreviations, and definitions used in this chapter . . . . . . . . . . . .321 table 251. fixed endpoint configuration . . . . . . . . . . . . .322 table 252. usb external interface . . . . . . . . . . . . . . . . . .325 table 253. usb device controller clock sources . . . . . . .326 table 254. register overview: usb device controller (base address 0x2008 c000) . . . . . . . . . . . . . . . . . .328 table 255. usb port select register (portsel - address 0x2008 c110) bit description . . . . . . . . . . . . .330 table 256. usb device interrupt status register (devintst - address 0x2008 c200) bit description . . . . .330 table 257. usb device interrupt enable register (devinten - address 0x2008 c204) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .331 table 258. usb device interrupt clear register (devintclr - address 0x2008 c208) bit description . . . . . 332 table 259. usb device interrupt set register (devintset - address 0x2008 c20c) bit description. . . . . . 333 table 260. usb device interrupt priority register (devintpri - address 0x2008 c22c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 table 261. usb endpoint registers bit allocation . . . . . . 335 table 262. usb endpoint interrupt status register (epintst - address 0x2008 c230) bit description . . . . . 335 table 263. usb endpoint interrupt enable register (epinten - address 0x2008 c234) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 264. usb endpoint interrupt clear register (epintclr - address 0x2008 c238) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 265. usb endpoint interrupt set register (epintset - address 0x2008 c23c) bit description. . . . . . 337 table 266. usb endpoint interrupt priority register (epintpri - address 0x2008 c240) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 267. usb realize endpoint register (reep - address 0x2008 c244) bit description . . . . . . . . . . . . . 339 table 268. usb endpoint index register (epin - address 0x2008 c248) bit description . . . . . . . . . . . . . 340 table 269. usb maxpacketsize register (maxpsize - address 0x2008 c24c) bit description. . . . . . 340 table 270. usb receive data register (rxdata - address 0x2008 c218) bit description . . . . . . . . . . . . . 341 table 271. usb receive packet length register (rxplen - address 0x2008 c220) bit description . . . . . . 341 table 272. usb transmit data register (txdata - address 0x2008 c21c) bit description. . . . . . . . . . . . . 342 table 273. usb transmit packet length register (txplen - address 0x2008 c224) bit description . . . . . . 342 table 274. usb control register (ctrl - address 0x2008 c228) bit description . . . . . . . . . . . . . 343 table 275. usb command code register (cmdcode - address 0x2008 c210) bit description . . . . . . 344 table 276. usb command data register (cmddata - address 0x2008 c214) bit description . . . . . . 344 table 277. usb dma request status register (dmarst - address 0x2008 c250) bit description . . . . . . 345 table 278. usb dma request clear register (dmarclr - address 0x2008 c254) bit description . . . . . . 346 table 279. usb dma request set register (dmarset - address 0x2008 c258) bit description . . . . . . 346 table 280. usb udca head register (udcah - address 0x2008 c280) bit description . . . . . . . . . . . . . 347 table 281. usb ep dma status register (epdmast - address 0x2008 c284) bit description . . . . . . 347 t able 28 2. usb ep dma enable register (epdmaen - address 0x2008 c288) bit description . . . . . . 347 table 283. usb ep dma disable register (epdmadis - address 0x2008 c28c) bit description. . . . . . 348 table 284. usb dma interrupt status register (dmaintst - address 0x2008 c290) bit description . . . . . . 348 table 285. usb dma interrupt enable register (dmainten - address 0x2008 c294) bit description . . . . . 349
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 913 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 286. usb end of transfer interrupt status register (eotintst - address 0x2008 c2a0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .349 table 287. usb end of transfer interrupt clear register (eotintclr - address 0x2008 c2a4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .349 table 288. usb end of transfer interrupt set register (eotintset - address 0x2008 c2a8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .350 table 289. usb new dd request interrupt status register (nddrintst - address 0x2008 c2ac) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .350 table 290. usb new dd request interrupt clear register (nddrintclr - address 0x2008 c2b0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .350 table 291. usb new dd request interrupt set register (nddrintset - address 0x2008 c2b4) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .350 table 292. usb system error interrupt status register (syserrintst - address 0x2008 c2b8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .351 table 293. usb system error interrupt clear register (syserrintclr - addre ss 0x2008 c2bc) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .351 table 294. usb system error interrupt set register (syserrintset - address 0x2008 c2c0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .351 table 295. clkctrl register (clkctrl - address 0x2008 cff4) bit description . . . . . . . . . . . . .352 table 296. usb clock status register (clkst - address 0x2008 cff8) bit description . . . . . . . . . . . . .352 table 297. sie command code table. . . . . . . . . . . . . . . .357 table 298. set address command bit description . . . . . .357 table 299. configure device command bit description . .358 table 300. set mode command bit description . . . . . . . .358 table 301. set device status command bit description. .360 table 302. get error code command bit description. . . .361 table 303. read error status command bit description .362 table 304. select endpoint command bit description . . .363 table 305. set endpoint status command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .364 table 306. clear buffer command bit description . . . . . .365 table 307. dma descriptor . . . . . . . . . . . . . . . . . . . . . . .372 table 308. usb (ohci) related acronyms and abbreviations used in this chapter . . . . . . . . . . . . . . . . . . . .386 table 309. usb otg port pins . . . . . . . . . . . . . . . . . . . .388 table 310. usb host register address definitions . . . . .389 table 311. usb otg port 1 pins . . . . . . . . . . . . . . . . . . .393 table 312. register overview: usb otg controller (base address 0x2008 c000) . . . . . . . . . . . . . . . . . .398 table 313. otg interrupt status register (intst - address 0x2008 c100) bit description . . . . . . . . . . . . .398 table 314. otg interrupt enable register (inten - address 0x2008 c104) bit description . . . . . . . . . . . . .399 table 315. otg interrupt enable register (intset - address 0x2008 c108) bit description . . . . . . . . . . . . .399 table 316. otg interrupt enable register (intclr - address 0x2008 c10c) bit description . . . . . . . . . . . . .400 table 317. otg status control register (stctrl - address 0x2008 c110) bit description . . . . . . . . . . . . . 401 table 318. otg timer re gister (tmr - address 0x2008 c114) bit description . . . . . . . . . . . . . 402 table 319. i2c receive register (i2c_rx - address 0x2008 c300) bit description . . . . . . . . . . . . . 402 table 320. i2c transmit register (i2c_tx - address 0x2008 c300) bit description . . . . . . . . . . . . . 403 table 321. i2c status register (i2c_sts - address 0x2008 c304) bit description . . . . . . . . . . . . . 403 table 322. i2c control register (i2c_ctl - address 0x2008 c308) bit description . . . . . . . . . . . . . 405 table 323. i2c_clkhi register (i2c_clkhi - address 0x2008 c30c) bit description. . . . . . . . . . . . . 406 table 324. i2c_clklo register (i2c_clklo - address 0x2008 c310) bit description . . . . . . . . . . . . . 406 table 325. otg clock control register (clkctrl - address 0x2008 cff4) bit description. . . . . . . . . . . . . 407 table 326. otg clock status register (clkst - address 0x2008 cff8) bit description. . . . . . . . . . . . . 408 table 327. spifi flash memory map. . . . . . . . . . . . . . . . 424 table 328. spifi pin description. . . . . . . . . . . . . . . . . . . 424 table 329. supported qspi devices. . . . . . . . . . . . . . . . 425 table 330. spifi function allocation . . . . . . . . . . . . . . . . 426 table 331. bit values for spifi_init options parameter . . . 427 table 332. error codes for spifi_init . . . . . . . . . . . . . . . . 428 table 333. error codes for spifi_program and spifi_erase . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 table 334. bit values for spifiopers options parameter. 432 table 335. sd/mmc card interface pin description. . . . . 435 table 336. command format . . . . . . . . . . . . . . . . . . . . . 439 table 337. simple response format . . . . . . . . . . . . . . . . 439 table 338. long response format . . . . . . . . . . . . . . . . . . 440 table 339. command path status flags. . . . . . . . . . . . . . 440 table 340. crc token status . . . . . . . . . . . . . . . . . . . . . 443 table 341. data path status flags . . . . . . . . . . . . . . . . . . 444 table 342. transmit fifo status flags . . . . . . . . . . . . . . 445 table 343. receive fifo status flags . . . . . . . . . . . . . . . 445 table 344. register overview: sd card interface (base address 0x400c 0000). . . . . . . . . . . . . . . . . . 447 table 345: power control register (pwr - address 0x400c 0000) bit description . . . . . . . . . . . . . 447 table 346: mci clock control register (clock - address 0x400c 0004) bit description . . . . . . . . . . . . . 448 table 347: mci argument register (argument - address 0x400c 0008) bit description . . . . . . . . . . . . . 448 table 348: mci command register (command - address 0x400c 000c) bit description. . . . . . . . . . . . . 449 table 349: command response types . . . . . . . . . . . . . 449 table 350: mci command resp onse register (respcmd - address 0x400c 0010) bit description . . . . . . 449 table 351: mci response registers (response[0:3] - addresses 0x40 0c 0014, 0x400c 0018, 0x400c 001c and 0x400c 0020) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 table 352: response register type. . . . . . . . . . . . . . . . 450 table 353: mci data timer register (datatimer - address 0x400c 0024) bit description . . . . . . . . . . . . . 450
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 914 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 354: mci data length register (datalength - address 0x400c 0028) bit description . . . . . .450 table 355: data control register (datactrl - address 0x400c 002c) bit description . . . . . . . . . . . . .451 table 356: data block length . . . . . . . . . . . . . . . . . . . . .451 table 357: mci data counter register (datacnt - address 0x400c 0030) bit description . . . . . . . . . . . . .452 table 358: mci status register (status - address 0x400c 0034) bit description . . . . . . . . . . . . .452 table 359: mci clear register (clear - address 0x400c 0038) bit description . . . . . . . . . . . . .453 table 360: mci interrupt mask registers (mask0 - address 0x400c 003c) bit description . . . . . . . . . . . . .454 table 361: mci fifo counter register (fifocnt - address 0x400c 0048) bit description . . . . . . . . . . . . .454 table 362: mci data fifo register (fifo - address 0x400c 0080 to 0x400c 00bc) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .455 table 363: uart1 pin description . . . . . . . . . . . . . . . . .459 table 364: register overview: uart1 (base address 0x4001 0000) . . . . . . . . . . . . . . . . . .460 table 365: uart1 receiver buffer register when dlab = 0 (rbr - address 0x4001 0000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .461 table 366: uart1 transmitter holding register when dlab = 0 (thr - address 0x4001 0000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .461 table 367: uart1 divisor latch lsb register when dlab = 1 (dll - address 0x4001 0000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .462 table 368: uart1 divisor latch msb register when dlab = 1 (dlm - address 0x4001 0004 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .462 table 369: uart1 interrupt enable register when dlab = 0 (ier - address 0x4001 0004 ) bit description .463 table 370: uart1 interrupt identification register (iir - address 0x4001 0008) bit description. . . . . . .464 table 371: uart1 interrupt handling . . . . . . . . . . . . . . .465 table 372: uart1 fifo control register (fcr - address 0x4001 0008) bit description . . . . . . . . . . . . .467 table 373: uart1 line control register (lcr - address 0x4001 000c) bit description . . . . . . . . . . . . .469 table 374: uart1 modem control register (mcr - address 0x4001 0010) bit description . . . . . . . . . . . . .470 table 375: modem status interrupt generation . . . . . . . .471 table 376: uart1 line status register (lsr - address 0x4001 0014) bit description . . . . . . . . . . . . .473 table 377: uart1 modem status register (msr - address 0x4001 0018) bit description . . . . . . . . . . . . .474 table 378: uart1 scratch pad register (scr - address 0x4001 0014) bit description . . . . . . . . . . . . .476 table 379: auto-baud control register (acr - address 0x4001 0020) bit description . . . . . . . . . . . . .476 table 380: uart1 fractional divider register (fdr - address 0x4001 0028) bit description. . . . . . .480 table 381. fractional divider setting look-up table . . . . .482 table 382: uart1 transmit enable register (ter - address 0x4001 0030) bit description . . . . . . . . . . . . .483 table 383: uart1 rs485 control register (rs485ctrl - address 0x4001 004c) bit description . . . . . . 484 table 384. uart1 rs-485 address match register (rs485adrmatch - address 0x4001 0050) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 table 385. uart1 rs-485 delay value register (rs485dly - address 0x4001 0054) bit description . . . . . 485 table 386: uartn pin description . . . . . . . . . . . . . . . . . 489 table 387. register overview: uart0/2/3 (base address: 0x4000 c000, 0x4008 8000, 0x4009 c000) . 490 table 388: uartn receiver buffer register when dlab = 0, read only (rbr - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 04009 c000 (uart3) ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 table 389: uartn transmit holding register when dlab = 0, write only (thr - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 0x4009 c000 (uart3)) bit description. . . . . . . . . . . . . . . . . 491 table 390: uartn divisor latch lsb register when dlab = 1 (dll - address 0x4000 c000 (uart0), 0x4009 8000 (uart2), 0x4009 c000 (uart3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 492 table 391: uartn divisor latch msb register when dlab = 1 (dlm - address 0x4000 c004 (uart0), 0x4009 8004 (uart2), 0x4009 c004 (uart3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 492 table 392: uartn interrupt enable register when dlab = 0 (ier - address 0x4000 c004 (uart0), 0x4009 8004 (uart2), 0x4009 c004 (uart3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 493 table 393: uartn interrupt identification register, read only (iir - address 0x4000 c008 (uart0), 0x4009 8008 (uart2), 0x4009 c008 (uart3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 494 table 394: uartn interrupt handling . . . . . . . . . . . . . . . 495 table 395: uartn fifo control register, write only (fcr - address 0x4000 c008 (uart0), 0x4009 8008 (uart2), 0x4007 c008 (uart3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 table 396: uartn line control register (lcr - address 0x4000 c00c (uart0), 0x4009 800c (uart2), 0x4009 c00c (uart3)) bit description . . . . . 497 table 397: uartn line status register (lsr - address 0x4000 c014 (uart0), 0x4009 8014 (uart2), 0x4009 c014 (uart3)) bit description . . . . . 498 table 398: uartn scratch pad register (scr - address 0x4000 c01c (uart0), 0x4009 801c (uart2), 0x4009 c01c (uart3)) bit description . . . . . 499 table 399: uartn auto-baud control register (acr - a ddress 0x4000 c02 0 (uart0), 0x4009 8020 (uart2), 0x4009 c020 (uart3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 table 400: uartn fractional divider register (fdr - address 0x4000 c028 (uart0), 0x4009 8028 (uart2), 0x4009 c028 (uart3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 table 401. fractional divider setting look-up table . . . . . 505 table 402: uartn transmit enable register (ter - address
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 915 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 0x4000 c030 (uart0), 0x4009 8030 (uart2), 0x4009 c030 (uart3)) bit description. . . . . .506 table 403: uartn rs485 control register (rs485ctrl - address 0x4000 c04c (uart0), 0x4009 804c (uart2), 0x4009 c04c (uart3)) bit description 507 table 404. uartn rs-485 address match register (rs485adrmatch - address 0x4000 c050 (uart0), rs485adrmatch - 0x4009 8050 (uart2), rs485adrmatch - 0x4009 c050 (uart3)) bit description . . . . . . . . . . . . . . . . .507 table 405. uartn rs-485 delay value register (rs485dly - address 0x4000 0054 (uart0), rs485dly - 0x4009 8054 (uart2), rs485dly - 0x4009 c054 (uart3)) bit description. . . . . .508 table 406: uart4 pin description. . . . . . . . . . . . . . . . . .512 table 407. register overview: uart4 (base address: 0x400a 4000) . . . . . . . . . . . . . . . . . . . . . . . . .513 table 408: uart4 receiver buffer register when dlab = 0 (rbr - address 0x400a 4000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .514 table 409: uart4 transmit holding register when dlab = 0 (thr -address 0x400a 4000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .514 table 410: uart4 divisor latch lsb register when dlab = 1 (dll - address 0x400a 4000 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .515 table 411: uart4 divisor latch msb register when dlab = 1 (dlm - address 0x400a 4004 ) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .515 table 412: uart4 interrupt enable register when dlab = 0 (ier - address 0x400a 4004 ) bit description .516 table 413: uart4 interrupt identification register (iir - address 0x400a 4008) bit description . . . . . .517 table 414: uart4 interrupt handling . . . . . . . . . . . . . . .518 table 415: uart4 fifo control register (fcr - address 0x400a 4008) bit description . . . . . . . . . . . . .520 table 416: uart4 line control register (lcr - address 0x400a 400c) bit description . . . . . . . . . . . . .521 table 417: uart4 line status register (lsr - address 0x400a 4014) bit description . . . . . . . . . . . . .522 table 418: uart4 scratch pad register (scr - address 0x400a 401c) bit description . . . . . . . . . . . . .523 table 419: uart4 auto-baud control register (acr - 0x400a 4020) bit description . . . . . . . . . . . . .524 table 420: uart4 irda control register (icr - address 0x400a 4024) bit description . . . . . . . . . . . . .527 table 421: irda pulse width . . . . . . . . . . . . . . . . . . . . . .527 table 422: uart4 fractional divider register (fdr - address 0x400a 4028) bit description . . . . . .528 table 423. fractional divider setting look-up table . . . . .530 table 424. uart4 oversampling register (osr - address 0x400a 402c) bit description . . . . . . . . . . . . .531 table 425. uart4 smart card interface control register (scictrl - address 0x400a 4048) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .532 table 426: uart4 rs485 control register (rs485ctrl - address 0x400a 404c) bit description . . . . . .533 table 427. uart4 rs-485 address match register (rs485adrmatch - address 0x400a 4050) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 table 428. uart4 rs-485 delay value register (rs485dly - address 0x400a 4054) bit description . . . . . 534 table 429. uart4 synchronous mode control register (syncctrl - address 0x400a 4058) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 table 430. can pin descriptions . . . . . . . . . . . . . . . . . . 539 table 431. memory map of the can block . . . . . . . . . . . 544 table 432. register overview: can acceptance filter (base address 0x4003 c000). . . . . . . . . . . . . . . . . . 544 table 433. register overview: central can (base address 0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 544 table 434. register overview: can (base address 0x4004 4000 (can1) and 0x4004 8000 (can2)) . . . . 544 table 435. can1 and can2 controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 table 436. register overview: can wake and sleep (base address 0x400f c000) . . . . . . . . . . . . . . . . . 546 table 437. can mode register (can1mod - address 0x4004 4000, can2mod - address 0x4004 8000) bit description . . . . . . . . . . . . . 547 table 438. can command register (can1cmr - address 0x4004 4004, can2cmr - address 0x4004 8004) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 549 table 439. can global status register (can1gsr - address 0x4004 4008, can2gsr - address 0x4004 8008) bit description . . . . . . . . . . . . . 550 table 440. can interrupt and capture register (can1icr - address 0x4004 400c, can2icr - address 0x4004 800c) bit description . . . . . . . . . . . . 553 table 441. can interrupt enable register (can1ier - address 0x4004 4010, can2ier - address 0x4004 8010) bit description . . . . . . . . . . . . . 556 table 442. can bus timing register (can1btr - address 0x4004 4014, can2btr - address 0x4004 8014) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 557 table 443. can error warning limit register (can1ewl - address 0x4004 4018, can2ewl - address 0x4004 8018) bit description . . . . . . . . . . . . . 558 table 444. can status register (can1sr - address 0x4004 401c, can2sr - address 0x4004 801c) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 559 table 445. can receive frame status register (can1rfs - address 0x4004 4020, can2rfs - address 0x4004 8020) bit description . . . . . . . . . . . . . 560 table 446. can receive identifier register (can1rid - address 0x4004 4024, can2rid - address 0x4004 8024) bit description . . . . . . . . . . . . . 561 table 447. rx identifier register when ff = 1 . . . . . . . . 561 table 448. can receive data register a (can1rda - address 0x4004 4028, can2rda - address 0x4004 8028) bit description . . . . . . . . . . . . . 562 table 449. can receive data register b (can1rdb - address 0x4004 402c, can2rdb - address 0x4004 802c) bit description . . . . . . . . . . . . . 562 table 450. can transmit frame information register
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 916 of 942 nxp semiconductors UM10562 chapter 41: supplementary information (can1tfi[1/2/3] - address 0x4004 40[30/40/50], can2tfi[1/2/3] - 0x4004 80[30/40/50]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .563 table 451. can transfer identifier register (can1tid[1/2/3] - address 0x4004 40[34/44/54], can2tid[1/2/3] - address 0x4004 80[34/44/54]) bit description.564 table 452. transfer identifier register when ff = 1. . . . .564 table 453. can transmit data register a (can1tda[1/2/3] - address 0x4004 40[38/48/58], can2tda[1/2/3] - address 0x4004 80[38/48/58]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .564 table 454. can transmit data register b (can1tdb[1/2/3] - address 0x4004 40[3c/4c/5c], can2tdb[1/2/3] - address 0x4004 80[3c/4c/5c]) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .565 table 455. central transit status register (txsr - address 0x4004 0000) bit description . . . . . . . . . . . . .566 table 456. central receive status register (rxsr - address 0x4004 0004) bit description . . . . . . . . . . . . .567 table 457. central miscellaneous status register (msr - address 0x4004 0008) bit description. . . . . . .567 table 458. acceptance filter modes and access control .568 table 459. section configuration register settings . . . . . .569 table 460. acceptance filter mode register (afmr - address 0x4003 c000) bit description . . . . . .571 table 461. standard frame individual start address register (sff_sa - address 0x4003 c004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .572 table 462. standard frame group start address register (sff_grp_sa - address 0x4003 c008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .573 table 463. extended frame start address register (eff_sa - address 0x4003 c00c) bit description . . . . .573 table 464. extended frame group start address register (eff_grp_sa - address 0x4003 c010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .573 table 465. end of af tables register (endoftable - address 0x4003 c014) bit description . . . . . .574 table 466. lut error address register (luterrad - address 0x4003 c018) bit description . . . . . .574 table 467. lut error register (luterr - address 0x4003 c01c) bit description . . . . . . . . . . . . .574 table 468. global fullcan enable register (fcanie - address 0x4003 c020) bit description . . . . . .575 table 469. fullcan interrupt and capture register 0 (fcanic0 - address 0x4003 c024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .575 table 470. fullcan interrupt and capture register 1 (fcanic1 - address 0x4003 c028) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .575 table 471. format of automatically stored rx messages 578 table 472. fullcan semaphore operation. . . . . . . . . . . .578 table 473. example of acceptance filter tables and id index values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .589 table 474. used id-look-up table sections . . . . . . . . . .591 table 475. used id-look-up table sections . . . . . . . . . .592 table 476. ssp pin descriptions . . . . . . . . . . . . . . . . . . .597 table 477. register overview: ssp (base address 0x4008 8000 (ssp0), 0x4003 0000 (ssp1), 0x400a c000 (ssp2)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 table 478: sspn control re gister 0 (cr0 - address 0x4008 8000 (ssp0), 0x4003 0000 (ssp1) , 0x400a c000 (ssp2)) bit description . . . . . . 606 table 479: sspn control re gister 1 (cr1 - address 0x4008 8004 (ssp0), 0x4003 0004 (ssp1), 0x400a c004 (ssp2)) bit description . . . . . . 607 table 480: sspn data register (dr - address 0x4008 8008 (ssp0), 0x4003 0008 (ssp1), 0x400a c008 (ssp2)) bit description . . . . . . . . . . . . . . . . . . 607 table 481: sspn status register (sr - address 0x4008 800c (ssp0), 0x4003 000c (ssp1), 0x400a c00c (ssp2)) bit description . . . . . . 608 table 482: sspn clock presca le register (cpsr - address 0x4008 8010 (ssp0), 0x4003 0010 (ssp1), 0x400a c010 (ssp2)) bit description . . . . . . 608 table 483: sspn interrupt mask set/clear register (imsc - address 0x4008 8014 (ssp0), 0x4003 0014 (ssp1), 0x400a c014 (ssp2)) bit description609 table 484: sspn raw interrupt status register (ris - address 0x4008 8018 (ssp0), 0x4003 0018 (ssp1), 0x400a c018 (ssp2)) bit description609 table 485: sspn masked interrup t status register (mis - address 0x4008 801c (ssp0), 0x4003 001c (ssp1), 0x400a c01c (ssp2)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 table 486: sspn interrupt cl ear register (icr - address 0x4008 8020 (ssp0), 0x4003 0020 (ssp1) , 0x400a c020 (ssp2)) bit description . . . . . . 610 table 487: sspn dma control register (dmacr - address 0x4008 8024 (ssp0), 0x4003 0024 (ssp1), 0x400a c024 (ssp2)) bit description . . . . . . 610 table 488. i 2 c pin description . . . . . . . . . . . . . . . . . . . . 614 table 489. i2c0conset and i2c1conset used to configure master mode . . . . . . . . . . . . . . . . . 615 table 490. i2c0conset and i2c1conset used to configure slave mode . . . . . . . . . . . . . . . . . . 617 table 491. register overview: i2c-bus interface (base address 0x4001 c000 (i2c0), 0x4005 c000 (i2c1), 0x400a 0000 (i2c2)) . . . . . . . . . . . . . 623 table 492. i 2 c control set register (conset - addresses 0x4001 c000 (i2c0), 0x4005 c000 (i2c1) , 0x400a 0000 (i2c2)) bit description . . . . . . . 624 table 493. i 2 c control clear register (conclr - addresses 0x4001 c018 (i2c0), 0x4005 c018 (i2c1), 0x400a 0018 (i2c2)) bit description . . . . . . . 626 table 494. i 2 c status register (stat - addresses 0x4001 c004 (i2c0), 0x4005 c004 (i2c1), 0x400a 0004 (i2c2)) bit description . . . . . . . 626 table 495. i 2 c data register (dat- addresses 0x4001 c008 (i2c0), 0x4005 c008 (i2c1), 0x400a 0008 (2c2)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 627 table 496. i 2 c monitor mode control register (mmctrl - addresses 0x4001 c01c (i2c0), 0x4005 c01c (i2c1), 0x400a 001c (i2c2)) bit description . 627 table 497. i 2 c data buffer register (data_buffer - addresses 0x4001 c02c (i2c0), 0x4005 c02c
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 917 of 942 nxp semiconductors UM10562 chapter 41: supplementary information (i2c1), 0x400a 002c (i2c2)) bit description. .628 table 498. i 2 c slave address register 0 (adr0 - address 0x4001 c00c (i2c0), 0x4005 c00c (i2c1), 0x400a 000c (i2c2)) bit description. . . . . . . .629 table 499. i 2 c slave address registers (adr[1:3] - address 0x4001 c020 (adr1) to 0x4001 c028 (adr3) (i2c0), 0x4005 c020 (adr1) to 0x4005 c028 (adr3) (i2c1), 0x400a 0020 (adr1) to 0x400a 0028 (adr3) (i2c2)) bit description .629 table 500. i 2 c mask registers (mask[0:3] - address 0x4001 c030 (mask0) to 0x4001 c03c (mask3) (i2c0), 0x4005 c030 (mask0) to 0x4005 c03c (mask3) (i2c1), 0x400a 0030 (mask0) to 0x400a 003c (mask3) (i2c1 )) bit description . . . 629 table 501. i 2 c scl high duty cycle register (sclh - address 0x4001 c010 (i2c0), 0x4005 c010 (i2c1), 0x400a 0010(i2c2)) bit description . .630 table 502. i 2 c scl low duty cycle register (scll - address 0x4001 c014 (i2c0), 0x4005 c014 (i2c1), 0x400a 0014 (i2c2)) bit description . . . . . . . .630 table 503. example i 2 c clock rates. . . . . . . . . . . . . . . . .630 table 504. abbreviations used to describe an i 2 c operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .632 table 505. i2conset used to initialize master transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633 table 506. i2conset used to initialize slave receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637 table 507. master transmitter mode. . . . . . . . . . . . . . . .640 table 508. master receiver mode. . . . . . . . . . . . . . . . . .641 table 509. slave receiver mode. . . . . . . . . . . . . . . . . . .642 table 510. slave transmitter mode. . . . . . . . . . . . . . . . .644 table 511. miscellaneous states . . . . . . . . . . . . . . . . . . .645 table 512. pin descriptions . . . . . . . . . . . . . . . . . . . . . . .662 table 513. register overview: i 2 s (base address 0x400a 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664 table 514: digital audio output register (dao - address 0x400a 8000) bit description . . . . . . . . . . . . .665 table 515: digital audio input register (dai - address 0x400a 8004) bit description . . . . . . . . . . . . .665 table 516: transmit fifo register (txfifo - address 0x400a 8008) bit description . . . . . . . . . . . . .666 table 517: receive fifo register (rxfifo - address 0x400a 800c) bit description . . . . . . . . . . . . .666 table 518: status feedback register (state - address 0x400a 8010) bit description . . . . . . . . . . . . .666 table 519: dma configuration register 1 (dma1 - address 0x400a 8014) bit description . . . . . . . . . . . . .667 table 520: dma configuration register 2 (dma2 - address 0x400a 8018) bit description . . . . . . . . . . . . .667 table 521: interrupt request control register (irq - address 0x400a 801c) bit description . . . . . . . . . . . . .668 table 522: transmit clock rate register (txrate - address 0x400a 8020) bit description . . . . . . . . . . . . .668 table 523: receive clock rate register (rxrate - address 0x400a 8024) bit description . . . . . . . . . . . . .669 table 524: transmit clock bit rate register (txbitrate - address 0x400a 8028) bit description . . . . . .670 table 525: receive clock rate bit register (rxbitrate - address 0x400a 802c) bit description . . . . . . 670 table 526: transmit mode control register (txmode - 0x400a 8030) bit description . . . . . . . . . . . . . 670 table 527: receive mode control register (rxmode - 0x400a 8034) bit description . . . . . . . . . . . . . 671 table 528: i 2 s transmit modes . . . . . . . . . . . . . . . . . . . . 674 table 529: i 2 s receive modes . . . . . . . . . . . . . . . . . . . . . 677 table 530. conditions for fifo level comparison . . . . . . 681 table 531. dma and interrupt request generation . . . . . 681 table 532. status feedback in the i2sstate register . . 681 table 533. timer/counter pin description . . . . . . . . . . . . 686 table 534. register overview: timer0/1/2/3 (register base addresses 0x4000 4000 (timer0), 0x4000 8000 (timer1), 0x4009 0000 (timer2), 0x4009 4000 (timer3)) . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 table 535. interrupt register (ir - addresses 0x4000 4000 (timer0), 0x4000 8000 (timer1), 0x4009 0000 (timer2), 0x4009 4000 (timer3)) bit description 688 table 536. timer control register (tcr - addresses 0x4000 4004 (timer0), 0x4000 8004 (timer1), 0x4009 0004 (timer2), 0x4009 4004 (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 688 table 537. timer counter registers (tc - addresses 0x400 4008 (timer0), 0x4000 8008 (timer1), 0x4009 0008 (timer2), 0x4009 4008 (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 689 table 538. timer prescale registers (pr - addresses 0x4000 400c (timer0), 0x4000 800c (timer1), 0x4009 000c (timer2), 0x4009 400c (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 689 table 539. timer prescale counter registers (pc - addresses 0x4000 4010 (timer0), 0x4000 8010 (timer1), 0x4009 0010 (timer2), 0x4009 4010 (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 689 table 540. match control register (mcr - addresses 0x4000 4014 (timer0), 0x4000 8014 (timer1), 0x4009 0014 (timer2), 0x4009 4014 (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 690 table 541. timer match registers (mr[0:3], addresses 0x4000 4018 (mr0) to 0x4000 4024 (mr3) (timer0), 0x4000 8018 (mr0) to 0x4000 8024 (mr3) (timer1), 0x4009 0018 (mr0) to 0x4009 0024 (mr3) (timer2), 0x4009 4018 (mr0) to 0x4009 4024 (mr3)(timer3)) bit description 691 table 542. capture control register (ccr - addresses 0x4000 4028 (timer0), 0x4000 8020 (timer1), 0x4009 0028 (timer2), 0x4009 4028 (timer3)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 691 table 543. timer capture registers (cr[0:1], address 0x4000 402c (cr0) to 0x4000 4030 (cr1) (timer0), 0x4000 802c (cr0) to 0x4000 0030 (cr1) (timer1), 0x4009 002c (cr0) to 0x4009 0030 (cr1) (timer2), 0x4009 402c (cr0) to 0x4000 4030 (cr1) (timer3)) bit description692 table 544. timer external match registers (emr - addresses 0x4000 403c (timer0), 0x4000 803c (timer1),
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 918 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 0x4009 403c (timer2), 0x400c 403c (timer3)) bit description . . . . . . . . . . . . . . . .693 table 545. external match control . . . . . . . . . . . . . . . . .694 table 546. count control register (ctcr - addresses 0x4000 4070 (timer0), 0x4000 8070 (timer1), 0x4009 0070 (timer2), 0x4009 4070 (timer3)) bit description . . . . . . . . . . . . . . . . . . . . . . . . .695 table 547. system tick timer register map . . . . . . . . . .700 table 548. system timer control and status register (stctrl - 0xe000 e010) bit description . . . .700 table 549. system timer reload value register (streload - 0xe000 e014) bit description . . . . . . . . . . . .700 table 550. system timer current value register (stcurr - 0xe000 e018) bit description . . . . . . . . . . . . .701 table 551. system timer calibration value register (stcalib - 0xe000 e01c) bit description . . .701 table 552. set and reset inputs for pwm flip-flops . . . .707 table 553. pin summary . . . . . . . . . . . . . . . . . . . . . . . . .708 table 554. register overview: pwm (base addresses 0x4001 4000 (pwm0) and 0x4001 8000 (pwm1)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .709 table 555: pwm interrupt register (ir - address 0x4001 4000 (pwm0) and 0x4001 8000 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . .710 table 556: pwm timer control register (tcr - address 0x4001 4004 (pwm0) and 0x4001 8004 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 711 table 557. pwm timer counter registers (tc - addresses 0x4001 4008 (pwm0), 0x4001 8008 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 table 558. pwm prescale registers (pr - addresses 0x4001 400c (pwm0), 0x4001 800c (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .712 table 559. pwm prescale counter registers (pc - addresses 0x4001 4010 (pwm0), 0x4001 8010 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .712 table 560. match control register (mcr - address 0x4001 4014 (pwm0) and 0x4001 8014 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . .712 table 561. pwm match registers (mr[0:3], addresses 0x4001 4018 (mr0) to 0x4001 4024 (mr3) (pwm0), 0x4001 8018 (mr0) to 0x4001 5024 (mr3) (pwm1)) bit description . . . . . . . . . . . .714 table 562. pwm match registers (mr[4:6], addresses 0x4001 4040 (mr4) to 0x4001 4048 (mr6) (pwm0), 0x4001 8040 (mr4) to 0x4001 5048 (mr6) (pwm1)) bit description . . . . . . . . . . . .714 table 563: pwm capture contro l register (ccr - address 0x4001 4028 (pwm0) and 0x4001 8028 (pwm1)) bit description . . . . . . . . . . . . . . . . . . . . . . . . .715 table 564. pwm capture registers (cr[0:1], address 0x4001 402c (cr0) to 0x4001 4038 (cr3) (pwm0), 0x4001 802c (cr0) to 0x4001 8038 (cr3) (pwm1)) bit description . . . . . . . . . . . .716 table 565: pwm control registers (pcr - address 0x4001 404c (pwm0) and 0x4001 804c (pwm1)) bit description . . . . . . . . . . . . . . . . .716 table 566: pwm latch enable register (ler - address 0x4001 4050 (pwm0) and 0x4001 8050 (pwm1)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 717 table 567: pwm count control register (ctcr - address 0x4001 4070 (pwm0) and 0x4001 8070 (pwm1)) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 719 table 568. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 721 table 569. register overview: motor control pulse width modulator (mcpwm) (base address 0x400b 8000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 table 570. mcpwm control read address (con - 0x400b 8000) bit description . . . . . . . . . . . . . 725 table 571. mcpwm control set address (con_set - 0x400b 8004) bit description . . . . . . . . . . . . . 726 table 572. mcpwm control clear address (con_clr - 0x400b 8008) bit description . . . . . . . . . . . . . 727 table 573. mcpwm capture control read address (capcon - 0x400b 800c) bit description . . . 728 table 574. mcpwm capture control set address (capcon_set - 0x400b 8010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 table 575. mcpwm capture control clear register (capcon_clr - address 0x400b 8014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 730 table 576. mcpwm timer/counter 0 to 2 registers (tc[0:2] - 0x400b 8018 (tc0), 0x400b 801c (tc1), 0x400b 8020) (tc2)bit description . . . . . . . . 730 table 577. mcpwm limit 0 to 2 registers (lim[0:2] - 0x400b 8024 (lim0), 0x400b 8028 (lim1), 0x400b 802c (lim2)) bit description . . . . . . . 731 table 578. mcpwm match 0 to 2 registers (mat[0:2] - addresses 0x400b 8030 (mat0), 0x400b 8034 (mat1), 0x400b 8038 (mat2)) bit description 731 table 579. mcpwm dead-time register (dt - address 0x400b 803c) bit description. . . . . . . . . . . . . 733 table 580. mcpwm communication pattern register (cp - address 0x400b 8040) bit description . . . . . . 733 table 581. mcpwm capture read addresses (cap[0:2] - 0x400b 8044 (cap0), 0x400b 8048 (cap1), 0x400b 804c (cap2)) bit description . . . . . . 734 table 582. motor control pwm interrupts. . . . . . . . . . . . 734 table 583. mcpwm interrupt enable read address (inten - 0x400b 8050) bit description . . . . . . . . . . . . . 734 table 584. mcpwm interrupt enable set register (inten_set - address 0x400b 8054) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 table 585. pwm interrupt enable clear register (inten_clr - address 0x400b 8058) bit description . . . . . 736 table 586. mcpwm count control read address (cntcon - 0x400b 805c) bit description. . . . . . . . . . . . 736 table 587. mcpwm count control set address (cntcon_set - 0x400b 8060) bit de scriptio n . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 588. mcpwm count control clear address (cntcon_clr - 0x400b 8064) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 589. mcpwm interrupt flags read address (intf - 0x400b 8068) bit description . . . . . . . . . . . . . 740 table 590. mcpwm interrupt flags set address (intf_set
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 919 of 942 nxp semiconductors UM10562 chapter 41: supplementary information - 0x400b 806c) bit description . . . . . . . . . . . .741 table 591. mcpwm interrupt flags clear address (intf_clr - 0x400b 8070) bit description. . .742 table 592. mcpwm capture clear address (cap_clr - 0x400b 8074) bit description . . . . . . . . . . . . .742 table 593. encoder states . . . . . . . . . . . . . . . . . . . . . . . .751 table 594. encoder state transitions [1] . . . . . . . . . . . . . .751 table 595. encoder direction . . . . . . . . . . . . . . . . . . . . .752 table 596. qei pin description. . . . . . . . . . . . . . . . . . . . .754 table 597. register overview: qei (base address 0x400b c000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .755 table 598: qei control register (con - address 0x400b c000) bit description . . . . . . . . . . . . .756 table 599: qei configuration register (conf - address 0x400b c008) bit description . . . . . . . . . . . . .756 table 600: qei status register (stat - address 0x400b c004) bit description . . . . . . . . . . . . .756 table 601: qei position register (pos - address 0x400b c00c) bit description . . . . . . . . . . . . .757 table 602: qei maximum position register (maxpos - address 0x400b c010) bit description . . . . . .757 table 603: qei position compare register 0 (cmpos0 - address 0x400b c014) bit description . . . . . .757 table 604: qei position compare register 1 (cmpos1 - address 0x400b c018) bit description . . . . . .757 table 605: qei position compare register 2 (cmpos2 - address 0x400b c01c) bit description . . . . . .758 table 606: qei index count register (inxcnt - address 0x400b c020) bit description . . . . . . . . . . . . .758 table 607: qei index compare register 0 (inxcmp0 - address 0x400b c024) bit description . . . . . .758 table 608: qei timer load register (load - address 0x400b c028) bit description . . . . . . . . . . . . .758 table 609: qei timer register (time - address 0x400b c02c) bit description . . . . . . . . . . . . .758 table 610: qei velocity register (vel - address 0x400b c030) bit description . . . . . . . . . . . . .759 table 611: qei velocity capture register (cap - address 0x400b c034) bit description . . . . . . . . . . . . .759 table 612: qei velocity compare register (velcomp - address 0x400b c038) bit description . . . . . .759 table 613: qei digital filter on pha (filterpha - address 0x400b c03c) bit description . . . . . . . . . . . . .759 table 614: qei digital filter on phb (filterphb - address 0x400b c040) bit description . . . . . . . . . . . . .759 table 615: qei digital filter on inx (filterinx - address 0x400b c044) bit description . . . . . . . . . . . . .760 table 616: qei index acceptance window (window - address 0x400b c048) bit description . . . . . .760 table 617: qei index compare register 1 (inxcmp1 - address 0x400b c04c) bit description . . . . . .760 table 618: qei index compare register 2 (inxcmp2 - address 0x400b c050) bit description . . . . . .760 table 619: qei interrupt status register (intstat - address 0x400b cfe0) bit description . . . . . . . . . . . . .761 table 620: qei interrupt set register (set - address 0x400b cfec) bit description . . . . . . . . . . . .762 table 621: qei interrupt clear register (clr - 0x400b cfe8) bit description . . . . . . . . . . . . 763 table 622: qei interrupt enable register (ie - address 0x400b cfe4) bit description . . . . . . . . . . . . 764 table 623: qei interrupt enable set register (ies - address 0x400b cfdc) bit description . . . . . . . . . . . . 765 table 624: qei interrupt enable clear register (iec - address 0x400b cfd8) bit description . . . . . . . . . . . . 766 table 625. rtc pin description. . . . . . . . . . . . . . . . . . . . 769 table 626. register overview: real-time clock (base address 0x4002 4000) . . . . . . . . . . . . . . . . . . 770 table 627. interrupt location register (ilr - address 0x4002 4000) bit description . . . . . . . . . . . . . 771 table 628. clock control register (ccr - address 0x4002 4008) bit description . . . . . . . . . . . . . 771 table 629. counter increment interrupt register (ciir - address 0x4002 400c) bit description . . . . . . 772 table 630. alarm mask register (amr - address 0x4002 4010) bit description . . . . . . . . . . . . . 772 table 631. rtc auxiliary control register (rtc_aux - address 0x4002 405c) bit description . . . . . . 773 table 632. rtc auxiliary enable register (rtc_auxen - address 0x4002 4058) bit description . . . . . . 773 table 633. consolidated time register 0 (ctime0 - address 0x4002 4014) bit description . . . . . . . . . . . . . 774 table 634. consolidated time register 1 (ctime1 - address 0x4002 4018) bit description . . . . . . . . . . . . . 774 table 635. consolidated time register 2 (ctime2 - address 0x4002 401c) bit description . . . . . . . . . . . . . 774 table 636. time counter relationships and values . . . . . 774 table 637. time counter registers . . . . . . . . . . . . . . . . . 775 table 638. seconds register (sec - address 0x4002 4020) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 775 table 639. minutes register (min - address 0x4002 4024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 table 640. hours register (hrs - address 0x4002 4028) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 table 641. day of month register (dom - address 0x4002 402c) bit description . . . . . . . . . . . . . 776 table 642. day of week register (dow - address 0x4002 4030) bit description . . . . . . . . . . . . . 776 table 643. day of year register (doy - address 0x4002 4034) bit description . . . . . . . . . . . . . 776 table 644. month register (month - address 0x4002 4038) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 776 table 645. year register ( year - address 0x4002 403c) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 table 646. calibration register (calibration - address 0x4002 4040) bit description . . . . . . . . . . . . . 777 table 647. general purpose registers (gpreg[0:4] - a ddresses 0x4002 40 44 (gpreg0) to 0x4002 4054 (gpreg4)) bit description . . . . 778 table 648. alarm registers . . . . . . . . . . . . . . . . . . . . . . . 778 table 649. alarm seconds register (asec - address 0x4002 4060) bit description . . . . . . . . . . . . . 778 table 650. alarm minutes register (amin - address 0x4002 4064) bit description . . . . . . . . . . . . . 778 table 651. alarm hours register (ahrs - address 0x4002 4068) bit description . . . . . . . . . . . . . 779
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 920 of 942 nxp semiconductors UM10562 chapter 41: supplementary information table 652. alarm day of month register (adom - address 0x4002 406c) bit description . . . . . . . . . . . . .779 table 653. alarm day of week register (adow - address 0x4002 4070) bit description . . . . . . . . . . . . .779 table 654. alarm day of year register (adoy - address 0x4002 4074) bit description . . . . . . . . . . . . .779 table 655. alarm month register (amon - address 0x4002 4078) bit description . . . . . . . . . . . . .779 table 656. alarm year register (ayrs - address 0x4002 407c) bit description . . . . . . . . . . . . .779 table 657. event monitor/recorder pin description. . . . .784 table 658. register overview: event monitor/recorder (base address 0x4002 4000) . . . . . . . . . . . . . . . . . .784 table 659. event monitor/recorder control register (ercontrol - 0x4002 4084) bit description785 table 660. event monitor/recorder status register (erstatus - 0x4002 4080) bit description . .787 table 661. event monitor/recorder counters register (ercounters - 0x4002 4088) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .788 table 662. event monitor/recorder first stamp register (erfirststamp0 - 0x0x4002 4090, erfirststamp1 - 0x0x4002 4094, erfirststamp2 - 0x4002 4098) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .788 table 663. event monitor/recorder last stamp register (erlaststamp0 - 0x0x4002 40a0, erlaststamp1 - 0x0x4002 40a4, erlaststamp2 - 0x4002 40a8) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .789 table 664. register overview: watchdog (base address 0x4000 0000) . . . . . . . . . . . . . . . . . . . . . . . . .793 table 665: watchdog mode register (mod - 0x4000 0000) bit description . . . . . . . . . . . . . . . . . . . . . . . . .794 table 666. watchdog operating modes selection . . . . . .795 table 667: watchdog timer constant register (tc - address 0x4000 0004) bit description . . . . . . . . . . . . .795 table 668: watchdog feed register (feed - address 0x4000 0008) bit description . . . . . . . . . . . . .795 table 669: watchdog timer value register (tv - address 0x4000 000c) bit description . . . . . . . . . . . . .796 table 670: watchdog timer warning interrupt register (warnint - address 0x4000 0014) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .796 table 671: watchdog timer window register (window - address 0x4000 0018) bit description. . . . . . .796 table 672. adc pin description . . . . . . . . . . . . . . . . . . . .800 table 673. register overview: adc (base address 0x4003 4000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .801 table 674: a/d control register (cr - address 0x4003 4000) bit description . . . . . . . . . . . . .802 table 675: a/d global data register (gdr - address 0x4003 4004) bit description . . . . . . . . . . . . .803 table 676: a/d interrupt enable register (inten - address 0x4003 400c) bit description . . . . . . . . . . . . .804 table 677: a/d data registers (dr[0:7] - addresses 0x4003 4010 (dr0) to 0x4003 402c (dr7)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .805 table 678: a/d status register (stat - address 0x4003 4030) bit description . . . . . . . . . . . . . 806 table 679: a/d trim register (trm - address 0x4003 4034) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 807 table 680. d/a pin description . . . . . . . . . . . . . . . . . . . . 810 table 681. register overview: dac (base address 0x4008 c000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 table 682: d/a converter register (cr - address 0x4008 c000) bit description . . . . . . . . . . . . . 811 table 683. d/a control register (ctrl - address 0x4008 c004) bit description . . . . . . . . . . . . . 812 table 684: d/a converter counter value register (cntval - address 0x4008 c008) bit description . . . . . . 812 table 685: comparator pin description . . . . . . . . . . . . . . 817 table 686. register overview: comparator (base address 0x4002 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 817 table 687. comparator block control register (cmp_ctrl - address 0x4002 0000) bit description . . . . . . 818 table 688. comparator 0 control register (cmp_ctrl0 - address 0x4002 0004) bit description . . . . . 819 table 689. comparator 1 control register (cmp_ctrl1 - 0x4002 0008) bit description . . . . . . . . . . . . 822 table 690: interrupt configurations . . . . . . . . . . . . . . . . . 824 table 691. endian behavior . . . . . . . . . . . . . . . . . . . . . . 828 table 692. dma connections . . . . . . . . . . . . . . . . . . . . . 831 table 693. register overview: gpdma (base address 0x2008 0000) . . . . . . . . . . . . . . . . . . . . . . . . . 833 table 694. dma interrupt status register (intstat, address 0x2008 0000) bit description . . . . . . . . . . . . . 835 table 695. ma interrupt terminal count request status register (inttcstat, address 0x2008 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 table 696. dma interrupt terminal count request clear register (inttcclear, address 0x2008 0008) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 835 table 697. dma interrupt error status register (interrstat, address 0x2008 000c) bit description. . . . . . . . . . . . . . . . . . . . . . . . . 836 table 698. dma interrupt error clear register (interrclr, address 0x2008 0010) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 table 699. dma raw interrupt terminal count status register (rawinttcstat, address 0x2008 0014) bit description . . . . . . . . . . . . . . . . . . . 836 table 700. dma raw error interrupt status register (rawinterrstat, address 0x2008 0018) bit description . . . . . . . . . . . . . . . . . . . 837 table 701. dma enabled channel register (enbldchns, address 0x2008 001c) bit description . . . . . 837 table 702. dma software burst request register (softbreq, address 0x2008 0020) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 table 703. dma software single request register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 838 table 704. dma software last burst request register (softlbreq, address 0x2008 0028) bit de scr iption. . . . . . . . . . . . . . . . . . . . . . . . . 838 table 705. dma software last single request
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 921 of 942 nxp semiconductors UM10562 chapter 41: supplementary information register (softlsreq, address 0x2008 002c) bit description . . . . . . . . . . . . . . . . . . . . . . . . .839 table 706. dma configuration register (config, address 0x2008 0030) bit description . . . . . . . . . . . . .839 table 707. dma synchronization register (sync, address 0x2008 0034) bit description . . . . . . . . . . . . .840 table 708. dma channel source address registers (srcaddr[0:7], 0x2008 0100 (srcaddr0) to 0x2008 01e0 (srcaddr7)) bit description .840 table 709. dma channel destination address registers (destaddr[0:7], 0x2008 0104 (destaddr0) to 0x2008 01e4 (destaddr7)) bit description . . . . . . . . . . . . . . . . . . . . . . . .841 table 710. dma channel linked list item registers (lli[0:7], 0x2008 0108 (lli0) to 0x2008 01e8 (lli7)) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .841 table 711. dma channel control registers (control[0:7], 0x2008 010c (control0) to 0x2008 01ec (control7)) bit description . . . . . . . . . . . .842 table 712. dma channel configuration registers (config[0:7], 0x2008 0110 (config0) to 0x2008 01f0 (config7)) bit description . . .844 table 713. transfer type bits . . . . . . . . . . . . . . . . . . . . .845 table 714. dma request signal usage . . . . . . . . . . . . . .848 table 715. register overview: crc engine (base address 0x2009 0000) . . . . . . . . . . . . . . . . . . . . . . . . .856 table 716. crc mode register (mode - address 0x2009 0000) bit description . . . . . . . . . . . . .856 table 717. crc seed register (seed - address 0x2009 0004) bit description . . . . . . . . . . . . .856 table 718. crc checksum register (sum - address 0x2009 0008) bit description . . . . . . . . . . . . .857 table 719. crc data register (data - address 0x2009 0008) bit description . . . . . . . . . . . . . . . . . . . . . . . . .857 table 720. register overview: eeprom controller (base address 0x0020 0000) . . . . . . . . . . . . . . . . . .864 table 721. eeprom command register (cmd - address 0x0020 0080) bit description . . . . . . . . . . . . .865 table 722. eeprom address re gister (addr - address 0x0020 0084) address description . . . . . . . . .865 table 723. eeprom write data register (wdata - address 0x0020 0088) bit description . . . . . . . . . . . . .866 table 724. eeprom read data register (rdata - address 0x0020 008c) bit description . . . . . . . . . . . . .866 table 725. eeprom wait state register (wstate - address 0x0020 0090) bit description . . . . . . . . . . . . .867 table 726. eeprom clock divider register (clkdiv - address 0x0020 0094) bit description. . . . . . .868 table 727. eeprom power down /dcm register (pwrdwn - address 0x0020 0098) bit description . . . . .868 table 728. interrupt status register (intstat - address 0x0020 0fe0) bit description . . . . . . . . . . . . .869 table 729. interrupt status clear register (intstatclr - address 0x0020 0fe8) bit description . . . . . .869 table 730. interrupt status set register (intstatset - address 0x0020 0fec). . . . . . . . . . . . . . . . . .870 table 731. interrupt enable register (inten - address 0x0020 0fe4) bit description . . . . . . . . . . . . .870 table 732. interrupt enable clear register (intenclr - address 0x0020 0fd8) bit description . . . . . . 870 table 733. interrupt enable set register (intenset - address 0x0020 0fdc) bit description. . . . . . 871 table 734. flash sectors details . . . . . . . . . . . . . . . . . . . 878 table 735. code read protection options . . . . . . . . . . . 879 table 736. code read protection hardware/software interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . 880 table 737. isp command summary . . . . . . . . . . . . . . . . 881 table 738. isp unlock command . . . . . . . . . . . . . . . . . . 881 table 739. isp set baud rate command . . . . . . . . . . . . 882 table 740. isp echo command . . . . . . . . . . . . . . . . . . . 882 table 741. isp write to ram command . . . . . . . . . . . . . 883 table 742. isp read memory command . . . . . . . . . . . . 883 table 743. isp prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884 table 744. isp copy command . . . . . . . . . . . . . . . . . . . 884 table 745. isp go command . . . . . . . . . . . . . . . . . . . . . 885 table 746. isp erase sector command . . . . . . . . . . . . . 885 table 747. isp blank check sector command . . . . . . . . 886 table 748. isp read part identification command . . . . . 886 table 749. part identification numbers . . . . . . . . . . . . . . 886 table 750. isp read boot code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886 table 751. isp read device serial number command . . 887 table 752. isp compare command . . . . . . . . . . . . . . . . 887 table 753. isp return codes summary. . . . . . . . . . . . . 888 table 754. iap command summary . . . . . . . . . . . . . . . 890 table 755. iap prepare sector(s) for write operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891 table 756. iap copy ram to flash command . . . . . . . . 891 table 757. iap erase sector(s) command . . . . . . . . . . . 892 table 758. iap blank check se ctor(s) command . . . . . . 892 table 759. iap read part identification number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 table 760. iap read boot code version number command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 table 761. iap read device serial number command . . 893 table 762. iap compare command . . . . . . . . . . . . . . . . 893 table 763. re-invoke isp . . . . . . . . . . . . . . . . . . . . . . . . 894 table 764. iap status codes summary . . . . . . . . . . . . . 894 table 765. register overview: flash controller (base address 0x0020 0000) . . . . . . . . . . . . . . . . . . . . . . . . 895 table 766. flash module signature start register (fmsstart - 0x0020 0020) bit description . 896 table 767. flash module signature stop register (fmsstop - 0x0020 0024) bit description . . . . . . . . . . . . 896 t able 76 8. fmsw0 register bit description (fmsw0, address: 0x0020 002c) . . . . . . . . . . . . . . . . . 896 table 769. fmsw1 register bit description (fmsw1, address: 0x0020 0030) . . . . . . . . . . . . . . . . . 896 table 770. fmsw2 register bit description (fmsw2, address: 0x0020 0034) . . . . . . . . . . . . . . . . . 896 table 771. fmsw3 register bit description (fmsw3, address: 0x0020 0038) . . . . . . . . . . . . . . . . 896 table 772. flash module status register (stat - 0x0020 0fe0) bit description . . . . . . . . . . . . . 897 table 773. flash module status clear register (statclr -
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 922 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 0x0x0020 0fe8) bit description . . . . . . . . . . .897 table 774. jtag pin description . . . . . . . . . . . . . . . . . . .900 table 775. serial wire debug pin description . . . . . . . . .900 table 776. parallel trace pin description. . . . . . . . . . . . .900 table 777. memory mapping control register (memmap - 0x400f c040) bit description . . . . . . . . . . . . .903 table 778. abbreviations . . . . . . . . . . . . . . . . . . . . . . . .906
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 923 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 41.4 figures fig 1. lpc408x/407x simplified block diagram . . . . . . . .9 fig 2. lpc408x/407x block diagram, cpu and buses. .12 fig 3. system memory map . . . . . . . . . . . . . . . . . . . . . .15 fig 4. clock generation . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 5. emc programmable delays . . . . . . . . . . . . . . . . .41 fig 6. emc delay calibration . . . . . . . . . . . . . . . . . . . . .42 fig 7. reset block diagram . . . . . . . . . . . . . . . . . . . . . .51 fig 8. example of start-up after reset. . . . . . . . . . . . . . .52 fig 9. external interrupt logic . . . . . . . . . . . . . . . . . . . . .55 fig 10. oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for c x1 / x2 evaluation58 fig 11. pll0 and pll1 block diagram. . . . . . . . . . . . . . .62 fig 12. clkout selection . . . . . . . . . . . . . . . . . . . . . . . .73 fig 13. simplified block diagram of the flash accelerator showing potential bus connections . . . . . . . . . . .74 fig 14. i/o configurations. . . . . . . . . . . . . . . . . . . . . . . .120 fig 15. gpio interrupt block diagram . . . . . . . . . . . . . .149 fig 16. emc block diagram . . . . . . . . . . . . . . . . . . . . . .164 fig 17. sdram mode register . . . . . . . . . . . . . . . . . . . .171 fig 18. 32 bit bank external memory interfaces ( bits mw = 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 fig 19. 16 bit bank external memory interfaces (bits mw = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 fig 20. 8 bit bank external memory interface (bits mw = 00) . . . . . . . . . . . . . . . . . . . . . . . . . .198 fig 21. typical memory configuration diagram . . . . . . .199 fig 22. ethernet block diagram . . . . . . . . . . . . . . . . . . .202 fig 23. ethernet packet fields . . . . . . . . . . . . . . . . . . . .204 fig 24. receive descriptor memory layout. . . . . . . . . . .231 fig 25. transmit descriptor memory layout . . . . . . . . . .234 fig 26. transmit example memory and registers. . . . . .247 fig 27. receive example memory and registers . . . . .253 fig 28. transmit flow control . . . . . . . . . . . . . . . . . . . .258 fig 29. receive filter block diagram. . . . . . . . . . . . . . . .260 fig 30. receive active/inactive state machine . . . . . . .264 fig 31. transmit active/inactive state machine . . . . . . .265 fig 32. lcd controller block diagram. . . . . . . . . . . . . . .281 fig 33. cursor movement . . . . . . . . . . . . . . . . . . . . . . .289 fig 34. cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .290 fig 35. cursor image format . . . . . . . . . . . . . . . . . . . . .291 fig 36. power-up and power-down sequences . . . . . . .296 fig 37. horizontal timing for stn displays. . . . . . . . . . .314 fig 38. vertical timing for stn displays . . . . . . . . . . . . .315 fig 39. horizontal timing for tft displays . . . . . . . . . . .315 fig 40. vertical timing for tft displays . . . . . . . . . . . . .316 fig 41. usb device controller block diagram . . . . . . . . .323 fig 42. usb maxpacketsize register array indexing . . .340 fig 43. interrupt event handling . . . . . . . . . . . . . . . . . . .355 fig 44. udca head register and dma descriptors . . . .371 fig 45. isochronous out endpoint operation example .378 fig 46. data transfer in atle mode. . . . . . . . . . . . . . . .379 fig 47. usb host controller block diagram . . . . . . . . . .387 fig 48. usb otg controller block diagram . . . . . . . . . .392 fig 49. usb otg port configuration: port u1 otg dual-role device, port u2 host . . . . . . . . . . . . . . . . . . . . . .394 fig 50. usb otg port configuration: vp_vm mode . . . 395 fig 51. usb host port configuration: port u1 and u2 as hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 fig 52. usb device port configuration: port u1 host and port u2 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 fig 53. port selection for port_func bit 0 = 0 and port_func bit 1 = 0 . . . . . . . . . . . . . . . . . . . 402 fig 54. usb otg interrupt handling . . . . . . . . . . . . . . . 409 fig 55. usb otg controller with software stack . . . . . . 411 fig 56. hardware support for b-device switching from peripheral state to host state . . . . . . . . . . . . . . 412 fig 57. state transitions implemented in software during b-device switching from peripheral to host . . . . 413 fig 58. hardware support for a-device switching from host state to peripheral state. . . . . . . . . . . . . . . . . . . 415 fig 59. state transitions implemented in software during a-device switching from host to peripheral . . . . 416 fig 60. clocking and power control. . . . . . . . . . . . . . . . 420 fig 61. secure digital memory card connection . . . . . . 435 fig 62. multimedia card system . . . . . . . . . . . . . . . . . . 436 fig 63. sd card interface . . . . . . . . . . . . . . . . . . . . . . . 437 fig 64. command path state machine . . . . . . . . . . . . . 438 fig 65. command transfer . . . . . . . . . . . . . . . . . . . . . . 439 fig 66. data path state machine . . . . . . . . . . . . . . . . . . 441 fig 67. pending command start . . . . . . . . . . . . . . . . . . 443 fig 68. uart1 block diagram . . . . . . . . . . . . . . . . . . . . 458 fig 69. auto-rts functional timing . . . . . . . . . . . . . . . 471 fig 70. auto-cts functional timing . . . . . . . . . . . . . . . 472 fig 71. auto-baud a) mode 0 and b) mode 1 waveform 479 fig 72. algorithm for setting uart dividers . . . . . . . . . 481 fig 73. uart0, 2, and 3 block diagram . . . . . . . . . . . . 489 fig 74. auto-baud a) mode 0 and b) mode 1 waveform 502 fig 75. algorithm for setting uart dividers . . . . . . . . . 504 fig 76. uart 4 block diagram . . . . . . . . . . . . . . . . . . . 512 fig 77. auto-baud a) mode 0 and b) mode 1 waveform 526 fig 78. algorithm for setting uart dividers . . . . . . . . . 529 fig 79. can controller block diagram . . . . . . . . . . . . . . 540 fig 80. transmit buffer layout for standard and extended frame format configurations . . . . . . . . . . . . . . . 541 fig 81. receive buffer layout for standard and extended frame format configurations . . . . . . . . . . . . . . . 542 fig 82. global self-test (high-speed can bus example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 fig 83. local self test (high-speed can bus example). 543 fig 84. entry in fullcan and individual standard identifier tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 fig 85. entry in standard identifier range table . . . . . . . 570 fig 86. entry in either extended identifier table . . . . . . . 570 fig 87. id look-up table example explaining the search algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 fig 88. semaphore procedure for reading an auto-stored message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 fig 89. fullcan section example of the id look-up table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 fig 90. fullcan message object layout . . . . . . . . . . . . 582 fig 91. normal case, no messages lost . . . . . . . . . . . . 584
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 924 of 942 nxp semiconductors UM10562 chapter 41: supplementary information fig 92. message lost . . . . . . . . . . . . . . . . . . . . . . . . . . .584 fig 93. message gets overwritten . . . . . . . . . . . . . . . . .585 fig 94. message overwritten indicated by semaphore bits and message lost. . . . . . . . . . . . . . . . . . . . . . . .586 fig 95. message overwritten indicated by message lost587 fig 96. clearing message lost . . . . . . . . . . . . . . . . . . . .588 fig 97. detailed example of acceptance filter tables and id index values. . . . . . . . . . . . . . . . . . . . . . . . . . . .590 fig 98. id look-up table configuration example (no fullcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592 fig 99. id look-up table configuration example (fullcan activated and enabled) . . . . . . . . . . . . . . . . . . .594 fig 100. texas instruments synchronous serial frame format: a) single and b) continuous/back-to-back two frames transfer. . . . . . . . . . . . . . . . . . . . .598 fig 101. spi frame format with cpol=0 and cpha=0 (a) single and b) continuous transfer) . . . . . . . . . .599 fig 102. spi frame format with cpol=0 and cpha=1 . .600 fig 103. spi frame format with cpol = 1 and cpha = 0 (a) single and b) continuous transfer) . . . . . . . . . .601 fig 104. spi frame format with cpol = 1 and cpha = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602 fig 105. microwire frame format (single transfer) . . . . . .603 fig 106. microwire frame format (continuos transfers) . .604 fig 107. microwire frame format setup and hold details .604 fig 108. i 2 c-bus configuration. . . . . . . . . . . . . . . . . . . . .613 fig 109. format in the master transmitter mode . . . . . .615 fig 110. format of master receiver mode . . . . . . . . . . .616 fig 111. a master receiver swit ches to master transmitter after sending repeated start . . . . . . . . . . . . .616 fig 112. format of slave receiver mode . . . . . . . . . . . .617 fig 113. format of slave transmitter mode . . . . . . . . . .618 fig 114. i 2 c serial interface block diagram . . . . . . . . . . .619 fig 115. arbitration procedure . . . . . . . . . . . . . . . . . . . . .621 fig 116. serial clock synchronization . . . . . . . . . . . . . . .621 fig 117. format and states in the master transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634 fig 118. format and states in the master receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .636 fig 119. format and states in the slave receiver mode.638 fig 120. format and states in the slave transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639 fig 121. simultaneous repeated start conditions from two masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 fig 122. forced access to a busy i 2 c-bus . . . . . . . . . . .647 fig 123. recovering from a bus obstruction caused by a low level on sda . . . . . . . . . . . . . . . . . . . . . . .648 fig 124. simple i 2 s configurations and bus timing . . . . .663 fig 125. typical transmitter master mode, with or without mclk output . . . . . . . . . . . . . . . . . . . . . . . . . . .675 fig 126. transmitter master mode sharing the receiver reference clock . . . . . . . . . . . . . . . . . . . . . . . . .675 fig 127. 4-wire transmitter master mode sharing the receiver bit clock and ws . . . . . . . . . . . . . . . . . . . . . . . .675 fig 128. typical transmitter slave mode . . . . . . . . . . . . .675 fig 129. transmitter slave mode sharing the receiver reference clock . . . . . . . . . . . . . . . . . . . . . . . . .676 fig 130. 4-wire transmitter slave mode sharing the receiver bit clock and ws . . . . . . . . . . . . . . . . . . . . . . . . 676 fig 131. typical receiver master mode, with or without mclk output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 fig 132. receiver master mode sharing the transmitter reference clock . . . . . . . . . . . . . . . . . . . . . . . . . 678 fig 133. 4-wire receiver master mode sharing the transmitter bit clock and ws . . . . . . . . . . . . . . . . . . . . . . . . 678 fig 134. typical receiver slave mode . . . . . . . . . . . . . . . 678 fig 135. receiver slave mode sharing the transmitter reference clock . . . . . . . . . . . . . . . . . . . . . . . . . 679 fig 136. 4-wire receiver slave mode sharing the transmitter bit clock and ws . . . . . . . . . . . . . . . . . . . . . . . . 679 fig 137. i 2 s clocking and pin connections . . . . . . . . . . . 680 fig 138. fifo contents for various i 2 s modes . . . . . . . . 682 fig 139. timer block diagram . . . . . . . . . . . . . . . . . . . . . 685 fig 140. a timer cycle in wh ich pr=2, mrx=6, and both interrupt and reset on match are enabled. . . . . 697 fig 141. a timer cycle in which pr=2, mrx=6, and both interrupt and stop on match are enabled . . . . . 697 fig 142. system tick timer block diagram . . . . . . . . . . . 699 fig 143. pwm block diagram . . . . . . . . . . . . . . . . . . . . . 706 fig 144. sample pwm waveforms . . . . . . . . . . . . . . . . . 707 fig 145. mcpwm block diagram . . . . . . . . . . . . . . . . . . 722 fig 146. edge-aligned pwm waveform without dead time, pola = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 fig 147. center-aligned pwm waveform without dead time, pola = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 fig 148. edge-aligned pwm waveform with dead time, pola = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744 fig 149. center-aligned waveform with dead time, pola = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745 fig 150. three-phase dc mode sample waveforms . . . 747 fig 151. three-phase ac mode sample waveforms, edge aligned pwm mode. . . . . . . . . . . . . . . . . . . . . . 748 fig 152. encoder interface block diagram . . . . . . . . . . . 750 fig 153. quadrature encoder basic operation. . . . . . . . 752 fig 154. rtc domain conceptual diagram . . . . . . . . . . . 768 fig 155. rtc functional block diagram. . . . . . . . . . . . . . 768 fig 156. event monitor/recorder block diagram . . . . . . 783 fig 157. watchdog timer block diagram . . . . . . . . . . . . 792 fig 158. early watchdog feed with windowed mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 fig 159. correct watchdog feed with windowed mode enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 fig 160. watchdog warning interrupt . . . . . . . . . . . . . . . 798 fig 161. adc block diagram . . . . . . . . . . . . . . . . . . . . . 800 fig 162. dac control with dma interrupt and timer . . . . 810 fig 163. comparator block diagram . . . . . . . . . . . . . . . . 816 fig 164. dma controller block diagram. . . . . . . . . . . . . . 827 fig 165. lli example . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 fig 166. crc block diagram. . . . . . . . . . . . . . . . . . . . . . 855 fig 167. eeprom block diagram. . . . . . . . . . . . . . . . . . 859 fig 168. starting a write operation . . . . . . . . . . . . . . . . . 861 fig 169. (16-bit) write operations with post-incrementing of address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861 fig 170. programming a page into memory . . . . . . . . . . 862 fig 171. starting a read operation (32-bit read from address a). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 925 of 942 nxp semiconductors UM10562 chapter 41: supplementary information fig 172. map of lower memory . . . . . . . . . . . . . . . . . . . .873 fig 173. boot process flowchart . . . . . . . . . . . . . . . . . . .877 fig 174. iap parameter passing . . . . . . . . . . . . . . . . . . .890 fig 175. algorithm for generating a 128 bit signature . . .898 fig 176. arm standard jtag connector . . . . . . . . . . . .901 fig 177. cortex debug connector. . . . . . . . . . . . . . . . . .902 fig 178. cortex debug & etm connector. . . . . . . . . . . .902
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 926 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 41.5 contents chapter 1: introductory information 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 ordering information . . . . . . . . . . . . . . . . . . . . . 8 1.4.1 part options summary. . . . . . . . . . . . . . . . . . . . 8 5 simplified block diagram . . . . . . . . . . . . . . . . . 9 1.6 architectural overview . . . . . . . . . . . . . . . . . . 10 1.7 arm cortex-m4 processor . . . . . . . . . . . . . . . 10 1.8 on-chip flash memory system. . . . . . . . . . . . 10 1.9 on-chip static ram. . . . . . . . . . . . . . . . . . . . . 10 1.10 on-chip eeprom . . . . . . . . . . . . . . . . . . . . . . . 11 1.11 detailed block diagram . . . . . . . . . . . . . . . . . . 12 chapter 2: lpc408x/407x memory map 2.1 memory map and peripheral addressing. . . . 13 2.2 memory maps. . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . 16 2.3.1 ahb peripherals . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 apb peripheral addresses . . . . . . . . . . . . . . . 16 2.4 memory re-mapping . . . . . . . . . . . . . . . . . . . . 17 boot rom re-mapping . . . . . . . . . . . . . . . . . . . 17 2.5 ahb arbitration . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.1 matrix arbitration register. . . . . . . . . . . . . . . . 18 chapter 3: lpc408x/407x system and clock control 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 summary of clocking and power control functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 register description . . . . . . . . . . . . . . . . . . . . 22 3.3.1 pll registers . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1.1 pll control registers . . . . . . . . . . . . . . . . . . . 24 3.3.1.2 pll configuration registers . . . . . . . . . . . . . . 24 3.3.1.3 pll status registers . . . . . . . . . . . . . . . . . . . . 25 3.3.1.4 pll interrupts: plock0 and plock1. . . . . . 25 3.3.1.5 pll feed registers . . . . . . . . . . . . . . . . . . . . 25 3.3.2 power control . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.2.1 power mode control register . . . . . . . . . . . . . 27 3.3.2.1.1 encoding of reduced power modes . . . . . . . 28 3.3.2.2 power control for peripherals registers . . . . . 28 3.3.2.3 power boost control register . . . . . . . . . . . . . 30 3.3.3 clock selection and divider registers . . . . . . . 31 3.3.3.1 emc clock selection register . . . . . . . . . . . . 31 3.3.3.2 cpu clock selection register . . . . . . . . . . . . 31 3.3.3.3 usb clock selection register . . . . . . . . . . . . . 32 3.3.3.4 clock source selection register . . . . . . . . . . . 33 3.3.3.5 peripheral clock selection register. . . . . . . . . 33 3.3.3.6 spifi clock selection register . . . . . . . . . . . . 33 3.3.4 external interrupts. . . . . . . . . . . . . . . . . . . . . . 35 3.3.4.1 external interrupt flag register . . . . . . . . . . . . 35 3.3.4.2 external interrupt mode register . . . . . . . . . . 36 3.3.4.3 external interrupt polarity register . . . . . . . . . 37 3.3.5 device and peripheral reset . . . . . . . . . . . . . 38 3.3.5.1 reset source identification register . . . . . . . 38 3.3.5.2 reset control register 0 . . . . . . . . . . . . . . . . . 39 3.3.5.3 reset control register 1 . . . . . . . . . . . . . . . . . 40 3.3.6 emc delay control and calibration . . . . . . . . . 41 3.3.6.1 emc delay control register . . . . . . . . . . . . . . 41 3.3.6.2 emc calibration register . . . . . . . . . . . . . . . . 42 procedure for calibrating programmable delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 3.3.7 miscellaneous system control registers . . . . . 44 3.3.7.1 system controls and status register . . . . . . . 44 3.3.7.2 lcd configuration register . . . . . . . . . . . . . . 45 3.3.7.3 can sleep clear register . . . . . . . . . . . . . . . 46 3.3.7.4 can wake-up flags register . . . . . . . . . . . . 46 3.3.7.5 usb interrupt status register . . . . . . . . . . . . 47 3.3.7.6 dma request select register . . . . . . . . . . . . 48 3.3.7.6.1 timer dma requests . . . . . . . . . . . . . . . . . . . 49 3.3.7.7 clock output configuration register . . . . . . . 49 3.4 chip reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5 peripheral reset control . . . . . . . . . . . . . . . . . 53 3.6 brown-out detection . . . . . . . . . . . . . . . . . . . . 54 3.7 external interrupt inputs. . . . . . . . . . . . . . . . . 55 3.7.1 register description . . . . . . . . . . . . . . . . . . . . 56 3.8 oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.8.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 57 3.8.2 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 57 3.8.2.1 main oscillator startup . . . . . . . . . . . . . . . . . . 59 3.8.3 rtc oscillator . . . . . . . . . . . . . . . . . . . . . . . . 59 3.8.4 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 59 3.9 clock source selection multiplexer. . . . . . . . 60 3.10 pll0 and pll1 (phase locked loops) . . . . . 61 3.10.1 pll and startup/boot code interaction . . . . . . 61 3.10.2 pll register description . . . . . . . . . . . . . . . . . 62 3.10.3 plls and power-down mode. . . . . . . . . . . . . 63 3.10.4 pll frequency calculation . . . . . . . . . . . . . . . 64 3.10.5 procedure for determining pll settings. . . . . 64 3.10.6 pll configuration sequence . . . . . . . . . . . . . 66 to set up a pll and switch clocks to its output: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 to switch clocks away from a pll output:. . . . 66 3.10.7 pll configuration examples. . . . . . . . . . . . . . 67 3.11 clock selection and division . . . . . . . . . . . . . 68 3.12 power control . . . . . . . . . . . . . . . . . . . . . . . . . 68
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 927 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 3.12.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.12.2 deep sleep mode . . . . . . . . . . . . . . . . . . . . . . 69 3.12.3 power-down mode . . . . . . . . . . . . . . . . . . . . . 70 3.12.4 deep power-down mode . . . . . . . . . . . . . . . . 70 3.12.5 peripheral power control. . . . . . . . . . . . . . . . . 70 3.12.6 power boost . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.12.7 register description . . . . . . . . . . . . . . . . . . . . 71 3.12.8 wake-up from reduced power modes . . . . . 71 3.12.9 power control usage notes . . . . . . . . . . . . . . 71 3.12.10 power domains . . . . . . . . . . . . . . . . . . . . . . . 72 3.13 wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.14 external clock output pin . . . . . . . . . . . . . . . . 73 chapter 4: lpc408x/407x flash accelerator 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.2 flash accelerator blocks . . . . . . . . . . . . . . . . . 74 4.2.1 flash memory bank . . . . . . . . . . . . . . . . . . . . 74 4.2.2 flash programming issues . . . . . . . . . . . . . . . 75 4.3 register description . . . . . . . . . . . . . . . . . . . . 76 4.4 flash accelerator configuration register . . . 76 4.5 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 chapter 5: lpc408x/407x nested vectored interrupt controller (nvic) 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 vector table remapping . . . . . . . . . . . . . . . . . . 82 examples: . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 5.5 register description . . . . . . . . . . . . . . . . . . . . 83 5.5.1 . . . . . interrupt set-enable register 0 register 84 5.5.2 . . . . . interrupt set-enable register 1 register 85 5.5.3 interrupt clear-enable register 0 . . . . . . . . . . 86 5.4 . . . interrupt clear-enable register 1 register 87 5.5.5 . . . . interrupt set-pending register 0 register 88 5.5.6 . . . . interrupt set-pending register 1 register 89 5.5.7 . . interrupt clear-pending register 0 register 90 5.5.8 . . interrupt clear-pending register 1 register 91 5.5.9 interrupt active bit register 0 . . . . . . . . . . . . 92 5.5.10 interrupt active bit register 1 . . . . . . . . . . . . 93 5.5.11 interrupt priority register 0 . . . . . . . . . . . . . . 94 5.5.12 interrupt priority register 1 . . . . . . . . . . . . . . 94 5.5.13 interrupt priority register 2 . . . . . . . . . . . . . . 94 5.5.14 interrupt priority register 3 . . . . . . . . . . . . . . 95 5.5.15 interrupt priority register 4 . . . . . . . . . . . . . . 95 5.5.16 interrupt priority register 5 . . . . . . . . . . . . . . 95 5.5.17 interrupt priority register 6 . . . . . . . . . . . . . . 96 5.5.18 interrupt priority register 7 . . . . . . . . . . . . . . 96 5.5.19 interrupt priority register 8 . . . . . . . . . . . . . . 96 5.5.20 interrupt priority register 9 . . . . . . . . . . . . . . 97 5.5.21 interrupt priority register 10 . . . . . . . . . . . . . 97 5.5.22 software trigger interrupt register . . . . . . . . 97 chapter 6: lpc408x/407x pin configuration 6.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . 98 chapter 7: lpc408x/407x i/o configuration 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.3 iocon registers . . . . . . . . . . . . . . . . . . . . . . . 119 multiple connections . . . . . . . . . . . . . . . . . . . .120 7.3.1 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.3.2 pin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.3.3 hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.3.4 input inversion . . . . . . . . . . . . . . . . . . . . . . . 121 7.3.5 analog/digital mode . . . . . . . . . . . . . . . . . . . 121 7.3.6 input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.3.7 output slew rate . . . . . . . . . . . . . . . . . . . . . . 121 7.3.8 i 2 c modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3.9 open-drain mode . . . . . . . . . . . . . . . . . . . . . 122 7.3.10 dac enable . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.4 register description . . . . . . . . . . . . . . . . . . . 123 7.4.1 i/o configuration register contents (iocon) 129 7.4.1.1 type d iocon registers (applies to most gpio port pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.4.1.2 type a iocon registers (applies to pins that include an analog function) . . . . . . . . . . . . . 136 7.4.1.3 type u iocon registers (applies to pins that include a usb d+ or d- function). . . . . . . . . 138 7.4.1.4 type i iocon registers (applies to pins that include a specialized i 2 c function) . . . . . . . . 139 7.4.1.5 type w iocon registers (these pins are otherwise the same as type d, but include a selectable input glitch filter, and default to pull-down/pull-up disabled). . . . . . . . . . . . . . 140 chapter 8: lpc408x/407x gpio 8.1 basic configuration . . . . . . . . . . . . . . . . . . . . 142 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.2.1 digital i/o ports . . . . . . . . . . . . . . . . . . . . . . . 142 8.2.2 interrupt generating digital ports . . . . . . . . . 142 8.3 applications. . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.4 pin description . . . . . . . . . . . . . . . . . . . . . . . 143
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 928 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 8.5 register description . . . . . . . . . . . . . . . . . . . 144 8.5.1 gpio port registers. . . . . . . . . . . . . . . . . . . . 146 8.5.1.1 gpio port direction register . . . . . . . . . . . . . 146 8.5.1.2 fast gpio port mask register . . . . . . . . . . . 146 8.5.1.3 gpio port pin value register . . . . . . . . . . . . 146 8.5.1.4 gpio port output set register . . . . . . . . . . . 147 8.5.1.5 gpio port output clear register . . . . . . . . . . 148 8.5.2 gpio interrupt registers . . . . . . . . . . . . . . . . 149 8.5.2.1 gpio overall interrupt status register . . . . . 149 8.5.2.2 gpio interrupt status for port 0 rising edge interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.2.3 gpio interrupt status for port 0 falling edge interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.5.2.4 gpio interrupt clear register for port 0 . . . . 152 8.5.2.5 gpio interrupt enable for port 0 rising edge 153 8.5.2.6 gpio interrupt enable for port 0 falling edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 8.5.2.7 gpio interrupt status for port 2 rising edge interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 8.5.2.8 gpio interrupt status for port 2 falling edge interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.5.2.9 gpio interrupt clear register for port 2 . . . . 157 8.5.2.10 gpio interrupt enable for port 2 rising edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8.5.2.11 gpio interrupt enable for port 2 falling edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.6 gpio usage notes . . . . . . . . . . . . . . . . . . . . . 160 8.6.1 example: an instantaneous output of 0s and 1s on a gpio port . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.6.2 writing to fioset/fioclr vs. fiopin . . . . 160 chapter 9: lpc408x/407x external memory controller (emc) 9.1 how to read this chapter . . . . . . . . . . . . . . . . 161 9.2 basic configuration . . . . . . . . . . . . . . . . . . . . 162 9.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 9.5 emc functional description . . . . . . . . . . . . . 164 9.5.1 ahb slave register interface . . . . . . . . . . . . . 165 9.5.2 ahb slave memory interface . . . . . . . . . . . . 165 9.5.2.1 memory transaction endianness. . . . . . . . . . 165 9.5.2.2 memory transaction size. . . . . . . . . . . . . . . . 165 9.5.2.3 write protected memory areas . . . . . . . . . . . 165 9.5.3 pad interface . . . . . . . . . . . . . . . . . . . . . . . . 165 9.5.4 data buffers . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.5.4.1 write buffers . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.5.4.2 read buffers . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.5.5 memory controller state machine . . . . . . . . . 167 9.5.6 timing control with programmable delay elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.6 low-power operation. . . . . . . . . . . . . . . . . . . 168 9.6.1 low-power sdram deep-sleep mode. . . . . 168 9.6.2 low-power sdram partial array refresh . . . 168 9.7 memory bank select . . . . . . . . . . . . . . . . . . . 169 9.8 emc reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9.9 address shift mode . . . . . . . . . . . . . . . . . . . . 170 9.10 memory mapped i/o and burst disable . . . . 170 9.11 using the emc with sdram . . . . . . . . . . . . . 171 9.11.1 mode register setup . . . . . . . . . . . . . . . . . . . 171 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 9.12 pin description . . . . . . . . . . . . . . . . . . . . . . . . 173 9.13 register description . . . . . . . . . . . . . . . . . . . 174 9.13.1 emc control register . . . . . . . . . . . . . . . . . . 176 9.13.2 emc status register . . . . . . . . . . . . . . . . . . . 177 9.13.3 emc configuration register . . . . . . . . . . . . . 177 9.13.4 dynamic memory control register . . . . . . . . 178 9.13.5 dynamic memory refresh timer register . . 179 9.13.6 dynamic memory read configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.13.7 dynamic memory precharge command period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.13.8 dynamic memory active to precharge command period register . . . . . . . . . . . . . . . . . . . . . . . 181 9.13.9 dynamic memory self-refresh exit time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 9.13.10 dynamic memory last data out to active time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9.13.11 dynamic memory data-in to active command time register . . . . . . . . . . . . . . . . . . . . . . . . 182 9.13.12 dynamic memory write recovery time register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.13.13 dynamic memory active to active command period register . . . . . . . . . . . . . . . . . . . . . . . 183 9.13.14 dynamic memory auto-refresh period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9.13.15 dynamic memory exit self-refresh register 184 9.13.16 dynamic memory active bank a to active bank b time register . . . . . . . . . . . . . . . . . . . . . . . . 185 9.13.17 dynamic memory load mode register to active command time . . . . . . . . . . . . . . . . . . . . . . 185 9.13.18 static memory extended wait register . . . . 186 9.13.19 dynamic memory configuration registers . . 187 9.13.20 dynamic memory ras & cas delay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.13.21 static memory configuration registers . . . . 191 9.13.22 static memory write enable delay registers 192 9.13.23 static memory output enable delay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 9.13.24 static memory read delay registers . . . . . . 193 9.13.25 static memory page mode read delay registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 9.13.26 static memory write delay registers . . . . . . 194 9.13.27 static memory turn round delay registers . 195 9.14 external memory interface . . . . . . . . . . . . . . 196 9.14.1 32-bit wide memory bank connection . . . . . 196 9.14.2 16-bit wide memory bank connection . . . . . 197 9.14.3 8-bit wide memory bank connection . . . . . . 198 9.14.4 memory configuration example . . . . . . . . . . 199
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 929 of 942 nxp semiconductors UM10562 chapter 41: supplementary information chapter 10: lpc408x/407x ethernet 10.1 basic configuration . . . . . . . . . . . . . . . . . . . . 200 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 10.4 architecture and operation . . . . . . . . . . . . . . 202 10.5 dma engine functions . . . . . . . . . . . . . . . . . . 203 10.6 overview of dma operation . . . . . . . . . . . . . 203 10.7 ethernet packet . . . . . . . . . . . . . . . . . . . . . . . 204 10.8 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.8.1 partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.8.2 example phy devices . . . . . . . . . . . . . . . . . 206 10.9 pin description . . . . . . . . . . . . . . . . . . . . . . . . 207 10.10 register description . . . . . . . . . . . . . . . . . . . 208 10.10.1 ethernet mac register definitions . . . . . . . . . 210 10.10.1.1 mac configuration register 1 . . . . . . . . . . . 210 10.10.1.2 mac configuration register 2 . . . . . . . . . . . 211 10.10.1.3 back-to-back inter-packet-gap register . . . 212 10.10.1.4 non back-to-back inter-packet-gap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.10.1.5 collision window / retry register . . . . . . . . 213 10.10.1.6 maximum frame register . . . . . . . . . . . . . . 213 10.10.1.7 phy support register . . . . . . . . . . . . . . . . . 213 10.10.1.8 test register . . . . . . . . . . . . . . . . . . . . . . . . 214 10.10.1.9 mii mgmt configuration register . . . . . . . . . 214 10.10.1.10 mii mgmt command register . . . . . . . . . . . 215 10.10.1.11 mii mgmt address register . . . . . . . . . . . . 215 10.10.1.12 mii mgmt write data register . . . . . . . . . . 216 10.10.1.13 mii mgmt read data register . . . . . . . . . . 216 10.10.1.14 mii mgmt indicators register . . . . . . . . . . . 216 10.10.1.15 station address 0 register . . . . . . . . . . . . . 217 10.10.1.16 station address 1 register . . . . . . . . . . . . . 217 10.10.1.17 station address 2 register . . . . . . . . . . . . . 217 10.10.2 control register definitions . . . . . . . . . . . . . . 218 10.10.2.1 command register . . . . . . . . . . . . . . . . . . . 218 10.10.2.2 status register . . . . . . . . . . . . . . . . . . . . . . 218 10.10.2.3 receive descriptor base address register . 219 10.10.2.4 receive status base address register . . . . 219 10.10.2.5 receive number of descriptors register . . . 219 10.10.2.6 receive produce index register . . . . . . . . . 219 10.10.2.7 receive consume index register . . . . . . . . 220 10.10.2.8 transmit descriptor base address register 220 10.10.2.9 transmit status base address register . . . 220 10.10.2.10 transmit number of descriptors register . 220 10.10.2.11 transmit produce index register . . . . . . . . 221 10.10.2.12 transmit consume index register . . . . . . . 221 10.10.2.13 transmit status vector 0 register . . . . . . . 221 10.10.2.14 transmit status vector 1 register . . . . . . . 223 10.10.2.15 receive status vector register . . . . . . . . . 224 10.10.2.16 flow control counter register . . . . . . . . . 225 10.10.2.17 flow control status register . . . . . . . . . . . 225 10.10.3 receive filter register definitions . . . . . . . . . 226 10.10.3.1 receive filter control register . . . . . . . . . . 226 10.10.3.2 receive filter wol status register . . . . . . . 226 10.10.3.3 receive filter wol clear register. . . . . . . . 227 10.10.3.4 hash filter table lsbs register . . . . . . . . . 227 10.10.3.5 hash filter table msbs register . . . . . . . . . 227 10.10.4 module control register definitions . . . . . . . . 228 10.10.4.1 interrupt status register . . . . . . . . . . . . . . . 228 10.10.4.2 interrupt enable register . . . . . . . . . . . . . . 229 10.10.4.3 interrupt clear register . . . . . . . . . . . . . . . . 229 10.10.4.4 interrupt set register . . . . . . . . . . . . . . . . . 230 10.10.4.5 power-down register . . . . . . . . . . . . . . . . . 230 10.11 descriptor and status formats . . . . . . . . . . . 231 10.11.1 receive descriptors and statuses . . . . . . . . 231 10.11.2 transmit descriptors and statuses . . . . . . . . 234 10.12 ethernet block functional description. . . . . 237 10.12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 10.12.2 ahb interface. . . . . . . . . . . . . . . . . . . . . . . . 237 10.13 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.13.1 direct memory access (dma) . . . . . . . . . . . 239 10.13.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . 241 10.13.3 transmit process . . . . . . . . . . . . . . . . . . . . . 243 10.13.4 receive process . . . . . . . . . . . . . . . . . . . . . 249 10.13.5 transmission retry . . . . . . . . . . . . . . . . . . . . 255 10.13.6 status hash crc calculations . . . . . . . . . . . 255 10.13.7 duplex modes . . . . . . . . . . . . . . . . . . . . . . . 256 10.13.8 iee 802.3/clause 31 flow control. . . . . . . . . 256 10.13.9 half-duplex mode backpressure . . . . . . . . . 258 10.13.10 receive filtering . . . . . . . . . . . . . . . . . . . . . . 259 10.13.11 power management. . . . . . . . . . . . . . . . . . . 261 10.13.12 wake-up on lan . . . . . . . . . . . . . . . . . . . . . 262 10.13.13 enabling and disabling receive and transmit 263 10.13.14 transmission padding and crc . . . . . . . . . 265 10.13.15 huge frames and frame length checking . . . 266 10.13.16 statistics counters . . . . . . . . . . . . . . . . . . . . 266 10.13.17 mac status vectors . . . . . . . . . . . . . . . . . . . 266 10.13.18 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 10.13.19 ethernet errors . . . . . . . . . . . . . . . . . . . . . . . 268 10.14 ahb bandwidth . . . . . . . . . . . . . . . . . . . . . . . 269 10.14.1 dma access. . . . . . . . . . . . . . . . . . . . . . . . . 269 10.14.2 types of cpu access. . . . . . . . . . . . . . . . . . 270 10.14.3 overall bandwidth . . . . . . . . . . . . . . . . . . . . 270 10.15 crc calculation. . . . . . . . . . . . . . . . . . . . . . . 272 chapter 11: lpc408x/407x lcd controller 11.1 how to read this chapter . . . . . . . . . . . . . . . . 274 11.2 basic configuration . . . . . . . . . . . . . . . . . . . . 274 11.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 11.4.1 programmable parameters . . . . . . . . . . . . . . 275 11.4.2 hardware cursor support . . . . . . . . . . . . . . . 276 11.4.3 types of lcd panels supported. . . . . . . . . . 276 11.4.4 tft panels. . . . . . . . . . . . . . . . . . . . . . . . . . 276 11.4.5 color stn panels. . . . . . . . . . . . . . . . . . . . . 277 11.4.6 monochrome stn panels . . . . . . . . . . . . . . 277 11.5 pin description . . . . . . . . . . . . . . . . . . . . . . . 278
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 930 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 11.5.1 signal usage . . . . . . . . . . . . . . . . . . . . . . . . . 278 11.5.1.1 signals used for single panel stn displays . 278 11.5.1.2 signals used for dual panel stn displays . . 278 11.5.1.3 signals used for tft displays . . . . . . . . . . . 279 11.6 lcd controller functional description . . . . . 280 11.6.1 ahb interfaces . . . . . . . . . . . . . . . . . . . . . . . 281 11.6.1.1 amba ahb slave interface . . . . . . . . . . . . . . 281 11.6.1.2 amba ahb master interface . . . . . . . . . . . . 281 11.6.2 dual dma fifos and associated control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 11.6.3 pixel serializer . . . . . . . . . . . . . . . . . . . . . . . 282 11.6.4 ram palette . . . . . . . . . . . . . . . . . . . . . . . . . 286 11.6.5 hardware cursor . . . . . . . . . . . . . . . . . . . . . . 288 11.6.5.1 cursor operation . . . . . . . . . . . . . . . . . . . . . . 288 11.6.5.2 cursor sizes . . . . . . . . . . . . . . . . . . . . . . . . . 288 11.6.5.3 cursor movement . . . . . . . . . . . . . . . . . . . . . 289 11.6.5.4 cursor xy positioning . . . . . . . . . . . . . . . . . . 289 11.6.5.5 cursor clipping . . . . . . . . . . . . . . . . . . . . . . . 290 11.6.5.6 cursor image format . . . . . . . . . . . . . . . . . . . 290 11.6.6 gray scaler . . . . . . . . . . . . . . . . . . . . . . . . . . 293 11.6.7 upper and lower panel formatters . . . . . . . . 293 11.6.8 panel clock generator . . . . . . . . . . . . . . . . . . 294 11.6.9 timing controller . . . . . . . . . . . . . . . . . . . . . . 294 11.6.10 stn and tft data select . . . . . . . . . . . . . . . 294 11.6.10.1 stn displays . . . . . . . . . . . . . . . . . . . . . . . . 294 11.6.10.2 tft displays . . . . . . . . . . . . . . . . . . . . . . . . . 294 11.6.11 interrupt generation . . . . . . . . . . . . . . . . . . . 294 11.6.11.1 master bus error interrupt . . . . . . . . . . . . . . . 295 11.6.11.2 vertical compare interrupt. . . . . . . . . . . . . . . 295 11.6.11.2.1 next base address update interrupt . . . . . . 295 11.6.11.2.2 fifo underflow interrupt . . . . . . . . . . . . . . . 295 11.6.12 lcd power-up and power-down sequence . 295 11.7 register description . . . . . . . . . . . . . . . . . . . 297 11.7.1 horizontal timing register . . . . . . . . . . . . . . 298 11.7.1.1 horizontal timing restrictions . . . . . . . . . . . . 298 11.7.2 vertical timing register . . . . . . . . . . . . . . . . 299 11.7.3 clock and signal polarity register . . . . . . . . 300 11.7.4 line end control register . . . . . . . . . . . . . . 301 11.7.5 upper panel frame base address register . 302 11.7.6 lower panel frame base address register . 302 11.7.7 lcd control register . . . . . . . . . . . . . . . . . . 303 11.7.8 interrupt mask register . . . . . . . . . . . . . . . . 305 11.7.9 raw interrupt status register . . . . . . . . . . . 306 11.7.10 masked interrupt status register . . . . . . . . . 306 11.7.11 interrupt clear register . . . . . . . . . . . . . . . . 307 11.7.12 upper panel current address register . . . . 307 11.7.13 lower panel current address register. . . . . 307 11.7.14 color palette registers . . . . . . . . . . . . . . . . . 308 11.7.15 cursor image registers . . . . . . . . . . . . . . . . 308 11.7.16 cursor control register. . . . . . . . . . . . . . . . . 309 11.7.17 cursor configuration register. . . . . . . . . . . . 309 11.7.18 cursor palette register 0 . . . . . . . . . . . . . . . 310 11.7.19 cursor palette register 1 . . . . . . . . . . . . . . . 310 11.7.20 cursor xy position register . . . . . . . . . . . . . . 311 11.7.21 cursor clip position register . . . . . . . . . . . . . 311 11.7.22 cursor interrupt mask register . . . . . . . . . . . 312 11.7.23 cursor interrupt clear register . . . . . . . . . . . 312 11.7.24 cursor raw interrupt status register . . . . . . 312 11.7.25 cursor masked interrupt status register . . . 313 11.8 lcd timing diagrams . . . . . . . . . . . . . . . . . . 314 11.9 lcd panel signal usage . . . . . . . . . . . . . . . . 317 chapter 12: lpc408x/407x usb device controller 12.1 how to read this chapter . . . . . . . . . . . . . . . . 320 12.2 basic configuration . . . . . . . . . . . . . . . . . . . . 320 12.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 320 12.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 12.5 fixed endpoint configuration . . . . . . . . . . . . 321 12.6 functional description . . . . . . . . . . . . . . . . . 323 12.6.1 analog transceiver . . . . . . . . . . . . . . . . . . . . 323 12.6.2 serial interface engine (sie) . . . . . . . . . . . . 323 12.6.3 endpoint ram (ep_ram) . . . . . . . . . . . . . . 323 12.6.4 ep_ram access control . . . . . . . . . . . . . . . . 324 12.6.5 dma engine and bus master interface . . . . . 324 12.6.6 register interface . . . . . . . . . . . . . . . . . . . . . 324 12.6.7 softconnect . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.6.8 goodlink . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.7 operational overview . . . . . . . . . . . . . . . . . . 325 12.8 pin description . . . . . . . . . . . . . . . . . . . . . . . . 325 12.9 clocking and power management . . . . . . . . 326 12.9.1 power requirements . . . . . . . . . . . . . . . . . . . 326 12.9.2 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 12.9.3 power management support . . . . . . . . . . . . 326 12.9.4 remote wake-up . . . . . . . . . . . . . . . . . . . . . 327 12.10 register description . . . . . . . . . . . . . . . . . . . 328 12.10.1 port select register . . . . . . . . . . . . . . . . . . . . 330 12.10.1.1 usb port select register . . . . . . . . . . . . . . . 330 12.10.2 device interrupt registers . . . . . . . . . . . . . . . 330 12.10.2.1 usb device interrupt status register . . . . . 330 12.10.2.2 usb device interrupt enable register . . . . . 331 12.10.2.3 usb device interrupt clear register . . . . . . 332 12.10.2.4 usb device interrupt set register . . . . . . . . 333 12.10.2.5 usb device interrupt priority register . . . . . 334 12.10.3 endpoint interrupt registers . . . . . . . . . . . . . 335 12.10.3.1 usb endpoint interrupt status register . . . . 335 12.10.3.2 usb endpoint interrupt enable register . . . 336 12.10.3.3 usb endpoint interrupt clear register . . . . 336 12.10.3.4 usb endpoint interrupt set register. . . . . . . 337 12.10.3.5 usb endpoint interrupt priority register . . . . 337 12.10.4 endpoint realization registers. . . . . . . . . . . . 338 12.10.4.1 ep ram requirements . . . . . . . . . . . . . . . . . 338 12.10.4.2 usb realize endpoint register . . . . . . . . . . 339 12.10.4.3 usb endpoint index register . . . . . . . . . . . . 340 12.10.4.4 usb maxpacketsize register . . . . . . . . . . . 340 12.10.5 usb transfer registers . . . . . . . . . . . . . . . . . 341 12.10.5.1 usb receive data register . . . . . . . . . . . . . 341 12.10.5.2 usb receive packet length register . . . . . 341 12.10.5.3 usb transmit data register . . . . . . . . . . . . . 342 12.10.5.4 usb transmit packet length register . . . . . 342 12.10.5.5 usb control register . . . . . . . . . . . . . . . . . . 343
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 931 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 12.10.6 sie command code registers . . . . . . . . . . . . 344 12.10.6.1 usb command code register . . . . . . . . . . . 344 12.10.6.2 usb command data register . . . . . . . . . . . 344 12.10.7 dma registers . . . . . . . . . . . . . . . . . . . . . . . . 345 12.10.7.1 usb dma request status register . . . . . . . . 345 12.10.7.2 usb dma request clear register . . . . . . . . 346 12.10.7.3 usb dma request set register . . . . . . . . . . 346 12.10.7.4 usb udca head register . . . . . . . . . . . . . . 347 12.10.7.5 usb ep dma status register . . . . . . . . . . . . 347 12.10.7.6 usb ep dma enable register . . . . . . . . . . . 347 12.10.7.7 usb ep dma disable register . . . . . . . . . . . 348 12.10.7.8 usb dma interrupt status register . . . . . . . 348 12.10.7.9 usb dma interrupt enable register . . . . . . . 349 12.10.7.10 usb end of transfer interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.10.7.11 usb end of transfer interrupt clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 12.10.7.12 usb end of transfer interrupt set register . 350 12.10.7.13 usb new dd request interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.10.7.14 usb new dd request interrupt clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 12.10.7.15 usb new dd request interrupt set register 350 12.10.7.16 usb system error interrupt status register 351 12.10.7.17 usb system error interrupt clear register . 351 12.10.7.18 usb system error interrupt set register . . 351 12.10.8 clock control registers . . . . . . . . . . . . . . . . . 352 12.10.8.1 usb clock control register . . . . . . . . . . . . . 352 12.10.8.2 usb clock status register . . . . . . . . . . . . . . 352 12.11 interrupt handling . . . . . . . . . . . . . . . . . . . . . 353 slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . .353 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . .353 12.12 serial interface engine command description . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 12.12.1 set address (command: 0xd0, data: write 1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 12.12.2 configure device (command: 0xd8, data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 12.12.3 set mode (command: 0xf3, data: write 1 byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 12.12.4 read current frame number (command: 0xf5, data: read 1 or 2 bytes) . . . . . . . . . . . . . . . . 359 12.12.5 read test register (command: 0xfd, data: read 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 12.12.6 set device status (command: 0xfe, data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12.12.7 get device status (command: 0xfe, data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 12.12.8 get error code (command: 0xff, data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 12.12.9 read error status (command: 0xfb, data: read 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 12.12.10 select endpoint (command: 0x00 - 0x1f, data: read 1 byte (optional)) . . . . . . . . . . . . . . . . . 363 12.12.11 select endpoint/clear interrupt (command: 0x40 - 0x5f, data: read 1 byte) . . . . . . . . . . 364 12.12.12 set endpoint status (command: 0x40 - 0x55, data: write 1 byte (optional)). . . . . . . . . . . . . 364 12.12.13 clear buffer (command: 0xf2, data: read 1 byte (optional)). . . . . . . . . . . . . . . . . . . . . . . . . . . 365 12.12.14 validate buffer (command: 0xfa, data: none) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 12.13 usb device controller initialization . . . . . . . 366 12.14 slave mode operation. . . . . . . . . . . . . . . . . . 368 12.14.1 interrupt generation . . . . . . . . . . . . . . . . . . . 368 12.14.2 data transfer for out endpoints . . . . . . . . . 368 12.14.3 data transfer for in endpoints . . . . . . . . . . . 368 12.15 dma operation. . . . . . . . . . . . . . . . . . . . . . . . 370 12.15.1 transfer terminology . . . . . . . . . . . . . . . . . . 370 12.15.2 usb device communication area. . . . . . . . . 370 12.15.3 triggering the dma engine . . . . . . . . . . . . . 371 12.15.4 the dma descriptor . . . . . . . . . . . . . . . . . . . 371 12.15.4.1 next_dd_pointer . . . . . . . . . . . . . . . . . . . . . 372 12.15.4.2 dma_mode . . . . . . . . . . . . . . . . . . . . . . . . . 373 12.15.4.3 next_dd_valid . . . . . . . . . . . . . . . . . . . . . . . 373 12.15.4.4 isochronous_endpoint . . . . . . . . . . . . . . . . . 373 12.15.4.5 max_packet_size . . . . . . . . . . . . . . . . . . . . . 373 12.15.4.6 dma_buffer_length . . . . . . . . . . . . . . . . . . . 373 12.15.4.7 dma_buffer_start_addr . . . . . . . . . . . . . . . . 373 12.15.4.8 dd_retired . . . . . . . . . . . . . . . . . . . . . . . . . . 373 12.15.4.9 dd_status . . . . . . . . . . . . . . . . . . . . . . . . . . 373 12.15.4.10 packet_valid . . . . . . . . . . . . . . . . . . . . . . . . 374 12.15.4.11 ls_byte_extracted . . . . . . . . . . . . . . . . . . . 374 12.15.4.12 ms_byte_extracted. . . . . . . . . . . . . . . . . . . 374 12.15.4.13 present_dma_count. . . . . . . . . . . . . . . . . . 374 12.15.4.14 message_length_position . . . . . . . . . . . . . . 374 12.15.4.15 isochronous_packetsize_memory_address 374 12.15.5 non-isochronous endpoint operation . . . . . . 375 12.15.5.1 setting up dma transfers. . . . . . . . . . . . . . . 375 12.15.5.2 finding dma descriptor. . . . . . . . . . . . . . . . 375 12.15.5.3 transferring the data . . . . . . . . . . . . . . . . . . 375 12.15.5.4 optimizing descriptor fetch . . . . . . . . . . . . . 375 12.15.5.5 ending the packet transfer . . . . . . . . . . . . . . 376 12.15.5.6 no_packet dd . . . . . . . . . . . . . . . . . . . . . . . 376 12.15.6 isochronous endpoint operation. . . . . . . . . . 376 12.15.6.1 setting up dma transfers. . . . . . . . . . . . . . . 376 12.15.6.2 finding the dma descriptor. . . . . . . . . . . . . 377 12.15.6.3 transferring the data . . . . . . . . . . . . . . . . . . 377 out endpoints. . . . . . . . . . . . . . . . . . . . . . . . 377 in endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.15.6.4 dma descriptor completion . . . . . . . . . . . . . 377 12.15.6.5 isochronous out endpoint operation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 12.15.7 auto length transfer extraction (atle) mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 out transfers in atle mode. . . . . . . . . . . . . 378 in transfers in atle mode. . . . . . . . . . . . . . . 380 12.15.7.1 setting up the dma transfer. . . . . . . . . . . . . 380 12.15.7.2 finding the dma descriptor. . . . . . . . . . . . . 380 12.15.7.3 transferring the data . . . . . . . . . . . . . . . . . . 380 out endpoints. . . . . . . . . . . . . . . . . . . . . . . . 380 in endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 380 12.15.7.4 ending the packet transfer . . . . . . . . . . . . . . 381 out endpoints. . . . . . . . . . . . . . . . . . . . . . . . 381 in endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . 381
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 932 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 12.16 double buffered endpoint operation . . . . . . 382 12.16.1 bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . 382 12.16.2 isochronous endpoints . . . . . . . . . . . . . . . . . 383 chapter 13: lpc408x/407x usb host controller 13.1 how to read this chapter . . . . . . . . . . . . . . . . 385 13.2 basic configuration . . . . . . . . . . . . . . . . . . . . 385 13.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.3.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 13.3.2 architecture . . . . . . . . . . . . . . . . . . . . . . . . . 387 13.4 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 13.4.1 pin description . . . . . . . . . . . . . . . . . . . . . . . 388 13.4.1.1 usb host usage note . . . . . . . . . . . . . . . . . . 389 13.4.2 software interface . . . . . . . . . . . . . . . . . . . . 389 13.4.2.1 register map . . . . . . . . . . . . . . . . . . . . . . . . 389 13.4.2.2 usb host register definitions . . . . . . . . . . . 390 chapter 14: lpc408x/407x usb otg controller 14.1 how to read this chapter . . . . . . . . . . . . . . . . 391 14.2 basic configuration . . . . . . . . . . . . . . . . . . . . 391 14.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 391 14.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 14.5 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 392 14.6 modes of operation . . . . . . . . . . . . . . . . . . . . 392 14.7 pin configuration . . . . . . . . . . . . . . . . . . . . . . 393 14.7.1 using port u1 for otg operation . . . . . . . . . 394 14.7.2 using both ports u1 and u2 for host operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 14.7.3 using u1 for host operation and u2 for device operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 14.8 register description . . . . . . . . . . . . . . . . . . . 398 14.8.1 otg interrupt status register . . . . . . . . . . . 398 14.8.2 otg interrupt enable register . . . . . . . . . . 399 14.8.3 otg interrupt set register . . . . . . . . . . . . . 399 14.8.4 otg interrupt clear register . . . . . . . . . . . . 399 14.8.5 otg status and control register . . . . . . . . 401 14.8.6 otg timer register . . . . . . . . . . . . . . . . . . 402 14.8.7 i2c receive register . . . . . . . . . . . . . . . . . . 402 14.8.8 i2c transmit register. . . . . . . . . . . . . . . . . . 403 14.8.9 i2c status register. . . . . . . . . . . . . . . . . . . . 403 14.8.10 i2c control register . . . . . . . . . . . . . . . . . . . 405 14.8.11 i2c clock high register . . . . . . . . . . . . . . . 406 14.8.12 i2c clock low register . . . . . . . . . . . . . . . 406 14.8.13 otg clock control register . . . . . . . . . . . . 407 14.8.14 otg clock status register . . . . . . . . . . . . . 408 14.8.15 interrupt handling . . . . . . . . . . . . . . . . . . . . . 409 14.9 hnp support . . . . . . . . . . . . . . . . . . . . . . . . . 410 14.9.1 b-device: peripheral to host switching . . . . . . 411 remove d+ pull-up . . . . . . . . . . . . . . . . . . . . 413 add d+ pull-up . . . . . . . . . . . . . . . . . . . . . . . . 414 14.9.2 a-device: host to peripheral hnp switching. 414 set bdis_acon_en in external otg transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 clear bdis_acon_en in external otg trans- ceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 discharge v bus . . . . . . . . . . . . . . . . . . . . . . . 417 load and enable otg timer . . . . . . . . . . . . . 418 stop otg timer . . . . . . . . . . . . . . . . . . . . . . . 418 suspend host on port 1 . . . . . . . . . . . . . . . . . 418 14.10 clocking and power management. . . . . . . . 419 14.10.1 device clock request signals . . . . . . . . . . . . 421 14.10.1.1 host clock request signals . . . . . . . . . . . . . . 421 14.10.2 power-down mode support . . . . . . . . . . . . . 421 14.11 usb otg controller initialization . . . . . . . . 422 chapter 15: lpc408x/407x spi flash interface (spifi) 15.1 basic configuration . . . . . . . . . . . . . . . . . . . . 423 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 15.3 general description . . . . . . . . . . . . . . . . . . . . 424 15.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 424 15.5 supported devices. . . . . . . . . . . . . . . . . . . . . 425 15.6 spifi hardware . . . . . . . . . . . . . . . . . . . . . . . . 426 15.7 spifi software library . . . . . . . . . . . . . . . . . . 426 15.7.1 spifi function allocation . . . . . . . . . . . . . . . . 426 15.7.2 spifi function calls . . . . . . . . . . . . . . . . . . . . 427 15.7.2.1 calling the spifi driver. . . . . . . . . . . . . . . . . 427 15.7.2.2 spifi initialization call spifi_init. . . . . . . . . . . 427 parameter0 obj . . . . . . . . . . . . . . . . . . . . . . . .427 parameter1 cshigh . . . . . . . . . . . . . . . . . . . . .427 parameter2 options . . . . . . . . . . . . . . . . . . . .427 parameter3 mhz . . . . . . . . . . . . . . . . . . . . . .428 return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 15.7.2.3 spifi program call spifi_program . . . . . . . . . 429 parameter0 obj . . . . . . . . . . . . . . . . . . . . . . . 429 parameter1 source . . . . . . . . . . . . . . . . . . . . 429 parameter2 opers . . . . . . . . . . . . . . . . . . . . . 429 return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 15.7.2.4 spifi erase call spifi_erase . . . . . . . . . . . . . 430 parameter0 obj . . . . . . . . . . . . . . . . . . . . . . . 430 parameter1 opers . . . . . . . . . . . . . . . . . . . . . 430 return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 15.7.2.5 spifi operands for program and erase . . . 431 15.7.2.6 address operands and checking . . . . . . . . . 433 15.7.2.7 protection. . . . . . . . . . . . . . . . . . . . . . . . . . . 433
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 933 of 942 nxp semiconductors UM10562 chapter 41: supplementary information chapter 16: lpc408x/407x sd card interface 16.1 how to read this chapter . . . . . . . . . . . . . . . . 434 16.2 basic configuration . . . . . . . . . . . . . . . . . . . . 434 16.3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 434 16.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 16.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 435 16.6 functional overview . . . . . . . . . . . . . . . . . . . 435 16.6.1 secure digital memory card . . . . . . . . . . . . . 435 16.6.1.1 secure digital memory card bus signals . . . . 435 16.6.2 multimedia card . . . . . . . . . . . . . . . . . . . . . . 435 16.6.3 sd card interface details. . . . . . . . . . . . . . . . 436 16.6.3.1 adapter register block. . . . . . . . . . . . . . . . . . 437 16.6.3.2 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . 437 16.6.3.3 command path . . . . . . . . . . . . . . . . . . . . . . . 438 16.6.3.4 command path state machine . . . . . . . . . . . 438 16.6.3.5 command format . . . . . . . . . . . . . . . . . . . . . 439 16.6.3.6 data path . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 16.6.3.7 data path state machine. . . . . . . . . . . . . . . . 441 16.6.3.8 data counter . . . . . . . . . . . . . . . . . . . . . . . . . 442 16.6.3.9 bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.6.3.10 crc token status. . . . . . . . . . . . . . . . . . . . . 443 16.6.3.11 status flags . . . . . . . . . . . . . . . . . . . . . . . . . . 444 16.6.3.12 crc generator . . . . . . . . . . . . . . . . . . . . . . . 444 16.6.3.13 data fifo . . . . . . . . . . . . . . . . . . . . . . . . . . 444 16.6.3.14 transmit fifo . . . . . . . . . . . . . . . . . . . . . . . 445 16.6.3.15 receive fifo. . . . . . . . . . . . . . . . . . . . . . . . 445 16.6.3.16 apb interfaces . . . . . . . . . . . . . . . . . . . . . . . 446 16.6.3.17 interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . 446 16.7 register description . . . . . . . . . . . . . . . . . . . 447 16.7.1 power control register . . . . . . . . . . . . . . . . 447 16.7.2 clock control register . . . . . . . . . . . . . . . . . 448 16.7.3 argument register . . . . . . . . . . . . . . . . . . . . 448 16.7.4 command register . . . . . . . . . . . . . . . . . . . 449 16.7.5 command response register. . . . . . . . . . . 449 16.7.6 response registers. . . . . . . . . . . . . . . . . . . 449 16.7.7 data timer register . . . . . . . . . . . . . . . . . . . 450 16.7.8 data length register . . . . . . . . . . . . . . . . . . 450 16.7.9 data control register . . . . . . . . . . . . . . . . . 451 16.7.10 data counter register . . . . . . . . . . . . . . . . . 451 16.7.11 status register. . . . . . . . . . . . . . . . . . . . . . . 452 16.7.12 clear register . . . . . . . . . . . . . . . . . . . . . . . 453 16.7.13 interrupt mask registers . . . . . . . . . . . . . . . 454 16.7.14 fifo counter register. . . . . . . . . . . . . . . . . 454 16.7.15 data fifo register . . . . . . . . . . . . . . . . . . . 455 chapter 17: lpc408x/407x uart1 17.1 basic configuration . . . . . . . . . . . . . . . . . . . . 456 17.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 17.3 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 459 17.5 register description . . . . . . . . . . . . . . . . . . . 460 17.5.1 uart1 receiver buffer register . . . . . . . . . 461 17.5.2 uart1 transmitter holding register . . . . . 461 17.5.3 uart1 divisor latch lsb and msb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 17.5.4 uart1 interrupt enable register . . . . . . . . 463 17.5.5 uart1 interrupt identification register . . . . 464 17.5.6 uart1 fifo control register . . . . . . . . . . . 467 17.5.6.1 dma operation . . . . . . . . . . . . . . . . . . . . . . . 467 uart receiver dma . . . . . . . . . . . . . . . . . . . .467 uart transmitter dma . . . . . . . . . . . . . . . . . .468 17.5.7 uart1 line control register . . . . . . . . . . . 469 17.5.8 uart1 modem control register . . . . . . . . . 470 17.5.9 auto-flow control . . . . . . . . . . . . . . . . . . . . . . 470 17.5.9.1 auto-rts . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.5.9.2 auto-cts . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.5.10 uart1 line status register. . . . . . . . . . . . . 473 17.5.11 uart1 modem status register . . . . . . . . . 474 17.5.12 uart1 scratch pad register . . . . . . . . . . . 476 17.5.13 uart1 auto-baud control register . . . . . . 476 17.5.14 auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 477 17.5.15 auto-baud modes. . . . . . . . . . . . . . . . . . . . . 478 17.5.16 uart1 fractional divider register . . . . . . . 480 17.5.16.1 baud rate calculation . . . . . . . . . . . . . . . . . . 481 17.5.16.1.1 example 1: pclk = 14.7456 mhz, br = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 17.5.16.1.2 example 2: pclk = 12 mhz, br = 115200 482 17.5.17 uart1 transmit enable register . . . . . . . . 483 17.5.18 uart1 rs485 control register . . . . . . . . . . 484 17.5.19 uart1 rs-485 address match register . . . 484 17.5.20 uart1 rs-485 delay value register . . . . . . 485 17.5.21 rs-485/eia-485 modes of operation . . . . . . 485 rs-485/eia-485 normal multidrop mode (nmm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 rs-485/eia-485 auto address detection (aad) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 rs-485/eia-485 auto direction control. . . . . 486 rs485/eia-485 driver delay time. . . . . . . . . . 486 rs485/eia-485 output inversion . . . . . . . . . . 486 chapter 18: lpc408x/407x uart0/2/3 18.1 how to read this chapter . . . . . . . . . . . . . . . . 487 18.2 basic configuration . . . . . . . . . . . . . . . . . . . . 487 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 18.4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 488 18.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 489 18.6 register description . . . . . . . . . . . . . . . . . . . 490 18.6.1 uartn receiver buffer register . . . . . . . . 491 18.6.2 uartn transmit holding register . . . . . . . 491 18.6.3 uartn divisor latch lsb register . . . . . . . 492 18.6.4 uartn interrupt enable register . . . . . . . . 493 18.6.5 uartn interrupt identification register . . . 494
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 934 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 18.6.6 uartn fifo control register . . . . . . . . . . . 496 18.6.6.1 dma operation . . . . . . . . . . . . . . . . . . . . . . . 496 uart receiver dma . . . . . . . . . . . . . . . . . . . .496 uart transmitter dma . . . . . . . . . . . . . . . . . .496 18.6.7 uartn line control register . . . . . . . . . . . . 497 18.6.8 uartn line status register . . . . . . . . . . . . 498 18.6.9 uartn scratch pad register . . . . . . . . . . . 499 18.6.10 uartn auto-baud control register . . . . . . . 500 18.6.10.1 auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 18.6.10.2 auto-baud modes . . . . . . . . . . . . . . . . . . . . . 501 18.6.11 uartn fractional divider register . . . . . . . 503 18.6.11.1 baud rate calculation . . . . . . . . . . . . . . . . . . 504 18.6.11.1.1 example 1: pclk = 14.7456 mhz, br = 9600. . . . . . . . . . . . . . . . . . . . . . . . . . . 505 18.6.11.1.2 example 2: pclk = 12 mhz, br = 115200 505 18.6.12 uartn transmit enable register . . . . . . . . 506 18.6.13 uartn rs485 control register . . . . . . . . . . 507 18.6.14 uartn rs-485 address match register . . . 507 18.6.15 uartn rs-485 delay value register . . . . . 508 18.6.16 rs-485/eia-485 modes of operation . . . . . . 508 rs-485/eia-485 normal multidrop mode (nmm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 rs-485/eia-485 auto address detection (aad) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 rs-485/eia-485 auto direction control. . . . . 509 rs485/eia-485 driver delay time. . . . . . . . . . 509 rs485/eia-485 output inversion . . . . . . . . . . 509 chapter 19: lpc408x/407x uart4 19.1 how to read this chapter . . . . . . . . . . . . . . . . 510 19.2 basic configuration . . . . . . . . . . . . . . . . . . . . 510 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 19.4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 511 19.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 512 19.6 register description . . . . . . . . . . . . . . . . . . . 513 19.6.1 uart4 receiver buffer register . . . . . . . . . 514 19.6.2 uart4 transmit holding register . . . . . . . . 514 19.6.3 uart4 divisor latch lsb register . . . . . . . 515 19.6.4 uart4 interrupt enable register . . . . . . . . . 516 19.6.5 uart4 interrupt identification register . . . . 517 19.6.6 uart4 fifo control register . . . . . . . . . . . 520 19.6.6.1 dma operation . . . . . . . . . . . . . . . . . . . . . . . 520 uart receiver dma . . . . . . . . . . . . . . . . . . . .520 uart transmitter dma . . . . . . . . . . . . . . . . . .520 19.6.7 uart4 line control register . . . . . . . . . . . . 521 19.6.8 uart4 line status register. . . . . . . . . . . . . 522 19.6.9 uart4 scratch pad register . . . . . . . . . . . 523 19.6.10 uart4 auto-baud control register . . . . . . 524 19.6.10.1 auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 19.6.10.2 auto-baud modes . . . . . . . . . . . . . . . . . . . . . 525 19.6.11 uart4 irda control register . . . . . . . . . . . 527 19.6.12 uart4 fractional divider register . . . . . . . 528 19.6.12.1 baud rate calculation . . . . . . . . . . . . . . . . . . 529 19.6.12.1.1 example 1: pclk = 14.7456 mhz, br = 9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 19.6.12.1.2 example 2: pclk = 12 mhz, br = 115200 530 19.6.13 uart4 oversampling register . . . . . . . . . . 531 19.6.14 uart4 smart card interface control register 532 19.6.14.1 smartcard connection . . . . . . . . . . . . . . . . . 532 19.6.14.2 smartcard setup . . . . . . . . . . . . . . . . . . . . . 532 19.6.15 uart4 rs485 control register . . . . . . . . . . 533 19.6.16 uart4 rs-485 address match register . . . 534 19.6.17 uart4 rs-485 delay value register . . . . . 534 19.6.18 rs-485/eia-485 modes of operation . . . . . . 534 rs-485/eia-485 normal multidrop mode (nmm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 rs-485/eia-485 auto address detection (aad) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 rs-485/eia-485 auto direction control. . . . . 535 rs485/eia-485 driver delay time. . . . . . . . . . 535 rs485/eia-485 output inversion . . . . . . . . . . 535 19.6.19 uart4 synchronous mode control register 536 chapter 20: lpc408x/407x can controller 20.1 basic configuration . . . . . . . . . . . . . . . . . . . . 538 20.2 can controllers . . . . . . . . . . . . . . . . . . . . . . . 538 20.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 20.3.1 general can features . . . . . . . . . . . . . . . . . 538 20.3.2 can controller features . . . . . . . . . . . . . . . . 539 20.3.3 acceptance filter features . . . . . . . . . . . . . . . 539 20.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 539 20.5 can controller architecture . . . . . . . . . . . . . 539 20.5.1 apb interface block (aib) . . . . . . . . . . . . . . 540 20.5.2 interface management logic (iml). . . . . . . . 540 20.5.3 transmit buffers (txb) . . . . . . . . . . . . . . . . . 540 20.5.4 receive buffer (rxb) . . . . . . . . . . . . . . . . . 541 20.5.5 error management logic (eml) . . . . . . . . . 542 20.5.6 bit timing logic (btl) . . . . . . . . . . . . . . . . . 542 20.5.7 bit stream processor (bsp) . . . . . . . . . . . . . 542 20.5.8 can controller self-tests . . . . . . . . . . . . . . . . 542 global self test . . . . . . . . . . . . . . . . . . . . . . . . 543 local self test . . . . . . . . . . . . . . . . . . . . . . . . . 543 20.6 memory map of the can block . . . . . . . . . . 544 20.7 register description . . . . . . . . . . . . . . . . . . . 544 20.7.1 can mode register . . . . . . . . . . . . . . . . . . . 546 20.7.2 can command register . . . . . . . . . . . . . . . 548 20.7.3 can global status register . . . . . . . . . . . . 550 rx error counter . . . . . . . . . . . . . . . . . . . . . . 551 tx error counter. . . . . . . . . . . . . . . . . . . . . . . 552 20.7.4 can interrupt and capture register . . . . . . 552 20.7.5 can interrupt enable register . . . . . . . . . . 556 20.7.6 can bus timing register . . . . . . . . . . . . . . 557 baud rate prescaler . . . . . . . . . . . . . . . . . . . . 557 synchronization jump width . . . . . . . . . . . . . . 558 time segment 1 and time segment 2. . . . . . . 558 20.7.7 can error warning limit register . . . . . . . . 558 20.7.8 can status register . . . . . . . . . . . . . . . . . . 558
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 935 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 20.7.9 can receive frame status register . . . . . . 560 20.7.9.1 id index field . . . . . . . . . . . . . . . . . . . . . . . . . 561 20.7.10 can receive identifier register . . . . . . . . . . 561 20.7.11 can receive data register a . . . . . . . . . . . 561 20.7.12 can receive data register b . . . . . . . . . . . 562 20.7.13 can transmit frame information register . . 562 automatic transmit priority detection. . . . . . . .563 tx dlc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563 20.7.14 can transmit identifier register . . . . . . . . . 564 20.7.15 can transmit data register a . . . . . . . . . . . 564 20.7.16 can transmit data register b . . . . . . . . . . . 564 20.8 can controller operation . . . . . . . . . . . . . . . 565 20.8.1 error handling . . . . . . . . . . . . . . . . . . . . . . . . 565 20.8.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . 565 20.8.3 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 20.8.4 transmit priority . . . . . . . . . . . . . . . . . . . . . . 566 20.9 centralized can registers. . . . . . . . . . . . . . . 566 20.9.1 central transmit status register . . . . . . . . . 566 20.9.2 central receive status register . . . . . . . . . 567 20.9.3 central miscellaneous status register . . . . 567 20.10 global acceptance filter . . . . . . . . . . . . . . . . 567 20.11 acceptance filter modes . . . . . . . . . . . . . . . . 567 20.11.1 acceptance filter off mode . . . . . . . . . . . . . . 568 20.11.2 acceptance filter bypass mode . . . . . . . . . . 568 20.11.3 acceptance filter operating mode . . . . . . . . 568 20.11.4 fullcan mode . . . . . . . . . . . . . . . . . . . . . . . 568 20.12 sections of the id look-up table ram . . . . . 568 20.13 id look-up table ram. . . . . . . . . . . . . . . . . . . 569 20.14 acceptance filter registers . . . . . . . . . . . . . . 571 20.14.1 acceptance filter mode register . . . . . . . . . 571 20.14.2 section configuration registers . . . . . . . . . . . 572 20.14.3 standard frame individual start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.14.4 standard frame group start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 20.14.5 extended frame start address register . . . . 573 20.14.6 extended frame group start address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 20.14.7 end of af tables register . . . . . . . . . . . . . . 573 20.14.8 status registers . . . . . . . . . . . . . . . . . . . . . . . 574 20.14.9 lut error address register . . . . . . . . . . . . . 574 20.14.10 lut error register . . . . . . . . . . . . . . . . . . . . 574 20.14.11 global fullcaninterrupt enable register . . . 575 20.14.12 fullcan interrupt and capture registers . . . 575 20.15 configuration and search algorithm . . . . . . 575 20.15.1 acceptance filter search algorithm . . . . . . . . 575 20.16 fullcan mode . . . . . . . . . . . . . . . . . . . . . . . . 577 20.16.1 fullcan message layout . . . . . . . . . . . . . . . 578 20.16.2 fullcan interrupts . . . . . . . . . . . . . . . . . . . . 581 20.16.2.1 fullcan message interrupt enable bit . . . . . 581 20.16.2.2 message lost bit and can channel number. 582 20.16.2.3 setting the interrupt pending bits (intpnd 63 to 0) 583 20.16.2.4 clearing the interrupt pending bits (intpnd 63 to 0) 583 20.16.2.5 setting the message lost bit of a fullcan message object (msglost 63 to 0). . . . . . . . 583 20.16.2.6 clearing the message lost bit of a fullcan message object (msglost 63 to 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 20.16.3 set and clear mechanism of the fullcan interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 20.16.3.1 scenario 1: normal case, no message lost . 583 20.16.3.2 scenario 2: message lost. . . . . . . . . . . . . . . 584 20.16.3.3 scenario 3: message gets overwritten indicated by semaphore bits . . . . . . . . . . . . . . . . . . . . 585 20.16.3.4 scenario 3.1: message gets overwritten indicated by semaphore bits and message lost. . . . . 585 20.16.3.5 scenario 3.2: message gets overwritten indicated by message lost . . . . . . . . . . . . . . . . . . . . . 586 20.16.3.6 scenario 4: clearing message lost bit . . . . 587 20.17 examples of acceptance filter tables and id index values. . . . . . . . . . . . . . . . . . . . . . . . . . 588 20.17.1 example 1: only one section is used . . . . . . 588 20.17.2 example 2: all sections are used . . . . . . . . . 588 20.17.3 example 3: more than one but not all sections are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 20.17.4 configuration example 4 . . . . . . . . . . . . . . . 589 20.17.5 configuration example 5 . . . . . . . . . . . . . . . 589 20.17.6 configuration example 6 . . . . . . . . . . . . . . . 590 explicit standard frame format identifier section (11-bit can id): . . . . . . . . . . . . . . . . . . . . . . . 591 group of standard frame format identifier section (11-bit can id): . . . . . . . . . . . . . . . . . . . . . . . 591 explicit extended frame format identifier section (29-bit can id, figure 98 ) . . . . . . . . . . . . . . . 591 group of extended frame format identifier section (29-bit can id, figure 98 ) . . . . . . . . . . . . . . . 591 20.17.7 configuration example 7 . . . . . . . . . . . . . . . 592 fullcan explicit standard frame format identifier section (11-bit can id) . . . . . . . . . . . . . . . . . 593 explicit standard frame format identifier section (11-bit can id) . . . . . . . . . . . . . . . . . . . . . . . 593 fullcan message object data section . . . . . . 593 20.17.8 look-up table programming guidelines . . . . 594 chapter 21: lpc408x/407x ssp interfaces 21.1 basic configuration . . . . . . . . . . . . . . . . . . . . 596 21.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 21.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 597 21.5 bus description . . . . . . . . . . . . . . . . . . . . . . . 598 21.5.1 texas instruments synchronous serial frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598 21.5.2 spi frame format . . . . . . . . . . . . . . . . . . . . . 598 21.5.2.1 clock polarity (cpol) and phase (cpha) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 21.5.2.2 spi format with cpol=0,cpha=0. . . . . . . . 599 21.5.2.3 spi format with cpol=0,cpha=1. . . . . . . . 600
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 936 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 21.5.2.4 spi format with cpol = 1,cpha = 0 . . . . . . 601 21.5.2.5 spi format with cpol = 1,cpha = 1 . . . . . . 602 21.5.3 national semiconductor microwire frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 21.5.3.1 setup and hold time requirements on cs with respect to sk in microwire mode . . . . . . . . . 604 21.6 register description . . . . . . . . . . . . . . . . . . . 605 21.6.1 sspn control register 0 . . . . . . . . . . . . . . . 606 21.6.2 sspn control register 1 . . . . . . . . . . . . . . . 607 21.6.3 sspn data register . . . . . . . . . . . . . . . . . . 607 21.6.4 sspn status register . . . . . . . . . . . . . . . . . 608 21.6.5 sspn clock prescale regi ster . . . . . . . . . . 608 21.6.6 sspn interrupt mask se t/clear register . . 609 21.6.7 sspn raw interrupt status register . . . . . . 609 21.6.8 sspn masked interrupt status register . . . 610 21.6.9 sspn interrupt clear regi ster . . . . . . . . . . . 610 21.6.10 sspn dma control register . . . . . . . . . . . . 610 chapter 22: lpc408x/407x i2c-bus interfaces 22.1 basic configuration . . . . . . . . . . . . . . . . . . . . 611 22.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 22.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 612 22.4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 22.4.1 i 2 c fast mode plus. . . . . . . . . . . . . . . . . . . 613 22.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 614 22.6 i 2 c operating modes . . . . . . . . . . . . . . . . . . . 614 22.6.1 master transmitter mode . . . . . . . . . . . . . . . 614 22.6.2 master receiver mode . . . . . . . . . . . . . . . . . 615 22.6.3 slave receiver mode . . . . . . . . . . . . . . . . . . 616 22.6.4 slave transmitter mode . . . . . . . . . . . . . . . . 617 22.7 i 2 c implementation and operation . . . . . . . . 618 22.7.1 input filters and output stages. . . . . . . . . . . . 618 22.7.2 address registers, i2adr0 to i2adr3 . . . . 620 22.7.3 address mask r egisters, i2mask0 to |2mask3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 22.7.4 comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 620 22.7.5 shift register, i2dat . . . . . . . . . . . . . . . . . . . 620 22.7.6 arbitration and synchronization logic . . . . . . 620 22.7.7 serial clock generator . . . . . . . . . . . . . . . . . . 621 22.7.8 timing and control . . . . . . . . . . . . . . . . . . . . 622 22.7.9 control register, i2conset and i2conclr 622 22.7.10 status decoder and status register . . . . . . . . 622 22.8 register description . . . . . . . . . . . . . . . . . . . 623 22.8.1 i 2 c control set register. . . . . . . . . . . . . . . . . 624 22.8.2 i 2 c control clear register . . . . . . . . . . . . . . 626 22.8.3 i 2 c status register . . . . . . . . . . . . . . . . . . . . 626 22.8.4 i 2 c data register . . . . . . . . . . . . . . . . . . . . . 627 22.8.5 i 2 c monitor mode control register . . . . . . . . 627 22.8.5.1 interrupt in monitor mode . . . . . . . . . . . . . . . 628 22.8.5.2 loss of arbitration in monitor mode . . . . . . . 628 22.8.6 i 2 c data buffer register . . . . . . . . . . . . . . . . 628 22.8.7 i 2 c slave address registers . . . . . . . . . . . . . 629 22.8.8 i 2 c mask registers . . . . . . . . . . . . . . . . . . . . 629 22.8.9 i 2 c scl high duty cycle regist er. . . . . . . . . 630 22.8.10 i 2 c scl low duty cycle register . . . . . . . . . 630 22.8.11 selecting the appropriate i 2 c data rate and duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630 22.9 details of i 2 c operating modes. . . . . . . . . . . 632 22.9.1 master transmitter mode . . . . . . . . . . . . . . . 633 22.9.2 master receiver mode . . . . . . . . . . . . . . . . . 635 22.9.3 slave receiver mode . . . . . . . . . . . . . . . . . . 637 22.9.4 slave transmitter mode . . . . . . . . . . . . . . . . 639 22.9.5 detailed state tables . . . . . . . . . . . . . . . . . . . 640 22.9.6 miscellaneous states . . . . . . . . . . . . . . . . . . 645 22.9.6.1 i2stat = 0xf8 . . . . . . . . . . . . . . . . . . . . . . . 645 22.9.6.2 i2stat = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 645 22.9.7 some special cases . . . . . . . . . . . . . . . . . . . 646 22.9.7.1 simultaneous repeated start conditions from two masters . . . . . . . . . . . . . . . . . . . . . . . . . 646 22.9.7.2 data transfer after loss of arbitration . . . . . . 646 22.9.7.3 forced access to the i 2 c-bus. . . . . . . . . . . . 646 22.9.7.4 i 2 c-bus obstructed by a low level on scl or sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 22.9.7.5 bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 22.9.8 i 2 c state service routines . . . . . . . . . . . . . . . 649 22.9.8.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . 649 22.9.8.2 i 2 c interrupt service . . . . . . . . . . . . . . . . . . . 649 22.9.8.3 the state service routines . . . . . . . . . . . . . . 649 22.9.8.4 adapting state services to an application. . . 649 22.10 software example . . . . . . . . . . . . . . . . . . . . . 650 22.10.1 initialization routine . . . . . . . . . . . . . . . . . . . 650 22.10.2 start master transmit function . . . . . . . . . . . 650 22.10.3 start master receive function . . . . . . . . . . . 650 22.10.4 i 2 c interrupt routine . . . . . . . . . . . . . . . . . . . 650 22.10.5 non mode specific states. . . . . . . . . . . . . . . 651 22.10.5.1 state: 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . 651 22.10.5.2 master states . . . . . . . . . . . . . . . . . . . . . . . . 651 22.10.5.3 state: 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . 651 22.10.5.4 state: 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . . 651 22.10.6 master transmitter states . . . . . . . . . . . . . . 652 22.10.6.1 state: 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . 652 22.10.6.2 state: 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . 652 22.10.6.3 state: 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . 652 22.10.6.4 state: 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . 652 22.10.6.5 state: 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . 653 22.10.7 master receiver states . . . . . . . . . . . . . . . . 654 22.10.7.1 state: 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.10.7.2 state: 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.10.7.3 state: 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.10.7.4 state: 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . 654 22.10.8 slave receiver states . . . . . . . . . . . . . . . . . 655 22.10.8.1 state: 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . 655 22.10.8.2 state: 0x68 . . . . . . . . . . . . . . . . . . . . . . . . . . 655 22.10.8.3 state: 0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . 655 22.10.8.4 state: 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . 655 22.10.8.5 state: 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . 656 22.10.8.6 state: 0x88 . . . . . . . . . . . . . . . . . . . . . . . . . . 656 22.10.8.7 state: 0x90 . . . . . . . . . . . . . . . . . . . . . . . . . . 656 22.10.8.8 state: 0x98 . . . . . . . . . . . . . . . . . . . . . . . . . . 656 22.10.8.9 state: 0xa0. . . . . . . . . . . . . . . . . . . . . . . . . . 656
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 937 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 22.10.9 slave transmitter states . . . . . . . . . . . . . . . . 657 22.10.9.1 state: 0xa8 . . . . . . . . . . . . . . . . . . . . . . . . . . 657 22.10.9.2 state: 0xb0 . . . . . . . . . . . . . . . . . . . . . . . . . . 657 22.10.9.3 state: 0xb8. . . . . . . . . . . . . . . . . . . . . . . . . . 657 22.10.9.4 state: 0xc0 . . . . . . . . . . . . . . . . . . . . . . . . . 657 22.10.9.5 state: 0xc8 . . . . . . . . . . . . . . . . . . . . . . . . . 658 chapter 23: lpc408x/407x i 2 s interface 23.1 basic configuration . . . . . . . . . . . . . . . . . . . . 659 23.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 23.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 23.4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . 662 23.5 register description . . . . . . . . . . . . . . . . . . . 664 23.5.1 digital audio output register. . . . . . . . . . . . . 665 23.5.2 digital audio input register . . . . . . . . . . . . . . 665 23.5.3 transmit fifo register . . . . . . . . . . . . . . . . . 666 23.5.4 receive fifo register . . . . . . . . . . . . . . . . . 666 23.5.5 status feedback register . . . . . . . . . . . . . . . 666 23.5.6 dma configuration register 1 . . . . . . . . . . . 667 23.5.7 dma configuration register 2 . . . . . . . . . . . 667 23.5.8 interrupt request control register . . . . . . . . 668 23.5.9 transmit clock rate register . . . . . . . . . . . . 668 23.5.9.1 notes on fractional rate generators . . . . . . . 669 23.5.10 receive clock rate register . . . . . . . . . . . . 669 23.5.11 transmit clock bit rate register . . . . . . . . . 670 23.5.12 receive clock bit rate register . . . . . . . . . 670 23.5.13 transmit mode control register . . . . . . . . . . 670 23.5.14 receive mode control register . . . . . . . . . . 671 23.6 i 2 s transmit and receive interfaces . . . . . . . 672 23.7 i 2 s operating modes . . . . . . . . . . . . . . . . . . . 673 23.7.1 i 2 s transmit modes. . . . . . . . . . . . . . . . . . . . 674 23.7.2 i 2 s receive modes . . . . . . . . . . . . . . . . . . . . 677 23.7.2.1 overall clocking and pin connections. . . . . . 680 23.8 fifo controller . . . . . . . . . . . . . . . . . . . . . . . 681 chapter 24: lpc408x/407x timer0/1/2/3 24.1 basic configuration . . . . . . . . . . . . . . . . . . . . 683 24.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 24.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 684 24.4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 24.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 686 24.5.1 multiple cap and mat pins . . . . . . . . . . . . . 686 24.6 register description . . . . . . . . . . . . . . . . . . . 687 24.6.1 interrupt register . . . . . . . . . . . . . . . . . . . . . 688 24.6.2 timer control register . . . . . . . . . . . . . . . . . 688 24.6.3 timer counter registers . . . . . . . . . . . . . . . . 689 24.6.4 prescale register . . . . . . . . . . . . . . . . . . . . . 689 24.6.5 prescale counter register . . . . . . . . . . . . . . 689 24.6.6 match control register . . . . . . . . . . . . . . . . 689 24.6.7 match registers (mr0 to mr3) . . . . . . . . . . 691 24.6.8 capture control register . . . . . . . . . . . . . . . 691 24.6.9 capture registers . . . . . . . . . . . . . . . . . . . . 692 24.6.10 external match register. . . . . . . . . . . . . . . . 693 24.6.11 count control register . . . . . . . . . . . . . . . . 695 24.6.12 dma operation . . . . . . . . . . . . . . . . . . . . . . . 696 24.7 example timer operation . . . . . . . . . . . . . . . 697 chapter 25: lpc408x/407x system tick timer 25.1 basic configuration . . . . . . . . . . . . . . . . . . . . 698 25.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 25.4 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 25.5 register description . . . . . . . . . . . . . . . . . . . 700 25.5.1 system timer control and status register . . 700 25.5.2 system timer reload value register. . . . . . . 700 25.5.3 system timer current value register . . . . . . 701 25.5.4 system timer calibration value register . . . 701 25.6 example timer calculations . . . . . . . . . . . . . 702 example 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 702 example 2). . . . . . . . . . . . . . . . . . . . . . . . . . . 702 example 3). . . . . . . . . . . . . . . . . . . . . . . . . . . 702 example 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 702 chapter 26: lpc408x/407x pulse width modulators (pwm0/1) 26.1 basic configuration . . . . . . . . . . . . . . . . . . . . 703 26.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 26.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 26.4 sample waveform with rules for single and double edge control. . . . . . . . . . . . . . . . . . . . 707 26.4.1 rules for single edge controlled pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.4.2 rules for double edge controlled pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 26.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 708 26.6 register description . . . . . . . . . . . . . . . . . . . 709 26.6.1 pwm interrupt register . . . . . . . . . . . . . . . 709 26.6.2 pwm timer control register . . . . . . . . . . . . 711 26.6.3 pwm timer counter . . . . . . . . . . . . . . . . . . . 711 26.6.4 pwm prescale register . . . . . . . . . . . . . . . 712 26.6.5 pwm prescale counter register . . . . . . . . . 712 26.6.6 pwm match control register . . . . . . . . . . . 712 26.6.7 pwm match registers . . . . . . . . . . . . . . . . 714 26.6.8 pwm capture control register . . . . . . . . . . 715 26.6.9 pwm capture registers . . . . . . . . . . . . . . . 715 26.6.10 pwm control registers . . . . . . . . . . . . . . . 716 26.6.11 pwm latch enable register . . . . . . . . . . . . 717 26.6.12 pwm count control register . . . . . . . . . . . 719
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 938 of 942 nxp semiconductors UM10562 chapter 41: supplementary information chapter 27: lpc408x/407x motor control pwm 27.1 basic configuration . . . . . . . . . . . . . . . . . . . . 720 27.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 720 27.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 27.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 721 27.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 722 27.6 configuring other modules for mcpwm use 723 27.7 general operation . . . . . . . . . . . . . . . . . . . . . 723 27.8 register description . . . . . . . . . . . . . . . . . . . 724 27.8.1 mcpwm control register . . . . . . . . . . . . . . . 725 27.8.1.1 mcpwm control read address . . . . . . . . . . 725 27.8.1.2 mcpwm control set address . . . . . . . . . . . 726 27.8.1.3 mcpwm control clear address . . . . . . . . . . 727 27.8.2 pwm capture control register . . . . . . . . . . . 728 27.8.2.1 mcpwm capture control read address . . . 728 27.8.2.2 mcpwm capture control set address . . . . 729 27.8.2.3 mcpwm capture control clear address . . . 729 27.8.3 mcpwm timer/counter 0-2 registers . . . . . 730 27.8.4 mcpwm limit 0-2 registers . . . . . . . . . . . . . 731 27.8.5 mcpwm match 0-2 registers . . . . . . . . . . . . 731 27.8.5.1 match register in edge-aligned mode. . . . . . 732 27.8.5.2 match register in center-aligned mode . . . . 732 27.8.5.3 0 and 100% duty cycle . . . . . . . . . . . . . . . . . 732 27.8.6 mcpwm dead-time register . . . . . . . . . . . . 732 27.8.7 mcpwm communication pattern register . . 733 27.8.8 mcpwm capture read addresses . . . . . . . . 733 27.8.9 mcpwm interrupt registers . . . . . . . . . . . . . 734 8.9.1 mcpwm interrupt enable read address . . . 734 27.8.9.2 mcpwm interrupt enable set address . . . . 735 27.8.9.3 mcpwm interrupt enable clear address . . 735 27.8.10 mcpwm count control register . . . . . . . . . 736 27.8.10.1 mcpwm count control read address . . . . 736 27.8.10.2 mcpwm count control set address . . . . . . 738 27.8.10.3 mcpwm count control clear address . . . . 739 27.8.11 mcpwm interrupt flag registers. . . . . . . . . . 739 27.8.11.1 mcpwm interrupt flags read address . . . . 739 27.8.11.2 mcpwm interrupt flags set address . . . . . 741 27.8.11.3 mcpwm interrupt flags clear address . . . . 741 27.8.12 mcpwm capture clear address . . . . . . . . . 742 27.9 pwm operation . . . . . . . . . . . . . . . . . . . . . . . 743 27.9.1 pulse-width modulation . . . . . . . . . . . . . . . . 743 edge-aligned pwm without dead-time. . . . . . 743 center-aligned pwm without dead-time . . . . 743 dead-time counter . . . . . . . . . . . . . . . . . . . . . 744 27.9.2 shadow registers and simultaneous updates 745 27.9.3 fast abort (abort). . . . . . . . . . . . . . . . . . . 745 27.9.4 capture events. . . . . . . . . . . . . . . . . . . . . . . 745 27.9.5 external event counting (counter mode) . . . 746 27.9.6 three-phase dc mode . . . . . . . . . . . . . . . . 746 27.9.7 three phase ac mode. . . . . . . . . . . . . . . . . 747 27.9.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 chapter 28: lpc408x/407x quadrature encoder interface (qei) 28.1 how to read this chapter . . . . . . . . . . . . . . . . 749 28.2 basic configuration . . . . . . . . . . . . . . . . . . . . 749 28.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 28.4 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 750 28.5 functional description . . . . . . . . . . . . . . . . . 751 28.5.1 input signals . . . . . . . . . . . . . . . . . . . . . . . . . 751 28.5.1.1 quadrature input signals . . . . . . . . . . . . . . . 751 28.5.1.2 digital input filtering . . . . . . . . . . . . . . . . . . . 752 28.5.2 position capture . . . . . . . . . . . . . . . . . . . . . . 752 28.5.3 velocity capture . . . . . . . . . . . . . . . . . . . . . . 753 28.5.4 velocity compare . . . . . . . . . . . . . . . . . . . . . 753 28.6 pin description . . . . . . . . . . . . . . . . . . . . . . . . 754 28.7 register description . . . . . . . . . . . . . . . . . . . 755 28.7.1 register summary . . . . . . . . . . . . . . . . . . . . 755 28.7.2 control registers . . . . . . . . . . . . . . . . . . . . . . 756 28.7.2.1 qei control register . . . . . . . . . . . . . . . . . . . 756 28.7.2.2 qei configuration register . . . . . . . . . . . . . . 756 28.7.2.3 qei status register . . . . . . . . . . . . . . . . . . . . 756 28.7.3 position, index and timer registers . . . . . . . . 757 28.7.3.1 qei position register . . . . . . . . . . . . . . . . . . 757 28.7.3.2 qei maximum position register . . . . . . . . . . 757 28.7.3.3 qei position compare register 0 . . . . . . . . . 757 28.7.3.4 qei position compare register 1 . . . . . . . . 757 28.7.3.5 qei position compare register 2 . . . . . . . . 758 28.7.3.6 qei index count register . . . . . . . . . . . . . . 758 28.7.3.7 qei index compare register 0 . . . . . . . . . . 758 28.7.3.8 qei velocity timer reload register . . . . . . . 758 28.7.3.9 qei velocity timer register . . . . . . . . . . . . . 758 28.7.3.10 qei velocity register . . . . . . . . . . . . . . . . . . 759 28.7.3.11 qei velocity capture register . . . . . . . . . . . 759 28.7.3.12 qei velocity compare register. . . . . . . . . . . 759 28.7.3.13 qei digital filter on pha . . . . . . . . . . . . . . 759 28.7.3.14 qei digital filter on phb . . . . . . . . . . . . . . 759 28.7.3.15 qei digital filter on inx . . . . . . . . . . . . . . . 760 28.7.3.16 qei index acceptance window . . . . . . . . . . 760 28.7.3.17 qei index compare register 1 . . . . . . . . . . 760 28.7.3.18 qei index compare register 2 . . . . . . . . . . . 760 28.7.4 interrupt registers. . . . . . . . . . . . . . . . . . . . . 761 28.7.4.1 qei interrupt status register . . . . . . . . . . . . 761 28.7.4.2 qei interrupt set register . . . . . . . . . . . . . . 762 28.7.4.3 qei interrupt clear register . . . . . . . . . . . . . 763 28.7.4.4 qei interrupt enable register . . . . . . . . . . . 764 28.7.4.5 qei interrupt enable set register. . . . . . . . . 765 28.7.4.6 qei interrupt enable clear register . . . . . . . 766 chapter 29: lpc408x/407x real time clock (rtc) 29.1 basic configuration . . . . . . . . . . . . . . . . . . . . 767 29.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 939 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 29.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 29.4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 768 29.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 769 29.6 register description . . . . . . . . . . . . . . . . . . . 769 29.6.1 rtc interrupts . . . . . . . . . . . . . . . . . . . . . . . 771 29.6.2 miscellaneous register group . . . . . . . . . . . . 771 29.6.2.1 interrupt location register . . . . . . . . . . . . . . 771 29.6.2.2 clock control register . . . . . . . . . . . . . . . . . 771 29.6.2.3 counter increment interrupt register . . . . . . 772 29.6.2.4 alarm mask register . . . . . . . . . . . . . . . . . . 772 29.6.2.5 rtc auxiliary control register . . . . . . . . . . . 773 29.6.2.6 rtc auxiliary enable register. . . . . . . . . . . . 773 29.6.3 consolidated time registers . . . . . . . . . . . . . 773 29.6.3.1 consolidated time register 0 . . . . . . . . . . . 774 29.6.3.2 consolidated time register 1 . . . . . . . . . . . 774 29.6.3.3 consolidated time register 2 . . . . . . . . . . . 774 29.6.4 time counter group . . . . . . . . . . . . . . . . . . 774 29.6.4.1 leap year calculation . . . . . . . . . . . . . . . . . . 776 29.6.4.2 calibration register. . . . . . . . . . . . . . . . . . . . 776 29.6.5 calibration procedure. . . . . . . . . . . . . . . . . . 777 backward calibration . . . . . . . . . . . . . . . . . . . 777 forward calibration . . . . . . . . . . . . . . . . . . . . 777 29.6.6 general purpose registers . . . . . . . . . . . . . 778 29.6.6.1 general purpose registers 0 to 4 . . . . . . . . 778 29.6.7 alarm register group . . . . . . . . . . . . . . . . . . 778 29.7 rtc usage notes. . . . . . . . . . . . . . . . . . . . . . 780 chapter 30: lpc408x/407x event monitor/recorder 30.1 basic configuration . . . . . . . . . . . . . . . . . . . . 781 30.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 30.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 781 30.4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 782 30.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 784 30.6 register description . . . . . . . . . . . . . . . . . . . 784 30.6.1 event monitor/recorder control register . . 785 30.6.2 event monitor/recorder status register . . . 787 30.6.3 event monitor/recorder counters register . 788 30.6.4 event monitor/recorder first stamp register 788 30.6.5 event monitor/recorder last stamp register 788 chapter 31: lpc408x/407x windowed watchdog timer (wwdt) 31.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 31.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . 790 31.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 791 31.4 register description . . . . . . . . . . . . . . . . . . . 793 31.4.1 watchdog mode register . . . . . . . . . . . . . . . 794 wdtof . . . . . . . . . . . . . . . . . . . . . . . . . . . . .794 wdint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .794 wdprotect . . . . . . . . . . . . . . . . . . . . . . . . 794 31.4.2 watchdog timer constant register . . . . . . . 795 31.4.3 watchdog feed register. . . . . . . . . . . . . . . . 795 31.4.4 watchdog timer value register . . . . . . . . . . 796 31.4.5 watchdog timer warning interrupt register 796 31.4.6 watchdog timer window register . . . . . . . . 796 31.5 watchdog timing examples . . . . . . . . . . . . . 797 chapter 32: lpc408x/407x analog-to-digital converter (adc) 32.1 basic configuration . . . . . . . . . . . . . . . . . . . . 799 32.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 32.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 32.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 800 32.5 register description . . . . . . . . . . . . . . . . . . . 801 32.5.1 a/d control register . . . . . . . . . . . . . . . . . . 802 32.5.2 a/d global data register . . . . . . . . . . . . . . 803 32.5.3 a/d interrupt enable register . . . . . . . . . . . . 804 32.5.4 a/d data registers . . . . . . . . . . . . . . . . . . . 805 32.5.5 a/d status register . . . . . . . . . . . . . . . . . . . . 806 32.5.6 a/d trim register . . . . . . . . . . . . . . . . . . . . . 807 32.6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 32.6.1 hardware-triggered conversion . . . . . . . . . . 808 32.6.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 32.6.3 accuracy vs. digital receiver . . . . . . . . . . . . 808 32.6.4 dma control . . . . . . . . . . . . . . . . . . . . . . . . . 808 chapter 33: lpc408x/407x digital-to-analog converter (dac) 33.1 basic configuration . . . . . . . . . . . . . . . . . . . . 809 33.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 33.3 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 810 33.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 810 33.5 register description . . . . . . . . . . . . . . . . . . . 811 33.5.1 d/a converter register . . . . . . . . . . . . . . . . . 811 33.5.2 d/a converter control register. . . . . . . . . . . . 811 33.5.3 d/a converter counter value register . . . . . 812 33.6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 33.6.1 dma counter . . . . . . . . . . . . . . . . . . . . . . . . 813 33.6.2 double buffering. . . . . . . . . . . . . . . . . . . . . . 813 chapter 34: lpc408x/407x comparators 34.1 how to read this chapter . . . . . . . . . . . . . . . . 814 34.2 basic configuration . . . . . . . . . . . . . . . . . . . . 814 34.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 34.4 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 815
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 940 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 34.5 pin description . . . . . . . . . . . . . . . . . . . . . . . . 817 34.6 register description . . . . . . . . . . . . . . . . . . . 817 34.6.1 comparator block control register. . . . . . . . . 818 34.6.2 comparator 0 control register . . . . . . . . . . . 819 34.6.3 comparator 1 control register . . . . . . . . . . . 822 34.6.4 comparator interrupt configurations . . . . . . 824 chapter 35: lpc408x/407x general purpose dma controller 35.1 basic configuration . . . . . . . . . . . . . . . . . . . . 825 35.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 825 35.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 35.4 functional description . . . . . . . . . . . . . . . . . 827 35.4.1 dma controller functional description . . . . . . 827 35.4.1.1 ahb slave interface . . . . . . . . . . . . . . . . . . . 827 35.4.1.2 control logic and register bank . . . . . . . . . . . 827 35.4.1.3 dma request and response interface . . . . . . 827 35.4.1.4 channel logic and channel register bank . . . 827 35.4.1.5 interrupt request . . . . . . . . . . . . . . . . . . . . . . 828 35.4.1.6 ahb master interface . . . . . . . . . . . . . . . . . . 828 35.4.1.6.1 bus and transfer widths . . . . . . . . . . . . . . . . 828 35.4.1.6.2 endian behavior . . . . . . . . . . . . . . . . . . . . . . 828 35.4.1.6.3 error conditions . . . . . . . . . . . . . . . . . . . . . . 830 35.4.1.7 channel hardware . . . . . . . . . . . . . . . . . . . . 830 35.4.1.8 dma request priority . . . . . . . . . . . . . . . . . . . 830 35.4.1.9 interrupt generation . . . . . . . . . . . . . . . . . . . 831 35.4.2 dma system connections . . . . . . . . . . . . . . . 831 35.4.2.1 dma request signals . . . . . . . . . . . . . . . . . . 831 35.4.2.2 dma response signals . . . . . . . . . . . . . . . . . 831 35.4.2.3 dma request connections . . . . . . . . . . . . . . 831 35.5 register description . . . . . . . . . . . . . . . . . . . 833 35.5.1 dma interrupt status register . . . . . . . . . . . 835 35.5.2 dma interrupt terminal count request status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 35.5.3 dma interrupt terminal count request clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 35.5.4 dma interrupt error status register . . . . . . . 835 35.5.5 dma interrupt error clear register . . . . . . . . 836 35.5.6 dma raw interrupt terminal count status register 836 35.5.7 dma raw error interrupt status register . . . 837 35.5.8 dma enabled channel register . . . . . . . . . . 837 35.5.9 dma software burst request register . . . . . 837 35.5.10 dma software single request register . . . . 838 35.5.11 dma software last burst request register . 838 35.5.12 dma software last single request register 839 35.5.13 dma configuration register . . . . . . . . . . . . . 839 35.5.14 dma synchronization register . . . . . . . . . . . 839 35.5.15 dma channel registers . . . . . . . . . . . . . . . . 840 35.5.16 dma channel source address registers . . 840 35.5.17 dma channel destination address registers 841 35.5.18 dma channel linked list item registers . . . 841 35.5.19 dma channel control registers. . . . . . . . . . . 841 35.5.19.1 protection and access information. . . . . . . . 841 35.5.20 dma channel configuration registers . . . . . 844 35.5.20.1 lock control . . . . . . . . . . . . . . . . . . . . . . . . . 845 35.5.20.2 transfer type . . . . . . . . . . . . . . . . . . . . . . . . 845 35.6 using the dma controller . . . . . . . . . . . . . . . 846 35.6.1 programming the dma controller. . . . . . . . . 846 35.6.1.1 enabling the dma controller . . . . . . . . . . . . 846 35.6.1.2 disabling the dma controller . . . . . . . . . . . . 846 35.6.1.3 enabling a dma channel . . . . . . . . . . . . . . . 846 35.6.1.4 disabling a dma channel. . . . . . . . . . . . . . . 846 disabling a dma channel and losing data in the fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 disabling the dma channel without losing data in the fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 35.6.1.5 setting up a new dma transfer . . . . . . . . . . 846 35.6.1.6 halting a dma channel . . . . . . . . . . . . . . . . 847 35.6.1.7 programming a dma channel . . . . . . . . . . . 847 35.6.2 flow control . . . . . . . . . . . . . . . . . . . . . . . . . 847 35.6.2.1 peripheral-to-memory or memory-to-peripheral dma flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 35.6.2.2 peripheral-to-peripheral dma flow. . . . . . . . 848 35.6.2.3 memory-to-memory dma flow . . . . . . . . . . . 849 35.6.3 interrupt requests . . . . . . . . . . . . . . . . . . . . . 849 35.6.3.1 hardware interrupt sequence flow . . . . . . . . 850 35.6.4 address generation . . . . . . . . . . . . . . . . . . . 850 35.6.4.1 word-aligned transfers across a boundary . 850 35.6.5 scatter/gather . . . . . . . . . . . . . . . . . . . . . . . 850 35.6.5.1 linked list items . . . . . . . . . . . . . . . . . . . . . . 851 35.6.5.1.1 programming the dma controller for scatter/gather dma . . . . . . . . . . . . . . . . . . . 851 35.6.5.1.2 example of scatter/gather dma. . . . . . . . . . 851 chapter 36: lpc408x/407x crc engine 36.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 854 36.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 36.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 36.4 register description . . . . . . . . . . . . . . . . . . . 856 36.4.1 crc mode register . . . . . . . . . . . . . . . . . . . 856 36.4.2 crc seed register . . . . . . . . . . . . . . . . . . . . 856 36.4.3 crc checksum register . . . . . . . . . . . . . . . 857 36.4.4 crc data register . . . . . . . . . . . . . . . . . . . . 857 36.5 functional description . . . . . . . . . . . . . . . . . 858 crc-ccitt set-up . . . . . . . . . . . . . . . . . . . . 858 crc-16 set-up . . . . . . . . . . . . . . . . . . . . . . . . 858 crc-32 set-up . . . . . . . . . . . . . . . . . . . . . . . . 858 chapter 37: lpc408x/407x eeprom memory 37.1 basic configuration . . . . . . . . . . . . . . . . . . . . 859 37.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . 859
UM10562 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. user manual rev. 1 ? 13 september 2012 941 of 942 nxp semiconductors UM10562 chapter 41: supplementary information 37.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 37.4 eeprom operation . . . . . . . . . . . . . . . . . . . . 860 37.4.1 eeprom device description . . . . . . . . . . . . 860 37.4.2 eeprom operations . . . . . . . . . . . . . . . . . . 860 37.4.2.1 writing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 37.4.2.2 erase/programming . . . . . . . . . . . . . . . . . . . 862 37.4.2.3 reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862 37.4.2.4 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . 863 37.5 register description . . . . . . . . . . . . . . . . . . . 864 37.5.1 eeprom control registers . . . . . . . . . . . . . . 865 37.5.1.1 eeprom command register . . . . . . . . . . . . 865 37.5.1.2 eeprom addre ss register . . . . . . . . . . . . . . 865 37.5.1.3 eeprom write data register. . . . . . . . . . . . . 866 37.5.1.4 eeprom read data register . . . . . . . . . . . . 866 37.5.1.5 eeprom wait st ate register . . . . . . . . . . . . 867 example with cclk=120 mhz: . . . . . . . . . . . . . 867 37.5.1.6 eeprom clock divider register . . . . . . . . . . 867 37.5.1.7 eeprom power down register . . . . . . . . . . 868 37.5.2 interrupt registers. . . . . . . . . . . . . . . . . . . . . 869 37.5.2.1 interrupt status register . . . . . . . . . . . . . . . . 869 37.5.2.2 interrupt status clear register . . . . . . . . . . . . 869 37.5.2.3 interrupt status set . . . . . . . . . . . . . . . . . . . . 870 37.5.2.4 interrupt enable register. . . . . . . . . . . . . . . . 870 37.5.2.5 interrupt enable clear register . . . . . . . . . . . 870 37.5.2.6 interrupt enable set register . . . . . . . . . . . . . 871 chapter 38: lpc408x/407x flash memory 38.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 872 38.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 38.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 38.3.1 memory map after any reset. . . . . . . . . . . . . 873 38.3.1.1 criterion for valid user code . . . . . . . . . . . . 873 38.3.2 communication protocol . . . . . . . . . . . . . . . . 875 38.3.2.1 isp command format . . . . . . . . . . . . . . . . . . 875 38.3.2.2 isp response format . . . . . . . . . . . . . . . . . . . 875 38.3.2.3 isp data format. . . . . . . . . . . . . . . . . . . . . . . 875 38.3.2.4 isp flow control. . . . . . . . . . . . . . . . . . . . . . . 875 38.3.2.5 isp command abort . . . . . . . . . . . . . . . . . . . 875 38.3.2.6 interrupts during iap. . . . . . . . . . . . . . . . . . . 875 38.3.2.7 addresses in iap and isp commands . . . . . 875 38.3.2.8 ram used by isp command . . . . . . . . . . . . 876 38.3.2.9 ram used by boot pr ocess prior to entering user program . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876 38.3.2.10 ram used by iap command handler . . . . . . 876 38.4 boot process flowchart . . . . . . . . . . . . . . . . . 877 38.5 sector numbers . . . . . . . . . . . . . . . . . . . . . . . 878 38.6 code read protection (crp) . . . . . . . . . . . . 879 38.7 isp commands . . . . . . . . . . . . . . . . . . . . . . . . 881 38.7.1 unlock . . . . . . . . . . . . . . . . . 881 38.7.2 set baud rate . . . . 882 38.7.3 echo . . . . . . . . . . . . . . . . . . . . . . . 882 38.7.4 write to ram . . . . . . . . . . . . . . . . . . . . 882 38.7.5 read memory
. . . 883 38.7.6 prepare sector(s) for write operation . . . . . . . . . . 884 38.7.7 copy ram to flash . . . . . . . . . . . . . . . . 884 38.7.8 go
. . . . . . . . . . . . . . . . . 885 38.7.9 erase sector(s) . . . . . . . . . . . . . . . . . . . . . . 885 38.7.10 blank check sector(s) . . . . . . . . . . . . . . . . . . . . . . 886 38.7.11 read part identification number . . . . . . . . . 886 38.7.12 read boot code version number. . . . . . . . . 886 38.7.13 read device serial number . . . . . . . . . . . . . 887 38.7.14 compare . . . . . . . . . . . . . . . . . . . . . . . . 887 38.7.15 isp return codes . . . . . . . . . . . . . . . . . . . . 888 38.8 iap commands . . . . . . . . . . . . . . . . . . . . . . . 889 38.8.1 prepare sector(s) for write operation . . . . . . 891 38.8.2 copy ram to flash . . . . . . . . . . . . . . . . . . . 891 38.8.3 erase sector(s) . . . . . . . . . . . . . . . . . . . . . . 892 38.8.4 blank check sector(s). . . . . . . . . . . . . . . . . . 892 38.8.5 read part identification number . . . . . . . . . . 892 38.8.6 read boot code version number. . . . . . . . . 893 38.8.7 read device serial number . . . . . . . . . . . . . 893 38.8.8 compare . . . . . . . . . . . . . . . . . . . . . . . . 893 38.8.9 re-invoke isp . . . . . . . . . . . . . . . . . . . . . . . 894 38.8.10 iap status codes . . . . . . . . . . . . . . . . . . . . . 894 38.9 jtag flash programming interface . . . . . . . 895 38.10 flash signature generation . . . . . . . . . . . . . 895 38.10.1 register description for signature generation 895 38.10.1.1 signature generation address and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 38.10.1.2 signature generation result registers . . . . . . 896 38.10.1.3 flash module status register . . . . . . . . . . . 897 38.10.1.4 flash module status clear register . . . . . . . 897 38.10.2 algorithm and procedure for signature generation . . . . . . . . . . . . . . . . . . . . . . . . . . 898 signature generation . . . . . . . . . . . . . . . . . . . 898 content verification . . . . . . . . . . . . . . . . . . . . 898 chapter 39: lpc408x/407x jtag, debug, and trace 39.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 39.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 899 39.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . 899 39.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . 900 39.5 debug connections. . . . . . . . . . . . . . . . . . . . 901 39.6 jtag tap identification . . . . . . . . . . . . . . . . 902 39.7 debug notes . . . . . . . . . . . . . . . . . . . . . . . . . 903 39.8 debug memory re-mapping . . . . . . . . . . . . . 903
nxp semiconductors UM10562 chapter 41: supplementary information ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 13 september 2012 document identifier: UM10562 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 942 39.8.1 memory mapping control register . . . . . . . . 903 chapter 40: arm cortex-m4 appendix 40.1 arm cortex-m4 details . . . . . . . . . . . . . . . . . 904 40.1.1 cortex-m4 implementation options . . . . . . . 904 chapter 41: supplementary information 41.1 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 906 41.2 legal information. . . . . . . . . . . . . . . . . . . . . . 907 41.2.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 907 41.2.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 907 41.2.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 907 41.3 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908 41.4 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923 41.5 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926

▲Up To Search▲

Price & Availability of UM10562

	To Download UM10562 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .